BQ25150 是一款高度集成的电池充电管理 IC,它集成了用于可穿戴设备的常用功能,即充电器、输出电压轨、用于电池和系统监控的 ADC 以及按钮控制器。
器件型号 (1) | 封装 | 封装尺寸(标称值) |
---|---|---|
BQ25150 | DSBGA (20) | 2.00mm x 1.60mm |
Changes from Revision B (February 2019) to Revision C (April 2023)
Changes from Revision A (October 2018) to Revision B (February 2019)
Changes from Revision * (July 2018) to Revision A (October 2018)
BQ25150 IC 集成了可以对小型电池进行快速准确充电的线性充电器。该器件支持高达 500 mA 的充电电流并支持低至 0.5 mA 的终止电流,从而实现最充分的充电。该器件采用标准锂离子充电曲线分三个阶段对电池进行充电:预充电、恒流和恒压调节。
该器件集成了高级电源路径管理和控制,使该器件可以为系统提供电源,同时甚至能够使用很差的适配器为电池充电。主机还可以通过 I2C 控制电源路径,允许它断开输入适配器和/或电池,而无需实际移除它们。单按钮输入无需单独的按钮控制器 IC,从而减少了整体解决方案占用空间。按钮输入可用于唤醒功能或重置系统。12 位有效 ADC 可实现精确的电池电压监控,并可用于实现低 Iq 监测,以监控电池运行状况。它还可用于使用连接到 TS 引脚的热敏电阻以及外部系统信号(通过 ADCIN 引脚)来测量电池温度。运行和关断期间的低静态电流有助于延长电池寿命。可通过 I2C 接口对输入电流限制、充电电流、LDO 输出电压和其他参数进行编程,从而使 BQ25150 成为非常灵活的充电解决方案。该器件包含一个基于电压的 JEITA 兼容(或标准热/冷)电池组热敏电阻监控输入 (TS),可监控电池温度并自动更改充电参数,从而防止电池在超出其安全温度范围的温度下充电。还可以通过 I2C 对温度阈值进行编程,从而使主机能够自定义热负荷曲线。该充电器针对 5V USB 输入进行了优化,具有 20V 的绝对最大容差,可承受线路瞬变。该器件还集成了一个用于为无线电或处理器提供静态轨的线性稳压器,可以通过 I2C 独立地为其提供电源并对其进行控制。
DEFAULT SETTING | BQ25150 | BQ25155 |
---|---|---|
Fast Charge Current (ICHARGE) | 10 mA | 10 mA |
Pre-Charge Current (IPRECHARGE) | 2.5 mA | 2.5 mA |
Termination Current (ITERM) | 10% of ICHARGE | 10%of ICHARGE |
Input Current Ljmit (IILIM) | 100 mA | 500 mA |
VIN DPM | Enabled | Disabled |
LDO Output Voltage (VLDO) | 1.8 V | 1.8 V |
Ship Mode Wake Timer | 2 seconds | 0.125 seconds |
DEVICE_ID | 0x20h | 0x35h |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN | A1 | I | DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 µF of capacitance using a ceramic capacitor. |
PMID | A2, B2 | I/O | High Side Bypass Connection. Connect at least 10-µF ceramic capacitor (at least 3 µF of ceramic capacitance with DC bias de-rating) from PMID to GND as close to the PMID and GND pins as possible. Note: Shorting PMID to IN pin is not recommended as it may cause large discharge current from battery to IN if IN pin is not truly floating. |
GND | A4 | PWR | Ground connection. Connect to the ground plane of the circuit. |
VDD | D1 | O | Digital supply LDO. Connect at least 4.7-µF capacitor to ground. |
CE | C2 | I | Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid. Drive CE high to disable charge when VIN is present. CE is pulled low internally with 900-kΩ resistor. CE has no effect when VIN is not present. |
SCL | E3 | I/O | I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
SDA | E2 | I | I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor. |
LP | D3 | I | Low Power Mode Enable. Drive this pin low to set the device in low power mode when powered by the battery. This pin must be driven high to allow I2C communication when VIN is not present. LP is pulled low internally with 900-kΩ resistor. This pin has no effect when VIN is present. |
IMAX | C3 | I | Connect a 10-kΩ or lower resistor to this pin to set the maximum allowable fast charge current. Must not be left floating. |
INT | D2 | O | INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-µs pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in the control register. |
ADCIN | C4 | I | Input Channel to the ADC. Maximum ADC range 1.2 V. Leave floating or connect to ground if not used. |
MR | C1 | I | Manual Reset Input. MR is a general purpose input that must be held low for greater than tHWRESET to go into HW Reset and power cycle the output rails. If MR is also used to wake up the device out of Ship Mode when pressed for at least tWAKE2. MR has in internal 125-kΩ pull-up resistor to BAT. |
LS/LDO | D4 | O | Load Switch or LDO output. Connect 2.2 µF of ceramic capacitance to this pin to assure stability. Be sure to account for capacitance bias voltage derating when selecting the capacitor. If LDO is not to be used,, the pin may be shorted to VINLS |
VINLS | E4 | I | Input to the Load Switch / LDO output. Connect at least 1 µF of ceramic capacitance from this pin to ground. |
BAT | A3, B3 | I/O | Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 µF of ceramic capacitance. |
TS | B4 | I | Battery Pack NTC Monitor. Connect TS to a 10-kΩ NTC Thermistor in parallel to a 10-kΩ resistor. If TS function is not to be used connect a 5-kΩ resistor from TS to ground. |
PG | B1 | O | Open-drain Power Good status indication output. PG is pulled to GND when VIN is above VBAT+ VSLP and less than VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication. PG can also be configured through I2C as a push-button level shifted output ( MR), where the output of the PG pin reflects the status of the MR input, but pulled up to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor. The PG pin can also be configured as a general purpose open drain output. |
VIO | E1 | I | System IO supply. Connect to system IO supply to allow level shifting of input signals (SDA, SCL, LP and CE) to the device internal digital domain. Connect to VDD when external IO supply is not available. |