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  • CC3235S 和 CC3235SF SimpleLink™ Wi-Fi® 双频带单芯片解决方案

    • ZHCSJC1E April   2019  – December 2024 CC3235S , CC3235SF

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  • CC3235S 和 CC3235SF SimpleLink™ Wi-Fi® 双频带单芯片解决方案
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
    4. 6.4 Pin Multiplexing
    5. 6.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 6.6 Pad State After Application of Power to Device, Before Reset Release
    7. 6.7 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary (CC3235S)
      1.      24
      2.      25
    6. 7.6  Current Consumption Summary (CC3235SF)
      1.      27
      2.      28
    7. 7.7  TX Power Control for 2.4 GHz Band
    8. 7.8  TX Power Control for 5 GHz
    9. 7.9  Brownout and Blackout Conditions
    10. 7.10 Electrical Characteristics for GPIO Pins
      1.      33
      2.      34
    11. 7.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 7.12 WLAN Receiver Characteristics
      1.      37
      2.      38
    13. 7.13 WLAN Transmitter Characteristics
      1.      40
      2.      41
    14. 7.14 WLAN Transmitter Out-of-Band Emissions
      1.      43
      2.      44
    15. 7.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 7.16 Thermal Resistance Characteristics for RGK Package
    17. 7.17 Timing and Switching Characteristics
      1. 7.17.1 Power Supply Sequencing
      2. 7.17.2 Device Reset
      3. 7.17.3 Reset Timing
        1. 7.17.3.1 nRESET (32kHz Crystal)
        2.       52
        3.       53
        4. 7.17.3.2 nRESET (External 32kHz Clock)
          1.        55
      4. 7.17.4 Wakeup From HIBERNATE Mode
      5. 7.17.5 Clock Specifications
        1. 7.17.5.1 Slow Clock Using Internal Oscillator
        2. 7.17.5.2 Slow Clock Using an External Clock
          1.        60
        3. 7.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        62
        4. 7.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        64
      6. 7.17.6 Peripherals Timing
        1. 7.17.6.1  SPI
          1. 7.17.6.1.1 SPI Master
            1.         68
          2. 7.17.6.1.2 SPI Slave
            1.         70
        2. 7.17.6.2  I2S
          1. 7.17.6.2.1 I2S Transmit Mode
            1.         73
          2. 7.17.6.2.2 I2S Receive Mode
            1.         75
        3. 7.17.6.3  GPIOs
          1. 7.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3V)
            1.         78
          2. 7.17.6.3.2 GPIO Input Transition Time Parameters
            1.         80
        4. 7.17.6.4  I2C
          1.        82
        5. 7.17.6.5  IEEE 1149.1 JTAG
          1.        84
        6. 7.17.6.6  ADC
          1.        86
        7. 7.17.6.7  Camera Parallel Port
          1.        88
        8. 7.17.6.8  UART
        9. 7.17.6.9  SD Host
        10. 7.17.6.10 Timers
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 8.3  Wi-Fi® Network Processor Subsystem
      1. 8.3.1 WLAN
      2. 8.3.2 Network Stack
    4. 8.4  Security
    5. 8.5  FIPS 140-2 Level 1 Certification
    6. 8.6  Power-Management Subsystem
    7. 8.7  Low-Power Operating Mode
    8. 8.8  Memory
      1. 8.8.1 External Memory Requirements
      2. 8.8.2 Internal Memory
        1. 8.8.2.1 SRAM
        2. 8.8.2.2 ROM
        3. 8.8.2.3 Flash Memory
        4. 8.8.2.4 Memory Map
    9. 8.9  Restoring Factory Default Configuration
    10. 8.10 Boot Modes
      1. 8.10.1 Boot Mode List
    11. 8.11 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1  第三方产品免责声明
    2. 10.2  Tools and Software
    3. 10.3  Firmware Updates
    4. 10.4  Device Nomenclature
    5. 10.5  Documentation Support
    6. 10.6  Related Links
    7. 10.7  支持资源
    8. 10.8  Trademarks
    9. 10.9  静电放电警告
    10. 10.10 Export Control Notice
    11. 10.11 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Packaging Option Addendum
  14. 重要声明
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Data Sheet

CC3235S 和 CC3235SF SimpleLink™ Wi-Fi® 双频带单芯片解决方案

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

下载最新的英语版本

1 特性

  • 多核心架构，片上系统 (SoC)
  • 802.11 a/b/g/n：2.4GHz 和 5GHz
  • FIPS 140-2 1 级认证
  • 多层安全特性可帮助开发人员保护身份信息、数据和软件 IP
  • 低功耗模式，适用于电池供电应用
  • 与 2.4GHz 无线电共存
  • 工业温度：-40°C 至 +85°C
  • 获得 Wi-Fi Alliance® 的 Wi-Fi CERTIFIED®
  • 应用微控制器子系统：
    • 运行频率为 80MHz 的 Arm®Cortex®-M4 内核
    • 用户专用存储器
      • 256KB RAM
      • 可选的 1MB 可执行闪存
    • 多种外设和计时器
    • 27 个带灵活多路复用选项的 I/O 引脚
      • UART、I2S、I2C、SPI、SD、ADC，
        8 位并行接口
      • 计时器和 PWM
  • Wi-Fi 网络处理器子系统：
    • Wi-Fi® 内核：
      • 802.11 a/b/g/n 2.4GHz 和 5GHz
      • 模式：
        • 接入点 (AP)
        • 基站 (STA)
        • Wi-Fi Direct®（仅在 2.4GHz 受支持）
      • 安全性：
        • WEP
        • WPA™/ WPA2™ PSK
        • WPA2 企业级
        • WPA3™ 个人版
        • WPA3™ 企业版
    • 互联网和应用协议：
      • HTTP 服务器、mDNS、DNS-SD 和 DHCP
      • IPv4 和 IPv6 TCP/IP 堆栈
      • 16 BSD 套接字（完全安全的 TLS v1.2 和 SSL 3.0）
    • 内置的电源管理子系统：
      • 可配置的低功耗配置文件（始终、间歇性、标签）
      • 高级低功耗模式
      • 集成式直流/直流稳压器
  • 多层安全特性：
    • 独立执行环境
    • 网络安全
    • 设备身份和密钥
    • 硬件加速器加密引擎（AES、DES、SHA/MD5 和 CRC）
    • 应用级安全（加密、身份验证、访问控制）
    • 初始安全编程
    • 软件篡改检测
    • 安全启动
    • 证书注册请求 (CSR)
    • 每个设备具有唯一密钥对
  • 应用吞吐量：
    • UDP：16Mbps，TCP：13Mbps
    • 峰值：72Mbps
  • 电源管理子系统：
    • 集成式直流/直流转换器支持宽电源电压范围：
      • VBAT 宽电压模式：2.1V 至 3.6V
      • VIO 始终与 VBAT 关联
    • 高级低功耗模式：
      • 关断：1µA，休眠：4.5µA
      • 低功耗深度睡眠 (LPDS)：120µA
      • 空闲连接（MCU 处于 LPDS 状态）：710µA
      • RX 流量（MCU 处于活动模式）：59mA
      • TX 流量（MCU 处于活动模式）：223mA
  • Wi-Fi TX 功率：
    • 2.4 GHz：1 DSSS 时为 18.0dBm
    • 5GHz：6 OFDM 时为 18.1dBm
  • Wi-Fi RX 灵敏度：
    • 2.4 GHz：1 DSSS 时为 -96dBm
    • 5GHz：6 OFDM 时为 -92dBm
  • 时钟源：
    • 具有内部振荡器的 40.0MHz 晶体
    • 32.768kHz 晶体或外部 RTC
  • RGK 封装
    • 64 引脚 9mm × 9mm Very Thin Quad Flat Nonleaded (VQFN) 封装，0.5mm 间距
  • 器件支持 SimpleLink™ MCU 平台开发人员生态系统

2 应用

  • 对于物联网应用，例如：
    • 楼宇和住宅自动化：
      • HVAC 系统和恒温器
      • 视频监控、可视门铃和低功耗摄像头
      • 楼宇安全系统和电子锁
    • 电器
    • 资产跟踪
    • 工厂自动化
    • 医疗和保健
    • 电网基础设施

3 说明

双频带无线 MCU CC3235x 器件有两种型号：CC3235S 和 C3235SF。

  • CC3235S 包括 256KB RAM、IoT 网络安全性、器件身份/密钥以及 MCU 级安全特性，例如文件系统加密、用户 IP（MCU 镜像）加密、安全启动和调试安全性。
  • CC3235SF 基于 CC3235S 而构建，除了 256KB RAM 以外，还集成了一个用户专用的 1MB 可执行闪存。

使用 Wi-Fi CERTIFIED™ 无线微控制器 (MCU) 简化您的 IoT 设计。SimpleLink™ Wi-Fi® CC3235x 器件系列是一种双频带片上系统 (SoC) 解决方案，将两个处理器集成在一个芯片上，包括：

  • 应用处理器：Arm® Cortex®-M4 MCU，具有用户专用的 256KB RAM 和可选的 1MB 可执行闪存
  • 用以运行所有 Wi-Fi 和互联网逻辑层的网络处理器此基于 ROM 的子系统完全减轻了主机 MCU 的负载，包括一个 802.11 a/b/g/n 双频带 2.4GHz 和 5GHz 无线电、基带和带有强大硬件加密引擎的 MAC

这些器件引入了可进一步简化物联网连接的新功能。主要新特性包括：

  • 802.11a (5GHz) 支持
  • 与 BLE/2.4GHz 无线电共存
  • 天线选择
  • 经过 FIPS 140-2 1 级认证和其他认证，安全性更强 (1)
  • 可同时打开多达 16 个安全套接字
  • 证书注册请求 (CSR)
  • 在线证书状态协议 (OCSP)
  • 经过 Wi-Fi® Alliance 认证的 IoT 省电特性（例如 DMS、代理 ARP 等）
  • 降低模板包传输负载的无主机模式
  • 改善了快速扫描特性

CC3235x 器件系列是 SimpleLink™ MCU 平台的一部分，该平台是一个常见、易用的开发环境，基于一个单核软件开发套件 (SDK)，具有丰富的工具集和参考设计。E2E™ 社区支持 Wi-Fi®、低功耗 Bluetooth®、Sub-1GHz 器件和主机 MCU。关于更多信息，请访问 www.ti.com.cn/simplelink 或 www.ti.com.cn/simplelinkwifi。

器件信息(1)
器件型号封装

封装

尺寸
CC3235SM2RGKRVQFN (64)9.00mm × 9.00mm
CC3235SF12RGKRVQFN (64)9.00mm × 9.00mm
(1) 有关更多信息，请参阅节 12。
1. 关于特定器件型号的具体 FIPS 认证状态，请参考 https://csrc.nist.gov/publications/fips。

4 功能方框图

图 4-1 展示了 CC3235x SimpleLink™ Wi-Fi® 解决方案的功能方框图。

CC3235S CC3235SF 功能方框图
注意：双工器用于信号天线解决方案。使用天线选择功能（双天线）时，需要在双工器后应用 1 个 SPDT 开关和 2 条 GPIO 线路。
图 4-1 功能方框图

图 4-2 为 CC3235x 器件的硬件概览。

CC3235S CC3235SF CC3235x 硬件概览图 4-2 CC3235x 硬件概览

图 4-3 为 CC3235x 器件中的嵌入式软件概览。

CC3235S CC3235SF CC3235x 嵌入式软件概览图 4-3 CC3235x 嵌入式软件概览

5 Device Comparison

Table 5-1 lists the features supported across different CC3x35 devices.

Table 5-1 Comparison of Device Features
FEATUREDEVICE
CC3135CC3235SCC3235SF
ClassificationNetwork processorWireless microcontrollerWireless microcontroller
Standard802.11a/b/g/n802.11a/b/g/n802.11a/b/g/n
TCP/IP stackIPv4, IPv6IPv4, IPv6IPv4, IPv6
Sockets161616
Package9mm × 9mm VQFN9mm × 9mm VQFN9mm × 9mm VQFN
ON-CHIP APPLICATION MEMORY
Flash——1MB
RAM—256KB256KB
RF FEATURES
Frequency2.4GHz, 5GHz2.4GHz, 5GHz2.4GHz, 5GHz
Coexistence with BLE RadioYesYesYes
SECURITY FEATURES
Additional networking securityUnique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol (OCSP)
Certificate signing request (CSR)
Unique per-device key pair		Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol (OCSP)
Certificate signing request (CSR)
Unique per-device key pair		Unique device identity
Trusted root-certificate catalog
TI Root-of-trust public key
Online certificate status protocol (OCSP)
Certificate signing request (CSR)
Unique per-device key pair
Hardware accelerationHardware crypto enginesHardware crypto enginesHardware crypto engines
Secure boot—YesYes
Enhanced application level security—File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming		File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
FIPS 140-2 Level 1 Certification(1)YesYesYes
(1) For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.

5.1 Related Products

For information about other devices in this family of products or related products, see the links that follow.

    The SimpleLink™ MCU PortfolioThis portfolio offers a single development environment that delivers flexible hardware, software, and tool options for customers developing wired and wireless applications. With 100 percent code reuse across host MCUs, Wi-Fi®, Bluetooth® low energy, Sub-1GHz devices and more, choose the MCU or connectivity standard that fits your design. A one-time investment with the SimpleLink™ software development kit (SDK) allows you to reuse often, opening the door to create unlimited applications.
    SimpleLink™ Wi-Fi® FamilyThis device platform offers several Internet-on-a chip™ solutions, which address the need of battery-operated, security-enabled products. Texas Instruments offers a single-chip wireless microcontroller and a wireless network processor that can be paired with any MCU, allowing developers to design new Wi-Fi® products or upgrade existing products with Wi-Fi® capabilities.
    BoosterPack™ Plug-in ModuleExtend the functionality of the TI LaunchPad™ Development Kit with the BoosterPack™ Plug-in Module. The application-specific BoosterPack Plug-in Module allows you to explore a broad range of applications, including capacitive touch, wireless sensing, LED Lighting control, and more. Stack multiple BoosterPack Plug-in Modules onto a single LaunchPad Development Kit to further enhance the functionality of your design.
    Reference Designs for CC3200, CC3220 and CC3235 DevicesThe TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market.
    The SimpleLink™ Wi-Fi® SDKThe SDK contains drivers for the CC3235 programmable MCU, sample applications, and documentation required to start development with CC3235x solutions.

6 Pin Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows pin assignments for the 64-pin VQFN package.

CC3235S CC3235SF Top View Pin Assignment for 64-Pin VQFN
NC = No internal connection
Figure 6-1 Top View Pin Assignment for 64-Pin VQFN

6.2 Pin Attributes

The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and register control.

Note:

TI highly recommends using the Pin Mux Tool to obtain the desired pinout. In addition, refer to the user guide within the SimpleLink™ CC32XX Software Development Kit (SDK)

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.

Table 6-1 and Table 6-2 list the pin descriptions and attributes. Table 6-3 lists the signal descriptions. Table 6-4 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers.

The following special considerations apply:

  • All I/Os support drive strengths of 2mA, 4mA, and 6mA. The drive strength is individually configurable for each pin.
  • All I/Os support 10µA pullup and pulldown resistors.
  • The VIO and VBAT supply must be tied together at all times.
  • By default, all I/Os float in the Hibernate state. However, the software can change the default state.
  • All digital I/Os are non-fail-safe.
Note:

If an external device drives a positive voltage to the signal pads and the CC3235x device is not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wake-up and boot of the CC3235x device can occur. To prevent current draw, TI recommends any one of the following conditions:

  • All devices interfaced to the CC3235x device must be powered from the same power rail as the chip.
  • Use level shifters between the device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3235x device must be held low until the VBAT supply to the device is driven and stable.
  • All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.

 

The ADC inputs are tolerant up to 1.8V (see Table 7-30 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For more information, see Section 6.5.

Table 6-1 Pin Descriptions
PINSTYPEDESCRIPTIONSELECT AS WAKEUP SOURCECONFIGURE ADDITIONAL ANALOG MUXMUXED WITH JTAG
NO.NAME
1GPIO10I/OGeneral-purpose input or outputNoNoNo
2GPIO11I/OGeneral-purpose input or outputYesNoNo
3GPIO12I/OGeneral-purpose input or outputNoNoNo
4GPIO13I/OGeneral-purpose input or outputYesNoNo
5GPIO14I/OGeneral-purpose input or outputNoNoNo
6GPIO15I/OGeneral-purpose input or outputNoNoNo
7GPIO16I/OGeneral-purpose input or outputNoNoNo
8GPIO17I/OGeneral-purpose input or outputYesNoNo
9VDD_DIG1PowerInternal digital core voltageN/AN/AN/A
10VIN_IO1PowerI/O power supply (same as battery voltage)N/AN/AN/A
11FLASH_SPI_CLKOSerial flash interface: SPI clockN/AN/AN/A
12FLASH_SPI_DOUTOSerial flash interface: SPI data outN/AN/AN/A
13FLASH_SPI_DINISerial flash interface: SPI data inN/AN/AN/A
14FLASH_SPI_CSOSerial flash interface: SPI chip selectN/AN/AN/A
15GPIO22I/OGeneral-purpose input or outputNoNoNo
16TDII/OJTAG interface: data inputNoNoMuxed with JTAG TDI
17TDOI/OJTAG interface: data outputYesNoMuxed with JTAG TDO
18GPIO28I/OGeneral-purpose input or outputNoNoNo
19TCKI/OJTAG / SWD interface: clockNoNoMuxed with JTAG/
SWD-TCK
20TMSI/OJTAG / SWD interface: mode select or SWDIONoNoMuxed with JTAG/
SWD-TMSC
21(1)SOP2OConfiguration sense-on-powerNoNoNo
22WLAN_XTAL_NAnalog40-MHz XTALN/AN/AN/A
23WLAN_XTAL_PAnalog40-MHz XTAL or TCXO clock inputN/AN/AN/A
24VDD_PLLPowerInternal analog voltageN/AN/AN/A
25LDO_IN2PowerAnalog RF supply from analog DCDC outputN/AN/AN/A
26NC—No ConnectN/AN/AN/A
27A_RXRFRF A band: 5 GHz A_RXN/AN/AN/A
28A_TXRFRF A band: 5 GHz A_TXN/AN/AN/A
29GNDGNDGroundN/AN/AN/A
30GNDGNDGroundN/AN/AN/A
31RF_BGRFRF BG band: 2.4 GHz TX, RXN/AN/AN/A
32nRESETIMaster chip reset input. Active low input.N/AN/AN/A
33VDD_PA_INPowerRF power amplifier (PA) input from PA DC-DC outputN/AN/AN/A
34SOP1OConfiguration sense-on-power and 5 GHz switch controlN/AN/AN/A
35SOP0OConfiguration sense-on-power and 5 GHz switch controlN/AN/AN/A
36LDO_IN1PowerAnalog RF supply from analog DCDC outputN/AN/AN/A
37VIN_DCDC_ANAPowerAnalog DC-DC supply input (same as battery voltage)N/AN/AN/A
38DCDC_ANA_SWPowerAnalog DC/DC converter switching nodeN/AN/AN/A
39VIN_DCDC_PAPowerPA DC/DC converter input supply (same as battery voltage)N/AN/AN/A
40DCDC_PA_SW_PPowerPA DC/DC converter +ve switching nodeN/AN/AN/A
41DCDC_PA_SW_NPowerPA DC/DC converter –ve switching nodeN/AN/AN/A
42DCDC_PA_OUTPowerPA DC/DC converter output.N/AN/AN/A
43DCDC_DIG_SWPowerDigital DC/DC converter switching nodeN/AN/AN/A
44VIN_DCDC_DIGPowerDigital DC/DC converter supply input (same as battery voltage)N/AN/AN/A
45DCDC_ANA2_SW_PI/OAnalog2 DCDC converter +ve switching nodeNoUser configuration not required (2)No
46DCDC_ANA2_SW_NPowerAnalog2 DC-DC converter -ve switching nodeN/AN/AN/A
47VDD_ANA2PowerAnalog2 DC-DC outputN/AN/AN/A
48VDD_ANA1PowerAnalog1 power supply fed by ANA2 DC-DC outputN/AN/AN/A
49VDD_RAMAnalogSRAM LDO outputN/AN/AN/A
50GPIO0I/OGeneral-purpose input or outputNoUser configuration not required (2)No
51RTC_XTAL_PAnalog32.768-kHz XTAL_P or external CMOS level clock inputN/AN/AN/A
52RTC_XTAL_NAnalog32.768-kHz XTAL_NN/AUser configuration not required (2)(3)No
53GPIO30I/OGeneral-purpose input or outputNoUser configuration not required (2)No
54VIN_IO2AnalogChip supply voltage (VBAT)N/AN/AN/A
55GPIO1I/OGeneral-purpose input or outputNoNoNo
56VDD_DIG2AnalogInternal digital core voltageN/AN/AN/A
57GPIO2I/OAnalog input (1.5V max) or general-purpose input or outputWake-up sourceSee (4)No
58GPIO3I/OAnalog input (1.5V max) or general-purpose input or outputNoSee (4)No
59GPIO4I/OAnalog input (1.5V max) or general-purpose input or outputWake-up sourceSee (4)No
60GPIO5I/OAnalog input (1.5V max) or general-purpose input or outputNoSee (4)No
61GPIO6I/OGeneral-purpose input or outputNoNoNo
62GPIO7I/OGeneral-purpose input or outputNoNoNo
63GPIO8I/OGeneral-purpose input or outputNoNoNo
64GPIO9I/OGeneral-purpose input or outputNoNoNo
GND_TAB—Thermal pad and electrical groundN/AN/AN/A
(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(2) Device firmware automatically enables the digital path during ROM boot.
(3) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100kΩ resistor.
(4) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.

 

Table 6-2 Pin Attributes
PIN NO.SIGNAL NAME(1)SIGNAL TYPE(2)PIN MUX ENCODINGSIGNAL DIRECTIONPAD STATES
LPDS(3)Hib(4)nRESET = 0
1GPIO10 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SCL1I/O (open drain)Hi-Z, Pull, Drive
GT_PWM063OHi-Z, Pull, Drive
UART1_TX7O1
SDCARD_CLK6O0
GT_CCP0112IHi-Z, Pull, Drive
2GPIO11 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA1I/O (open drain)Hi-Z, Pull, Drive
GT_PWM073OHi-Z, Pull, Drive
pXCLK(XVCLK)4O0
SDCARD_CMD6I/O (open drain)Hi-Z, Pull, Drive
UART1_RX7IHi-Z, Pull, Drive
GT_CCP0212IHi-Z, Pull, Drive
MCAFSX13OHi-Z, Pull, Drive
3GPIO12 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McACLK3OHi-Z, Pull, Drive
pVS(VSYNC)4IHi-Z, Pull, Drive
I2C_SCL5I/O (open drain)Hi-Z, Pull, Drive
UART0_TX7O1
GT_CCP0312IHi-Z, Pull, Drive
4GPIO13 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA5I/O (open drain)
pHS(HSYNC)4I
UART0_RX7I
GT_CCP0412I
5GPIO14 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SCL5I/O (open drain)
GSPI_CLK7I/O
pDATA8(CAM_D4)4I
GT_CCP0512I
6GPIO15 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
I2C_SDA5I/O (open drain)
GSPI_MISO7I/O
pDATA9(CAM_D5)4I
GT_CCP0613I
SDCARD_ DATA08I/O
7GPIO16 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GSPI_MOSI7I/OHi-Z, Pull, Drive
pDATA10(CAM_D6)4IHi-Z, Pull, Drive
UART1_TX5O1
GT_CCP0713IHi-Z, Pull, Drive
SDCARD_CLK8O0
8GPIO17 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART1_RX5I
GSPI_CS7I/O
pDATA11 (CAM_D7)4I
SDCARD_ CMD8I/O
9VDD_DIG1 (PN)—N/AN/AN/AN/AN/A
10VIN_IO1—N/AN/AN/AN/AN/A
11FLASH_SPI_CLKON/AOHi-Z, Pull, Drive(5)Hi-Z, Pull, DriveHi-Z
12FLASH_SPI_DOUTON/AOHi-Z, Pull, Drive(5)Hi-Z, Pull, DriveHi-Z
13FLASH_SPI_DININ/AIHi-Z, Pull, Drive(5)Hi-ZHi-Z
14FLASH_SPI_CSON/AO1Hi-Z, Pull, DriveHi-Z
15GPIO22 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McAFSX7O
GT_CCP045I
16TDI (PN)I/O1IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO230I/O
UART1_TX2O1
I2C_SCL9I/O (open drain)Hi-Z, Pull, Drive
17TDO (PN)I/O1OHi-Z, Pull, DriveDriven high in SWD; driven low in 4-wire JTAGHi-Z
GPIO240I/O
PWM05O
UART1_RX2I
I2C_SDA9I/O (open drain)
GT_CCP064I
McAFSX6O
18GPIO28 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
19TCK (PN)I/O1IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GT_PWM038O
20TMS (PN)I/O1I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO290I/O
21(6)GPIO25O0OHi-Z, Pull, DriveDriven lowHi-Z
GT_PWM029OHi-Z, Pull, Drive
McAFSX2OHi-Z, Pull, Drive
TCXO_ENN/AO0
SOP2 (PN)See (7)IHi-Z, Pull, Drive
22WLAN_XTAL_N—N/AN/AN/AN/AN/A
23WLAN_XTAL_P—N/AN/AN/AN/AN/A
24VDD_PLL—N/AN/AN/AN/AN/A
25LDO_IN2—N/AN/AN/AN/AN/A
26NC—N/AN/AN/AN/AN/A
27A_RX—N/AN/AN/AN/AN/A
28A_TX—N/AN/AN/AN/AN/A
29GND—N/AN/AN/AN/AN/A
30GND—N/AN/AN/AN/AN/A
31RF_BG—N/AN/AN/AN/AN/A
32nRESET—N/AN/AN/AN/AN/A
33VDD_PA_IN—N/AN/AN/AN/AN/A
34(8)SOP1 (PN)I/ON/AN/AN/AN/AN/A
A_SC1N/AN/AN/AN/AN/A
35(8)SOP0 (PN)I/ON/AN/AN/AN/AN/A
A_SC2N/AN/AN/AN/AN/A
36LDO_IN1—N/AN/AN/AN/AN/A
37VIN_DCDC_ANA—N/AN/AN/AN/AN/A
38DCDC_ANA_SW—N/AN/AN/AN/AN/A
39VIN_DCDC_PA—N/AN/AN/AN/AN/A
40DCDC_PA_SW_P—N/AN/AN/AN/AN/A
41DCDC_PA_SW_N—N/AN/AN/AN/AN/A
42DCDC_PA_OUT—N/AN/AN/AN/AN/A
43DCDC_DIG_SW—N/AN/AN/AN/AN/A
44VIN_DCDC_DIG—N/AN/AN/AN/AN/A
45(9)GPIO31I/O0I/OHi-ZHi-ZHi-Z
UART0_RX9I
McAFSX12O
UART1_RX2I
McAXR06I/O
GSPI_CLK7I/O
DCDC_ANA2_SW_P (PN)—See (10)N/AN/AN/AN/A
46DCDC_ANA2_SW_N—N/AN/AN/AN/AN/A
47VDD_ANA2—N/AN/AN/AN/AN/A
48VDD_ANA1—N/AN/AN/AN/AN/A
49VDD_RAM—N/AN/AN/AN/AN/A
50GPIO0 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_CTS12IHi-Z, Pull, Drive
McAXR16I/OHi-Z, Pull, Drive
GT_CCP007IHi-Z, Pull, Drive
GSPI_CS9I/OHi-Z, Pull, Drive
UART1_RTS10O1
UART0_RTS3O1
McAXR04I/OHi-Z, Pull, Drive
51RTC_XTAL_P—N/AN/AN/AN/AN/A
52(11)RTC_XTAL_N (PN)ON/AN/AN/AHi-Z, Pull, DriveHi-Z
GPIO320OHi-Z, Pull, Drive
McACLK2O
McAXR04O
UART0_RTS6O1
GSPI_MOSI8OHi-Z, Pull, Drive
53GPIO30 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_TX9O1
McACLK2OHi-Z, Pull, Drive
McAFSX3O
GT_CCP054I
GSPI_MISO7I/O
54VIN_IO2—N/AN/AN/AN/AN/A
55GPIO1 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_TX3O1
pCLK (PIXCLK)4IHi-Z, Pull, Drive
UART1_TX6O1
GT_CCP017IHi-Z, Pull, Drive
56VDD_DIG2—N/AN/AN/AN/AN/A
57(12)ADC_CH0Analog input (up to 1.5V) or digital I/OSee (10)IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO2 (PN)0I/O
UART0_RX3I
UART1_RX6I
GT_CCP027I
58(12)ADC_CH1Analog input (up to 1.5V) or digital I/OSee (10)IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO3 (PN)0I/O
UART1_TX6O1
pDATA7 (CAM_D3)4IHi-Z, Pull, Drive
59(12)ADC_CH2Analog input (up to 1.5V) or digital I/OSee (10)IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO4 (PN)0I/O
UART1_RX6I
pDATA6 (CAM_D2)4I
60(12)ADC_CH3Analog input (up to 1.5V) or digital I/OSee (10)IHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GPIO5 (PN)0I/O
pDATA5 (CAM_D1)4I
McAXR16I/O
GT_CCP057I
61GPIO6 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
UART0_RTS5O1
pDATA4 (CAM_D0)4IHi-Z, Pull, Drive
UART1_CTS3I
UART0_CTS6I
GT_CCP067I
62GPIO7 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
McACLKX13O
UART1_RTS3O1
UART0_RTS10O
UART0_TX11O
63GPIO8 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
SDCARD_IRQ6I
McAFSX7O
GT_CCP0612I
64GPIO9 (PN)I/O0I/OHi-Z, Pull, DriveHi-Z, Pull, DriveHi-Z
GT_PWM053O
SDCARD_DATA06I/O
McAXR07I/O
GT_CCP0012I
GND_TAB—N/AN/AN/AN/AN/A
(1) Signals names with (PN) denote the default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(8) This pin has dual functions: as a SOP (device operation mode) input pin during boot up, and as the 5GHz switch control (output) pin on power up
(9) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(10) For details on proper use, see Section 6.5.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications, a 32.768kHz square-wave clock might always be available onboard. When a 32.768kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.
(12) This pin is shared by the ADC inputs and digital I/O pad cells.

6.3 Signal Descriptions

Table 6-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN
NO.		 PIN
TYPE		 SIGNAL DIRECTION DESCRIPTION
ADC ADC_CH0 57 I/O I ADC channel 0 input (maximum of 1.5 V)
ADC_CH1 58 I/O I ADC channel 1 input (maximum of 1.5 V)
ADC_CH2 59 I/O I ADC channel 2 input (maximum of 1.5 V)
ADC_CH3 60 I I ADC channel 3 input (maximum of 1.5 V)
Antenna selection GPIO10 1 I/O O Antenna selection control
GPIO11 2 I/O O
GPIO12 3 I/O O
GPIO13 4 I/O O
GPIO14 5 I/O O
GPIO15 6 I/O O
GPIO16 7 I/O O
GPIO17 8 I/O O
GPIO22 15 I/O O
GPIO28 18(1) I/O O
GPIO25 21 O O
GPIO31 45(1)(2) I/O O
GPIO0 50 I/O O
GPIO32 52(1) I/O O
GPIO30 53(1) I/O O
GPIO3 58 I/O O
GPIO4 59 I/O O
GPIO5 60 I/O O
GPIO6 61 I/O O
GPIO8 63 I/O O
GPIO9 64 I/O O
BLE/2.4 GHz radio coexistence GPIO10 1 I/O I/O Coexistence inputs and outputs
GPIO11 2 I/O O
GPIO12 3 I/O I/O
GPIO13 4 I/O I/O
GPIO14 5 I/O I/O
GPIO15 6 I/O I/O
GPIO16 7 I/O I/O
GPIO17 8 I/O O
GPIO22 15 I/O I/O
GPIO28 18(1) I/O I/O
GPIO25 21 O O
GPIO31 45(1)(2) I/O I/O
GPIO0 50 I/O I/O
GPIO32 52(1) I/O I/O
GPIO30 53(1) I/O I/O
GPIO3 58 I/O O
GPIO4 59 I/O O
GPIO5 60 I/O I/O
GPIO6 61 I/O I/O
GPIO8 63 I/O I/O
GPIO9 64 I/O I/O
Clock WLAN_XTAL_N 22 — — 40-MHz crystal; pull down if external TCXO is used
WLAN_XTAL_P 23 — — 40-MHz crystal or TCXO clock input
RTC_XTAL_P 51 — — Connect 32.768-kHz crystal or force external CMOS level clock
RTC_XTAL_N 52 — — Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage
Hostless mode HM_IO 1 I/O I/O Hostless mode inputs and outputs
2 I/O O
3 I/O I/O
4 I/O I/O
5 I/O I/O
6 I/O I/O
7 I/O I/O
8 I/O O
15 I/O I/O
18(1) I/O I/O
21 O O
45(1)(2) I/O I/O
50 I/O I/O
52(1) I/O I/O
53(1) I/O I/O
58 O O
59 O O
60 I/O I/O
61 I/O I/O
63 I/O I/O
64 I/O I/O
JTAG / SWD TDI 16 I/O I JTAG TDI. Reset default pinout.
TDO 17 I/O O JTAG TDO. Reset default pinout.
TCK 19 I/O I JTAG/SWD TCK. Reset default pinout.
TMS 20 I/O I/O JTAG/SWD TMS. Reset default pinout.
I2C I2C_SCL 1 I/O I/O (open drain) I2C clock data
3
5
16
I2C_SDA 2 I/O I/O (open drain) I2C data
4
6
17
Timers GT_PWM06 1 I/O O Pulse-width modulated O/P
GT_CCP01 1 I/O I Timer capture port
GT_PWM07 2 I/O O Pulse-width modulated O/P
GT_CCP02 2 I/O I Timer capture ports
GT_CCP03 3 I/O I
GT_CCP04 4 I/O I
15 I/O I
GT_CCP05 5 I/O I
GT_CCP06 6 I/O I
17 I/O I
61 I/O I
63 I/O I
GT_CCP07 7 I/O I
PWM0 17 I/O O Pulse-width modulated outputs
GT_PWM03 19 I/O O
GT_PWM02 21 O O
GT_CCP00 50 I/O I Timer capture ports
64 I/O I
GT_CCP05 53 I/O I
GT_CCP01 55 I/O I
GT_CCP02 57 I/O I
GT_CCP05 60 I I Timer capture port Input
GT_PWM05 64 I/O O Pulse-width modulated output
GPIO GPIO10 1 I/O I/O General-purpose inputs or outputs
GPIO11 2 I/O I/O
GPIO12 3 I/O I/O
GPIO13 4 I/O I/O
GPIO14 5 I/O I/O
GPIO15 6 I/O I/O
GPIO16 7 I/O I/O
GPIO17 8 I/O I/O
GPIO22 15 I/O I/O
GPIO23 16 I/O I/O
GPIO24 17 I/O I/O
GPIO28 18 I/O I/O
GPIO29 20 I/O I/O
GPIO25 21 O O
GPIO31 45(2) I/O I/O
GPIO0 50 I/O I/O
GPIO32 52 I/O O
GPIO30 53 I/O I/O
GPIO1 55 I/O I/O
GPIO2 57 I/O I/O
GPIO3 58 I/O I/O
GPIO4 59 I/O I/O
GPIO5 60 I/O I/O
GPIO6 61 I/O I/O
GPIO7 62 I/O I/O
GPIO8 63 I/O I/O
GPIO9 64 I/O I/O
McASP
I2S or PCM		 MCAFSX 2 I/O O I2S audio port frame sync
15
17
21
45(2)
53
63
McACLK 3 I/O O I2S audio port clock outputs
52 O O
53 I/O O
McAXR1 50 I/O I/O I2S audio port data 1 (RX/TX)
60 I I/O I2S audio port data 1 (RX and TX)
McAXR0 45(2) I/O I/O I2S audio port data 0 (RX and TX)
50 I/O I/O
52 O O I2S audio port data (only output mode is supported on pin 52)
64 I/O I/O I2S audio port data (RX and TX)
McACLKX 62 I/O O I2S audio port clock
Multimedia card
(MMC or SD)		 SDCARD_CLK 1 I/O O SD card clock data
7
SDCARD_CMD 2 I/O I/O (open drain) SD card command line
8 I/O I/O
SDCARD_DATA0 6 I/O I/O SD card data
64
SDCARD_IRQ 63 I/O I Interrupt from SD card(3)
Parallel interface
(8-bit π)		 pXCLK (XVCLK) 2 I/O O Free clock to parallel camera
pVS (VSYNC) 3 I/O I Parallel camera vertical sync
pHS (HSYNC) 4 I/O I Parallel camera horizontal sync
pDATA8 (CAM_D4) 5 I/O I Parallel camera data bit 4
pDATA9 (CAM_D5) 6 I/O I Parallel camera data bit 5
pDATA10 (CAM_D6) 7 I/O I Parallel camera data bit 6
pDATA11 (CAM_D7) 8 I/O I Parallel camera data bit 7
pCLK (PIXCLK) 55 I/O I Pixel clock from parallel camera sensor
pDATA7 (CAM_D3) 58 I/O I Parallel camera data bit 3
pDATA6 (CAM_D2) 59 I/O I Parallel camera data bit 2
pDATA5 (CAM_D1) 60 I I Parallel camera data bit 1
pDATA4 (CAM_D0) 61 I/O I Parallel camera data bit 0
Power VDD_DIG1 9 — — Internal digital core voltage
VIN_IO1 10 — — Device supply voltage (VBAT)
VDD_PLL 24 — — Internal analog voltage
LDO_IN2 25 — — Internal analog RF supply from analog DC/DC output
VDD_PA_IN 33 — — Internal PA supply voltage from PA DC/DC output
LDO_IN1 36 — — Internal analog RF supply from analog DC/DC output
VIN_DCDC_ANA 37 — — Analog DC/DC input (connected to device input supply [VBAT])
DCDC_ANA_SW 38 — — Internal analog DC/DC switching node
VIN_DCDC_PA 39 — — PA DC/DC input (connected to device input supply [VBAT])
DCDC_PA_SW_P 40 — — Internal PA DC/DC switching node
DCDC_PA_SW_N 41 — — Internal PA DC/DC switching node
DCDC_PA_OUT 42 — — Internal PA buck converter output
DCDC_DIG_SW 43 — — Internal digital DC/DC switching node
VIN_DCDC_DIG 44 — — Digital DC/DC input (connected to device input supply [VBAT])
DCDC_ANA2_SW_P 45(2) — — Analog to DC/DC converter +ve switching node
DCDC_ANA2_SW_N 46 — — Internal analog to DC/DC converter –ve switching node
VDD_ANA2 47 — — Internal analog to DC/DC output
VDD_ANA1 48 — — Internal analog supply fed by ANA2 DC/DC output
VDD_RAM 49 — — Internal SRAM LDO output
VIN_IO2 54 — — Device supply voltage (VBAT)
VDD_DIG2 56 — — Internal digital core voltage
Reset nRESET 32 I I Global master device reset (active low)
RF A_RX 27 I I WLAN analog A-band receive
A_TX 28 O O WLAN analog A-band transmit
RF_BG 31 I/O I/O WLAN analog RF 802.11 b/g bands
SPI GSPI_CLK 5 I/O I/O General SPI clock
45(2) I/O I/O
GSPI_MISO 6 I/O I/O General SPI MISO
53 I/O I/O
GSPI_CS 8 I/O I/O General SPI device select
50 I/O I/O
GSPI_MOSI 7 I/O I/O General SPI MOSI
52 O O
FLASH SPI FLASH_SPI_CLK 11 O O Clock to SPI serial flash (fixed default)
FLASH_SPI_DOUT 12 O O Data to SPI serial flash (fixed default)
FLASH_SPI_DIN 13 I I Data from SPI serial flash (fixed default)
FLASH_SPI_CS 14 O O Device select to SPI serial flash (fixed default)
UART UART1_TX 1 I/O O UART TX data
7 I/O O
16 I/O O
55 I/O O
58 I/O O UART1 TX data
UART1_RX 2 I/O I UART RX data
8 I/O I
17 I/O I
45(2) I/O I
57 I/O I UART1 RX data
59 I/O I
UART1_RTS 50 I/O O UART1 request-to-send (active low)
62 I/O O
UART1_CTS 61 I/O I UART1 clear-to-send (active low)
UART0_TX 3 I/O O UART0 TX data
53 I/O O
55 I/O O
62 I/O O
UART0_RX 4 I/O I UART0 RX data
45(2) I/O I
57 I/O I UART0 RX data
UART0_CTS 50 I/O I UART0 clear-to-send input (active low)
61
UART0_RTS 50 I/O O UART0 request-to-send (active low)
52 O O
61 I/O O
62 I/O O
Sense-On-Power SOP2 21(4) O I Sense-on-power 2
SOP1 34 I I Configuration sense-on-power 1
SOP0 35 I I Configuration sense-on-power 0
(1) LPDS retention unavailable.
(2) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(3) Future support.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

6.4 Pin Multiplexing

Table 6-4 Pin Multiplexing
Register AddressRegister NamePinANALOG OR SPECIAL FUNCTIONDigital Function (XXX Field Encoding)(1)
JTAGHostless ModeBLE COEX012345678910111213
CC_COEX_SW_OUTCC_COEX_BLE_IN
0x4402 E0C8GPIO_PAD_
CONFIG_10		1—YYYGPIO10I2C_
SCL		—GT_
PWM06		——SDCARD_
CLK		UART1_
TX		————GT_
CCP01		—
0x4402 E0CCGPIO_PAD_
CONFIG_11		2—Y(2)Y—GPIO11I2C_
SDA		—GT_
PWM07		pXCLK (XVCLK)—SDCARD_
CMD		UART1_
RX		————GT_
CCP02		MCAFSX
0x4402 E0D0GPIO_PAD_
CONFIG_12		3—YYYGPIO12——McACLKpVS (VSYNC)I2C_
SCL		—UART0_
TX		————GT_
CCP03		—
0x4402 E0D4GPIO_PAD_
CONFIG_13		4—YYYGPIO13———pHS (HSYNC)I2C_
SDA		—UART0_
RX		————GT_
CCP04		—
0x4402 E0D8GPIO_PAD_
CONFIG_14		5—YYYGPIO14———pDATA8 (CAM_D4)I2C_
SCL		—GSPI_
CLK		————GT_
CCP05		—
0x4402 E0DCGPIO_PAD_
CONFIG_15		6—YYYGPIO15———pDATA9 (CAM_D5)I2C_
SDA		—GSPI_
MISO		SDCARD_
DATA0		————GT_
CCP06
0x4402 E0E0GPIO_PAD_
CONFIG_16		7—YYYGPIO16———pDATA10 (CAM_D6)UART1_
TX		—GSPI_
MOSI		SDCARD_
CLK		————GT_
CCP07
0x4402 E0E4GPIO_PAD_
CONFIG_17		8—Y(2)Y—GPIO17———pDATA11 (CAM_D7)UART1_
RX		—GSPI_
CS		SDCARD_
CMD		—————
0x4402 E0F8GPIO_PAD_
CONFIG_22		15—YYYGPIO22————GT_
CCP04		—McAFSX——————
0x4402 E0FCGPIO_PAD_
CONFIG_23		16Muxed with JTAG———GPIO23TDIUART1_
TX		——————I2C_
SCL		————
0x4402 E100GPIO_PAD_
CONFIG_24		17Muxed with JTAG TDO———GPIO24TDOUART1_
RX		—GT_
CCP06		PWM0McAFSX——I2C_
SDA		————
0x4402 E140GPIO_PAD_
CONFIG_40		18—Y(3)Y(3)Y(3)GPIO28—————————————
0x4402 E110GPIO_PAD_
CONFIG_28		19Muxed with JTAG or SWD and TCK————TCK——————GT_
PWM03		—————
0x4402 E114GPIO_PAD_
CONFIG_29		20Muxed with JTAG or SWD and TMSC———GPIO29TMS————————————
0x4402 E104GPIO_PAD_
CONFIG_25		21(4)—Y(2)Y—GPIO25—McAFSX——————GT_
PWM02		————
0x4402 E11CGPIO_PAD_
CONFIG_31		45(3)(5)—YYYGPIO31—UART1_
RX		———McAXR0GSPI_
CLK		—UART0_
RX		——McAFSX—
0x4402 E0A0GPIO_PAD_
CONFIG_0		50—YYYGPIO0——UART0_
RTS		McAXR0—McAXR1GT_
CCP00		—GSPI_
CS		UART1_
RTS		—UART0_
CTS		—
0x4402 E120GPIO_PAD_
CONFIG_32		52—Y(3)Y(3)Y(3)GPIO32—McACLK—McAXR0—UART0_
RTS		—GSPI_
MOSI		—————
0x4402 E118GPIO_PAD_
CONFIG_30		53-—Y(3)Y(3)Y(3)GPIO30—McACLKMcAFSXGT_
CCP05		——GSPI_
MISO		—UART0_
TX		————
0x4402 E0A4GPIO_PAD_
CONFIG_1		55————GPIO1——UART0_
TX		pCLK (PIXCLK)—UART1_
TX		GT_
CCP01		——————
0x4402 E0A8GPIO_PAD_
CONFIG_2		57————GPIO2——UART0_
RX		——UART1_
RX		GT_
CCP02		——————
0x4402 E0ACGPIO_PAD_
CONFIG_3		58—Y(2)Y—GPIO3———pDATA7 (CAM_D3)—UART1_
TX		———————
0x4402 E0B0GPIO_PAD_
CONFIG_4		59—Y(2)Y—GPIO4———pDATA6 (CAM_D2)—UART1_
RX		———————
0x4402 E0B4GPIO_PAD_
CONFIG_5		60—YYYGPIO5———pDATA5 (CAM_D1)—McAXR1GT_
CCP05		——————
0x4402 E0B8GPIO_PAD_
CONFIG_6		61—YYYGPIO6——UART1_
CTS		pDATA4 (CAM_D0)UART0_
RTS		UART0_
CTS		GT_
CCP06		——————
0x4402 E0BCGPIO_PAD_
CONFIG_7		62————GPIO7——UART1_
RTS		——————UART0_
RTS		UART0_
TX		—McACLKX
0x4402 E0C0GPIO_PAD_
CONFIG_8		63—YYYGPIO8—————SDCARD_
IRQ		McAFSX————GT_
CCP06		—
0x4402 E0C4GPIO_PAD_
CONFIG_9		64-—YYYGPIO9——GT_
PWM05		——SDCARD_
DATA0		McAXR0————GT_
CCP00		—
(1) Pin mux encodings with (RD) denote the default encoding after reset release.
(2) Output Only
(3) LPDS retention unavailable.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(5) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

6.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins

Table 6-5 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time power up and reset (nRESET pulled low).

Table 6-5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
PinBoard-Level Configuration and UseDefault State at First Power Up
or Forced Reset		State After Configuration of Analog Switches (ACTIVE, LPDS, and HIB Power Modes)Maximum Effective Drive Strength (mA)
45VDD_ANA2 (pin 47) must be shorted to the input supply rail. Otherwise, the pin is driven by the ANA2 DC/DC.Analog is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
50Generic I/OAnalog is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
52The pin must have an external pullup of 100 kΩ to the supply rail and must be used in output signals only.Analog is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
53Generic I/OAnalog is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
57Analog signal (1.8-V absolute, 1.46-V full scale)ADC is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
58Analog signal (1.8-V absolute, 1.46-V full scale)ADC is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
59Analog signal (1.8-V absolute, 1.46-V full scale)ADC is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4
60Analog signal (1.8-V absolute, 1.46-V full scale)ADC is isolated. The digital I/O cell is also isolated.Determined by the I/O state, as are other digital I/Os.4

 

6.6 Pad State After Application of Power to Device, Before Reset Release

When a stable power is applied to the CC3235x device for the first time or when supply voltage is restored to the proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set of pins is required to have a definite value during this pre-reset period, an appropriate pullup or pulldown resistor must be used at the board level. The recommended value of this external pull is 2.7 kΩ.

 
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