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PVDD:VBAT 至 15V(QFN,VBAT < 3.5V)
TAS2563 是一款经过优化、可将高峰值功率高效地驱动到小型扬声器的数字输入 D 级音频放大器。该 D 类放大器能够在 3.6V 的电池电压下使用集成式 11.5V H 类升压功能将 6.1W 峰值功率提供给 4Ω 负载,或在升压旁路模式下使用外部 12V 电源将 10W 峰值功率提供给 4Ω 负载。
片上低延迟 DSP 支持德州仪器 (TI) 的 SmartAmp 扬声器保护算法。集成的电流和电压检测功能可对扬声器进行实时监测,从而在改变峰值声压级 (SPL) 的同时保持扬声器不受损坏。
集成的超前 H 级升压功能可在播放期间动态调整升压电压,从而提高电池供电型系统的效率并延长电池寿命。对于稳压壁式供电型系统,TAS2563 还具有升压旁路模式,支持高达 16V 的电源电压以实现更高的输出功率。
两个 PDM 麦克风输入简化了双向音频系统的音频信号链,能够将数字麦克风与主机处理器连接起来。电池跟踪峰值电压限制器具有欠压保护功能,可以优化放大器在整个充电周期中的余量,从而防止系统关断。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TAS2563 | DSBGA | 2.5mm × 3mm |
TAS2563 | QFN | 4.5mm x 4mm |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | DSBGA NO. | QFN NO. | ||
ADDR_SPICLK | C4 | 19 | I | I2C Mode - Address selection pin See General I2C operation. SPI Mode - SPI clock |
DREG | B6 | 2 | P | Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load. |
FSYNC | B3 | 5 | I | I2S word clock or TDM frame sync for ASI1 and ASI2 channels. |
GNDB | E1, E2, E3 | 14 | P | Boost ground. Connect to PCB GND plane. |
GNDD | F4 | 28 | P | Digital ground. Connect to PCB GND plane. |
GND | E4 | N/A | P | Analog ground. Connect to PCB GND plane. |
GNDP | E5,E6 | 27 | P | Power stage ground. Connect to PCB GND plane. |
GPIO | D6 | 22 | IO | General purpose input-ouput or MCLK base on register configuration. |
GREG | D4 | 13 | P | High-side gate CP regulator output. Do not connect to external load. |
IOVDD | A6 | 32 | P | 3.3-V/1.8-V IOVDD Supply |
IRQZ | C5 | 18 | O | Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up is not used. |
OUT_N | F6 | 26 | O | Class-D negative output for receiver channel. |
OUT_P | F5 | 21 | O | Class-D positive output for receiver channel. |
PDMCLK | A1 | 9 | IO | PDM clock. |
PDMD | A2 | 24 | IO | PDM data. |
PVDD | G4, G5, G6 | 25 | P | Power stage supply. |
SBCLK1 | B2 | 6 | I | ASI1 channel I2S/TDM serial bit clock. |
SBCLK2 | A5 | I | ASI2 channel I2S/TDM serial bit clock. | |
SDA_MOSI | B5 | 3 | IO | I2C Mode: I2C Data Pin. Pull up to IOVDD with a resistor. SPI Mode: Serial data input pin. |
SDIN1 | C2 | 11 | I | ASI1 channel I2S/TDM serial data input. |
SDIN2 | A4 | I | ASI2 channel I2S/TDM serial data input. | |
SDOUT1 | C1 | 10 | IO | ASI1 channel I2S/TDM serial data output. |
SDOUT2 | A3 | IO | ASI2 channel I2S/TDM serial data output. | |
SDZ | B1 | 7 | I | Active low hardware shutdown. |
SCL_SELZ | B4 | 4 | IO | I2C Mode: I2C clock pin. Pull up to IOVDD with a resistor. SPI Mode: active low chip select. |
SPII2CZ_MISO | C3 | 12 | IO | Pin is queried on power-up. Short to GND for I2C Mode. Pull to IOVDD with resistor for SPI mode. SPI serial data output pin. |
SW | F1, F2, F3 | 15 | P | Boost converter switch input. |
VBAT | D1, D2 | 30 | P | Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with a cap. |
VBST | G1, G2, G3 | 16 | P | Boost converter output. Do not connect to external load. |
VDD | C6 | 31 | P | Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to GND with cap. |
VSNS_N | D3 | 29 | I | Voltage sense negative input. Connect to Class-D OUT_N output after Ferrite bead filter. |
VSNS_P | D5 | 20 | I | Voltage sense positive input. Connect to Class-D OUT_P output after Ferrite bead filter. |
NC | 1, 8, 17 | No Connect. |