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PVDD:VBAT 至 15V(QFN,VBAT < 3.5V)
TAS2563 是一款经过优化、可将高峰值功率高效地驱动到小型扬声器的数字输入 D 级音频放大器。该 D 类放大器能够在 3.6V 的电池电压下使用集成式 11.5V H 类升压功能将 6.1W 峰值功率提供给 4Ω 负载,或在升压旁路模式下使用外部 12V 电源将 10W 峰值功率提供给 4Ω 负载。
片上低延迟 DSP 支持德州仪器 (TI) 的 SmartAmp 扬声器保护算法。集成的电流和电压检测功能可对扬声器进行实时监测,从而在改变峰值声压级 (SPL) 的同时保持扬声器不受损坏。
集成的超前 H 级升压功能可在播放期间动态调整升压电压,从而提高电池供电型系统的效率并延长电池寿命。对于稳压壁式供电型系统,TAS2563 还具有升压旁路模式,支持高达 16V 的电源电压以实现更高的输出功率。
两个 PDM 麦克风输入简化了双向音频系统的音频信号链,能够将数字麦克风与主机处理器连接起来。电池跟踪峰值电压限制器具有欠压保护功能,可以优化放大器在整个充电周期中的余量,从而防止系统关断。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TAS2563 | DSBGA | 2.5mm × 3mm |
TAS2563 | QFN | 4.5mm x 4mm |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | DSBGA NO. | QFN NO. | ||
ADDR_SPICLK | C4 | 19 | I | I2C Mode - Address selection pin See General I2C operation. SPI Mode - SPI clock |
DREG | B6 | 2 | P | Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load. |
FSYNC | B3 | 5 | I | I2S word clock or TDM frame sync for ASI1 and ASI2 channels. |
GNDB | E1, E2, E3 | 14 | P | Boost ground. Connect to PCB GND plane. |
GNDD | F4 | 28 | P | Digital ground. Connect to PCB GND plane. |
GND | E4 | N/A | P | Analog ground. Connect to PCB GND plane. |
GNDP | E5,E6 | 27 | P | Power stage ground. Connect to PCB GND plane. |
GPIO | D6 | 22 | IO | General purpose input-ouput or MCLK base on register configuration. |
GREG | D4 | 13 | P | High-side gate CP regulator output. Do not connect to external load. |
IOVDD | A6 | 32 | P | 3.3-V/1.8-V IOVDD Supply |
IRQZ | C5 | 18 | O | Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up is not used. |
OUT_N | F6 | 26 | O | Class-D negative output for receiver channel. |
OUT_P | F5 | 21 | O | Class-D positive output for receiver channel. |
PDMCLK | A1 | 9 | IO | PDM clock. |
PDMD | A2 | 24 | IO | PDM data. |
PVDD | G4, G5, G6 | 25 | P | Power stage supply. |
SBCLK1 | B2 | 6 | I | ASI1 channel I2S/TDM serial bit clock. |
SBCLK2 | A5 | I | ASI2 channel I2S/TDM serial bit clock. | |
SDA_MOSI | B5 | 3 | IO | I2C Mode: I2C Data Pin. Pull up to IOVDD with a resistor. SPI Mode: Serial data input pin. |
SDIN1 | C2 | 11 | I | ASI1 channel I2S/TDM serial data input. |
SDIN2 | A4 | I | ASI2 channel I2S/TDM serial data input. | |
SDOUT1 | C1 | 10 | IO | ASI1 channel I2S/TDM serial data output. |
SDOUT2 | A3 | IO | ASI2 channel I2S/TDM serial data output. | |
SDZ | B1 | 7 | I | Active low hardware shutdown. |
SCL_SELZ | B4 | 4 | IO | I2C Mode: I2C clock pin. Pull up to IOVDD with a resistor. SPI Mode: active low chip select. |
SPII2CZ_MISO | C3 | 12 | IO | Pin is queried on power-up. Short to GND for I2C Mode. Pull to IOVDD with resistor for SPI mode. SPI serial data output pin. |
SW | F1, F2, F3 | 15 | P | Boost converter switch input. |
VBAT | D1, D2 | 30 | P | Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with a cap. |
VBST | G1, G2, G3 | 16 | P | Boost converter output. Do not connect to external load. |
VDD | C6 | 31 | P | Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to GND with cap. |
VSNS_N | D3 | 29 | I | Voltage sense negative input. Connect to Class-D OUT_N output after Ferrite bead filter. |
VSNS_P | D5 | 20 | I | Voltage sense positive input. Connect to Class-D OUT_P output after Ferrite bead filter. |
NC | 1, 8, 17 | No Connect. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
IO Supply IOVDD | IOVDD | -0.3 | 3.9 | V |
Analog Voltage | VDD | –0.3 | 2 | V |
Battery Supply Voltage | VBAT | –0.3 | 6 | V |
Boost Pin | VBST | -0.3 | 18.5 | V |
Power Supply Voltage | PVDD(3) | -0.3 | 18.5 | V |
Switching Pin | SW | -0.7 | 16 | V |
High Side Regulator Pin | GREG | -0.3 | PVDD+6 | V |
Digital Regular Pin | DREG | -0.3 | 1.65 | V |
Input voltage(2) | Digital IOs referenced to VDD supply | –0.3 | VDD+0.3 | V |
Operating free-air temperature, TA | –40 | 85 | °C | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 OUT_N / OUT_P / VSNS_N / VSNS_P Pins(1) | ±3000 | V |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | ||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
IOVDD | IO Supplly Voltage 1.8V | 1.62 | 1.8 | 1.98 | V |
IOVDD | IO Supply Voltage 3.3V | 3 | 3.3 | 3.6 | V |
VBAT | Supply voltage | 2.5 | 3.6 | 5.5 | V |
VDD | Supply voltage | 1.62 | 1.8 | 1.95 | V |
PVDDDSBGA (VBST) | Supply voltage - external boost mode (DSBGA package) | VBAT | 16 | V | |
PVDDQFN (VBST) | Supply voltage - external boost mode (QFN package) | VBAT | 13 | V | |
PVDDQFN (VBST) | Supply voltage - external boost mode (QFN package), VBAT < 3.5V | VBAT | 15 | V | |
VIH | High-level digital input voltage | 0.7 x IOVDD | V | ||
VIL | Low-level digital input voltage | 0 | V | ||
RSPK | Minimum speaker impedance | 3.2 | Ω | ||
LSPK | Minimum speaker inductance | 10 | µH |
THERMAL METRIC(1) | TAS2563 | UNIT | ||
---|---|---|---|---|
RPP (QFN) | YBG (WCSP) | |||
32 PINS | 42 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 43.7 | 55.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 20.3 | 0.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 10.5 | 11.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 10.5 | 11.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUT and OUTPUT |
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VIH | High-level digital input logic voltage threshold (max current limit = 30 mA) | All digital pins except SDA_MOSI and SCL_SELZ | 0.65 × IOVDD | V | ||
VIL | Low-level digital input logic voltage threshold (max current limit = 30 mA) | All digital pins except SDA_MOSI and SCL_SELZ | 0.35 × IOVDD | V | ||
VIH(I2C) | High-level digital input logic voltage threshold (max current limit = 30 mA) | SDA_MOSI and SCL_SELZ | 0.7 × IOVDD | V | ||
VIL(I2C) | Low-level digital input logic voltage threshold (max current limit = 30 mA) | SDA_MOSI and SCL_SELZ | 0.3 × IOVDD | V | ||
VOH | High-level digital output voltage (max current limit = 30 mA) | All digital pins except SDA_MOSI ,SCL_SELZ and IRQZ; IOH = 2 mA. | IOVDD – 0.45 V | V | ||
VOL | Low-level digital output voltage (max current limit = 30 mA) | All digital pins except SDA_MOSI ,SCL_SELZ and IRQZ; IOL = –2 mA. | 0.45 | V | ||
VOL(I2C) | Low-level digital output voltage (max current limit = 30 mA) | SDA and SCL; IOL(I2C) = –2 mA. | 0.2 × IOVDD | V | ||
VOL(IRQZ) | Low-level digital output voltage for IRQZ open drain Output (max current limit = 30 mA) | IRQZ; IOL(IRQZ) = –2 mA. | 0.45 | V | ||
IIH | Input logic-high leakage for digital inputs | All digital pins; Input = VDD. | –5 | 0.1 | 5 | µA |
IIL | Input logic-low leakage for digital inputs | All digital pins; Input = GND. | –5 | 0.1 | 5 | µA |
CIN | Input capacitance for digital inputs | All digital pins | 8 | pF | ||
RPD | Pull down resistance for digital input/IO pins when asserted on | SDOUT, SDIN, FSYNC, SBCLK | 50 | kΩ | ||
AMPLIFIER PERFORMANCE - Internal Boost | ||||||
Output Voltage for Full-scale digital Input | Measured at -6 dB FS input | 6.32 | Vrms | |||
POUT | Maximum Continuous Output Power | RL = 32Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz | 1.25 | W | ||
RL = 8 Ω + 33 µH, THD+N = 0.03 %, fin = 1 kHz | 5 | W | ||||
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz | 6.1 | W | ||||
System efficiency at POUT = 1 W | RL = 8 Ω + 33 µH, fin = 1 kHz | 82 | % | |||
RL = 4 Ω + 33 µH, fin = 1 kHz | 78.5 | % | ||||
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V | 82.5 | % | ||||
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V | 84.2 | % | ||||
System efficiency at POUT =0.5 W | RL = 8 Ω + 33 µH, fin = 1 kHz | 76.6 | % | |||
RL = 4 Ω + 33 µH, fin = 1 kHz | 81.1 | % | ||||
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V | 84.2 | % | ||||
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 4.2 V | 81.6 | % | ||||
System efficiency at 0.1% THD+N power level | RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, | 78.8 | % | |||
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, | 80 | % | ||||
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz | 76.2 | % | ||||
THD+N | Total harmonic distortion + noise | POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz | 0.01 | % | ||
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz | 0.01 | % | ||||
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz | 0.01 | % | ||||
VN | Idle channel noise | A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running | 14.8 | µV | ||
FPWM | Class-D PWM switching frequency | Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 | 384 | kHz | ||
Fixed Frequency Mode, CLASSD_SYNC=0 | 384 | kHz | ||||
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz | 352.8 | kHz | ||||
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz | 384 | kHz | ||||
VOS | Output offset voltage | -1 | 1 | mV | ||
DNR | Dynamic range | A-Weighted, -60 dBFS Method | 105 | dB | ||
SNR | Signal to noise ratio | A-Weighted, Referenced to 1 % THD+N Output Level | 112.5 | dB | ||
KCP | Click and pop performance | Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. | 3.4 | mV | ||
Programmable output level range | 8 | 18 | dBV | |||
Programmable output level step size | 0.5 | dB | ||||
AVERROR | Amplifier gain error | POUT = 1 W | ±0.1 | dB | ||
Mute attenuation | Device in Shutdown or Muted in Normal Operation | 110 | dB | |||
VBAT power-supply rejection ratio | VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz | 108 | dB | |||
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz | 90 | dB | ||||
AVDD power-supply rejection ratio | VDD = 1.8 V + 200 mVpp, fripple = 217 Hz | 98 | dB | |||
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz | 93 | dB | ||||
Turn on time from release of SW shutdown | No Volume Ramping | 1.8 | ms | |||
Volume Ramping | 4.5 | ms | ||||
Turn off time from assertion of SW shutdown to amp Hi-Z | No Volume Ramping | 1.5 | ms | |||
Volume Ramping | 12.5 | ms | ||||
AMPLIFIER PERFORMANCE - External PVDD | ||||||
Output Voltage for Full-scale digital Input | Measured at -6 dB FS input | 7.94 | Vrms | |||
POUT | Maximum Continuous Output Power | RL = 32Ω + 33 µH, THD+N = 1 %, fin = 1 kHz | 1.3 | W | ||
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz | 5.2 | W | ||||
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz | 10.4 | W | ||||
RL = 32Ω + 33 µH, THD+N = 10 %, fin = 1 kHz | 1.6 | W | ||||
RL = 8 Ω + 33 µH, THD+N = 10 %, fin = 1 kHz | 6.3 | W | ||||
RL = 4 Ω + 33 µH, THD+N = 10%, fin = 1 kHz | 12.6 | W | ||||
System efficiency at POUT = 1 W | RL = 8 Ω + 33 µH, fin = 1 kHz | 83.8 | % | |||
RL = 4 Ω + 33 µH, fin = 1 kHz | 80 | % | ||||
RL = 8 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V | 85.9 | % | ||||
RL = 4 Ω + 33 µH, fin = 1 kHz, External PVDD = 8.4 V | 81.8 | % | ||||
System efficiency at 0.1% THD+N power level | RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, | 87.4 | % | |||
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, | 90 | % | ||||
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz | 85.2 | % | ||||
RL = 32 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V | 81.9 | % | ||||
RL = 8 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V | 90 | % | ||||
RL = 4 Ω + 33 µH, POUT = TBD W, fin = 1 kHz, External PVDD = 8.4 V | 86 | % | ||||
THD+N | Total harmonic distortion + noise | POUT = 0.25 W, RL = 32Ω + 33 µH, fin = 1 kHz | 0.01 | % | ||
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz | 0.01 | % | ||||
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz | 0.02 | % | ||||
VN | Idle channel noise | A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running | 21.3 | µV | ||
FPWM | Class-D PWM switching frequency | Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 | 384 | kHz | ||
Fixed Frequency Mode, CLASSD_SYNC=0 | 384 | kHz | ||||
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz | 352.8 | kHz | ||||
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz | 384 | kHz | ||||
VOS | Output offset voltage | -1 | 1 | mV | ||
DNR | Dynamic range | A-Weighted, -60 dBFS Method | 105 | dB | ||
SNR | Signal to noise ratio | A-Weighted, Referenced to 1 % THD+N Output Level | 109.5 | dB | ||
KCP | Click and pop performance | Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. Measured with APx Plugin. | 3 | mV | ||
Programmable output level range | 8 | 18 | dBV | |||
Programmable output level step size | 0.5 | dB | ||||
AVERROR | Amplifier gain error | POUT = 1 W | ±0.1 | dB | ||
Mute attenuation | Device in Shutdown or Muted in Normal Operation | 110 | dB | |||
VBAT power-supply rejection ratio | VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz | 110 | dB | |||
VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz | 90 | dB | ||||
PVDD power-supply rejection ratio | PVDD = 12 V + 200 mVpp, fripple = 217 Hz | 105 | dB | |||
PVDD = 12 V + 200 mVpp, fripple = 20 kHz | 90 | dB | ||||
AVDD power-supply rejection ratio | VDD = 1.8 V + 200 mVpp, fripple = 217 Hz | 86 | dB | |||
VDD = 1.8 V + 200 mVpp, fripple = 20 kHz | 73 | dB | ||||
Turn on time from release of SW shutdown | No Volume Ramping | 2 | ms | |||
Volume Ramping | 4.8 | ms | ||||
Turn off time from assertion of SW shutdown to amp Hi-Z | No Volume Ramping | 1.08 | ms | |||
Volume Ramping | 12.58 | ms | ||||
BOOST CONVERTER |
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Startup inrush current limit | default setting | 1.5 | A | |||
Startup inrush limit time | default setting | 0.45 | ms | |||
Switching Frequency | PFM mode | 50 | kHz | |||
Current Control Mode | 4 | MHz | ||||
Inductor Peak Current Limit | default setting | 4 | A | |||
DIE TEMPERATURE SENSOR |
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Resolution | 8 | bits | ||||
Die temperature measurement range | -40 | 150 | °C | |||
Die temperature resolution | 0.75 | °C | ||||
Die temperature accuracy | ±5 | °C | ||||
VOLTAGE MONITOR |
||||||
Resolution | 10 | bits | ||||
VBAT measurement range | 2 | 6 | V | |||
VBAT resolution | 6 | mV | ||||
VBAT accuracy | ±25 | mV | ||||
PDM INPUT PORT | ||||||
SNR | Signal to Noise Ratio | No signal, Input generated using a 4th order PDM modulator | 118 | dB | ||
No signal, Input generated using a 5th order PDM modulator | 128 | |||||
DR | Dynamic Range | 20Hz to 20kHz, -60dBFS input signal, A-weighted, Input generated using a 4th order PDM modulator | 117 | dB | ||
20Hz to 20kHz, -60dBFS input signal, A-weighted, Input generated using a 5th order PDM modulator | 127 | |||||
FR | Frequency Response | 20Hz to 20kHz | -0.1 | 0 | dB | |
GD | Group Delay | Input signal fs/50 | TBD | FSYNC Cycles | ||
TDM SERIAL AUDIO PORT |
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PCM Sample Rates & FSYNC Input Frequency | 8 | 96 | kHz | |||
SBCLK Input Frequency | I2S/TDM Operation | 0.512 | 24.57 | MHz | ||
SBCLK Maximum Input Jitter | RMS Jitter below 40 kHz that can be tolerated without performance degradation | 1 | ns | |||
RMS Jitter above 40 kHz that can be tolerated without performance degradation | 10 | ns | ||||
SBCLK Cycles per FSYNC in I2S and TDM Modes | Values: 64, 96, 128, 192, 256, 384 and 512 | 64 | 512 | Cycles | ||
PCM PLAYBACK CHARACTERISTICS to fs ≤ 48 kHz |
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fs | Sample Rates | 8 | 48 | kHz | ||
Passband LPF Corner | 0.454 | fs | ||||
Passband Ripple | 20 Hz to LPF cutoff | -0.3 | 0.3 | dB | ||
Stop Band Attenuation | ≥ 0.55 fs | 60 | dB | |||
≥ 1 fs | 65 | dB | ||||
Group Delay (ROM MODE) | DC to 0.454 fs | 38 | 1/fs | |||
Group Delay (RAM Mode) | DC to 0.454 fs | TBD | 1/fs | |||
PCM PLAYBACK CHARACTERISTICS fs > 48 kHz |
||||||
fs | Sample Rates | 88.2 | 96 | kHz | ||
Passband LPF Corner | fs = 96 kHz | 0.42 | fs | |||
fs = 192 kHz | 0.21 | fs | ||||
Passband Ripple | DC to LPF cutoff | -0.5 | 0.5 | dB | ||
Stop Band Attenuation | ≥ 0.55 fs | 60 | dB | |||
≥ 1 fs | 65 | dB | ||||
Group Delay (RAM Mode) | DC to 0.375 fs for 96 kHz | TBD | 1/fs | |||
CURRENT SENSE |
||||||
DNR | Dynamic range | Un-Weighted, Relative to 0 dBFS | 69 | dB | ||
THD+N | Total harmonic distortion + noise | RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 1 W | -56 | dB | ||
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 1 W | -57 | dB | ||||
Full-scale input current | 2.0 | A | ||||
Current-sense accuracy | RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W @ 1kHz) | ±1 | % | |||
Current-sense gain error over temperature | 0°C to 70°C, 8 Ω, using a 60Hz -40dB pilot tone | ±1 | % | |||
Current-sense gain error over output power | 50mW to 0.1 % THD+N level, fin = 1 kHz, 8 Ω, using a 60Hz -40dB pilot tone | ±1.5 | % | |||
LPF passband corner | fs = 8 kHz to 48 kHz | 0.417 | fs | |||
fs = 88.2 kHz | 0.208 | fs | ||||
fs = 96 kHz | 0.208 | fs | ||||
LPF passband ripple | -0.05 | 0.05 | dB | |||
LPF stopband attenuation | 0.55 fs | 60 | dB | |||
VOLTAGE SENSE |
||||||
DNR | Dynamic range | Un-Weighted, Relative 0 dBFS | 69 | dB | ||
THD+N | Total harmonic distortion + noise | RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 1W | -60 | dB | ||
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 1W | -60 | dB | ||||
Full-scale input voltage | 14 | VPK | ||||
Voltage-sense accuracy | RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) | ±0.5% | ||||
Voltage-sense gain error over temperature | 0°C to 70°C, 8 Ω, using a 60Hz -40dB pilot tone | ±0.5% | ||||
Voltage-sense gain error over output power | 50mV to 0.1 % THD+N level, 8 Ω, using a 60Hz -40dB pilot tone | ±0.5% | ||||
LPF passband corner | fs = 14.7 kHz to 48 kHz | 0.417 | fs | |||
fs = 88.2 kHz | 0.208 | fs | ||||
fs = 96 kHz | 0.208 | fs | ||||
LPF passband ripple | -0.05 | 0.05 | dB | |||
LPF stopband attenuation | 0.55 fs | 60 | dB | |||
VOLTAGE/CURRENT SENSE RATIO |
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Gain ratio error over output power | 50mW to 0.1 % THD+N level, fin = 1 kHz, 8Ω, using a 60Hz -40dB pilot tone | ±1% | ||||
Gain ratio drift over temperature | 0°C to 70°C | ±1% | ||||
V/I phase error | 300 | ns | ||||
TYPICAL CURRENT CONSUMPTION |
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Current consumption in hardware shutdown | SDZ = 0, VBAT | 1 | µA | |||
SDZ = 0, VDD | 1 | µA | ||||
Current consumption in software shutdown | All Clocks Stopped, VBAT | 1 | µA | |||
All Clocks Stopped, VDD | 10 | µA | ||||
Current consumption in idle channel | Clocking 0s PCM mode, VBAT | 2.7 | mA | |||
Clocking 0s PCM mode, VDD, DSBGA Package | 10.9 | mA | ||||
Clocking 0s PCM mode, VDD, QFN Package | 11.7 | mA | ||||
Current consumption during active operation with IV sense disabled | fs = 48 kHz, VBAT | 4.6 | mA | |||
fs = 48 kHz, VDD, DSBGA Package | 10.9 | mA | ||||
fs = 48 kHz, VDD, QFN Package | 11.7 | mA | ||||
Current consumption during active operation with IV sense enabled | fs = 48 kHz, VBAT | 4.6 | mA | |||
fs = 48 kHz, VDD, DSBGA Package | 12.5 | mA | ||||
fs = 48 kHz, VDD, QFN Package | 13.3 | mA | ||||
PROTECTION CIRCUITRY |
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Thermal shutdown temperature | 140 | °C | ||||
Thermal shutdown retry | 1.5 | s | ||||
VBAT undervoltage lockout threshold (UVLO) | UVLO is asserted | 2 | V | |||
UVLO is released | 2.55 | V | ||||
Output short circuit limit | Output to Output, Output to GND, Output to VBST or Output to VBAT Short | 3.75 | A |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Standard-Mode | |||||
fSCL | SCL clock frequency | 0 | 100 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4 | μs | ||
tLOW | LOW period of the SCL clock | 4.7 | μs | ||
tHIGH | HIGH period of the SCL clock | 4 | μs | ||
tSU;STA | Setup time for a repeated START condition | 4.7 | μs | ||
tHD;DAT | Data hold time: For I2C bus devices | 0 | 3.45 | μs | |
tSU;DAT | Data set-up time | 250 | ns | ||
tr | SDA and SCL rise time | 1000 | ns | ||
tf | SDA and SCL fall time | 300 | ns | ||
tSU;STO | Set-up time for STOP condition | 4 | μs | ||
tBUF | Bus free time between a STOP and START condition | 4.7 | μs | ||
Cb | Capacitive load for each bus line | 400 | pF | ||
Fast-Mode | |||||
fSCL | SCL clock frequency | 0 | 400 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.6 | μs | ||
tLOW | LOW period of the SCL clock | 1.3 | μs | ||
tHIGH | HIGH period of the SCL clock | 0.6 | μs | ||
tSU;STA | Setup time for a repeated START condition | 0.6 | μs | ||
tHD;DAT | Data hold time: For I2C bus devices | 0 | 0.9 | μs | |
tSU;DAT | Data set-up time | 100 | ns | ||
tr | SDA and SCL rise time | 20 + 0.1 × Cb | 300 | ns | |
tf | SDA and SCL fall time | 20 + 0.1 × Cb | 300 | ns | |
tSU;STO | Set-up time for STOP condition | 0.6 | μs | ||
tBUF | Bus free time between a STOP and START condition | 1.3 | μs | ||
Cb | Capacitive load for each bus line | 400 | pF | ||
Fast-Mode Plus |
|||||
fSCL | SCL clock frequency | 0 | 1000 | kHz | |
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 0.26 | μs | ||
tLOW | LOW period of the SCL clock | 0.5 | μs | ||
tHIGH | HIGH period of the SCL clock | 0.26 | μs | ||
tSU;STA | Setup time for a repeated START condition | 0.26 | μs | ||
tHD;DAT | Data hold time: For I2C bus devices | 0 | μs | ||
tSU;DAT | Data set-up time | 50 | ns | ||
tr | SDA and SCL Rise Time | 120 | ns | ||
tf | SDA and SCL Fall Time | 120 | ns | ||
tSU;STO | Set-up time for STOP condition | μs | |||
tBUF | Bus free time between a STOP and START condition | 0.5 | μs | ||
Cb | Capacitive load for each bus line | TBD | pF |
SYMBOL | PARAMETER | CONDITIONS | IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||
---|---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | ||||
tsck | SCLK Period | 60 | 50 | ns | |||
tsckh | SCLK Pulse width High | 30 | 25 | ns | |||
tsckl | SCLK Pulse width Low | 30 | 25 | ns | |||
tlead | Enable Lead Time | 60 | 50 | ns | |||
ttrail | Enable Trail Time | 60 | 50 | ns | |||
td;seqxfr | Sequential Transfer Delay | 60 | 50 | ns | |||
ta | Slave DOUT access time | 35 | 25 | ns | |||
tdis | Slave DOUT disable time | 35 | 25 | ns | |||
tsu | DIN data setup time | 8 | 8 | ns | |||
th;DIN | DIN data hold time | 8 | 8 | ns | |||
tv;DOUT | DOUT data valid time | 35 | 25 | ns | |||
tr | SCLK Rise Time | 4 | 4 | ns | |||
tf | SCLK Fall Time | 4 | 4 | ns | |||
Pd-spi | External Pullup on SPII2CSELZ_MISO_PAD | 18 | 18 | kΩ |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tSU(PDM) | PDM IN setup time | 20 | ns | |||
tHLD(PDM) | PDM IN hold time | 3 | ns | |||
tr(PDM) | PDM IN rise time | 10 % - 90 % Rise Time | 4 | ns | ||
tf(PDM) | PDM IN fall time | 90 % - 10 % Fall Time | 4 | ns |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tH(SBCLK) | SBCLK high period | 20 | ns | |||
tL(SBCLK) | SBCLK low period | 20 | ns | |||
tSU(FSYNC) | FSYNC setup time | 6.5 | ns | |||
tHLD(FSYNC) | FSYNC hold time | 6.5 | ns | |||
tSU(FSYNC) | SDIN setup time | 6.5 | ns | |||
tHLD(SDIN) | SDIN hold time | 6.5 | ns | |||
td(DO-SBCLK) | SBCLK to SDOUT delay | 50% of SBCLK to 50% of SDOUT | 29 | ns | ||
tr(SBCLK) | SBCLK rise time | 10% - 90 % Rise Time | 8 | ns | ||
tf(SBCLK) | SBCLK fall time | 90% - 10 % Fall Time | 8 | ns |