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  • TAS2563具有集成式 DSP 和 IV 检测功能的 6.1W 升压 D 类音频放大器

    • ZHCSJB4D April   2019  – January 2024 TAS2563

      PRODUCTION DATA  

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  • TAS2563具有集成式 DSP 和 IV 检测功能的 6.1W 升压 D 类音频放大器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2C Timing Requirements
    7. 5.7  SPI Timing Requirements
    8. 5.8  PDM Port Timing Requirements
    9. 5.9  TDM Port Timing Requirements
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PurePath Console 3 Software
      2. 7.3.2  Device Mode and Address Selection
      3. 7.3.3  General I2C Operation
      4. 7.3.4  General SPI Operation
      5. 7.3.5  Single-Byte and Multiple-Byte Transfers
      6. 7.3.6  Single-Byte Write
      7. 7.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 7.3.8  Single-Byte Read
      9. 7.3.9  Multiple-Byte Read
      10. 7.3.10 Register Organization
      11. 7.3.11 Operational Modes
        1. 7.3.11.1 Hardware Shutdown
        2. 7.3.11.2 Software Shutdown
        3. 7.3.11.3 Mute
        4. 7.3.11.4 Active
        5. 7.3.11.5 Perform Load Diagnostics
        6. 7.3.11.6 Mode Control and Software Reset
      12. 7.3.12 Faults and Status
      13. 7.3.13 Digital Input Pull Downs
    4. 7.4 Device Functional Modes
      1. 7.4.1 PDM Input
      2. 7.4.2 TDM Port
      3. 7.4.3 Playback Signal Path
        1. 7.4.3.1 Digital Signal Processor
        2. 7.4.3.2 High Pass Filter
        3. 7.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 7.4.3.4 Auto-mute During Idle Channel Mode
        5. 7.4.3.5 Auto-start/stop on Audio Clocks
        6. 7.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 7.4.3.7 Class-D Settings
      4. 7.4.4 SAR ADC
      5. 7.4.5 Boost
      6. 7.4.6 IV Sense
      7. 7.4.7 Load Diagnostics
      8. 7.4.8 Clocks and PLL
      9. 7.4.9 Thermal Foldback
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table Page=0x00
      2. 7.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 7.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 7.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 7.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 7.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 7.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 7.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 7.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
      1. 9.2.1 Boost Supply Details
      2. 9.2.2 External Boost Mode (Boost Bypass Mode)
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
  15. 重要声明
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Data Sheet

TAS2563具有集成式 DSP 和 IV 检测功能的 6.1W 升压 D 类音频放大器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 主要特性
    • 11.5V、12 级超前 H 级升压
    • 集成型 DSP
    • 高达 40kHz 的满量程超声波输出
    • 2 个 PDM 麦克风输入
  • 强大的 D 级音频放大器:
    • 6.1W 1% THD+N(4Ω,3.6V)
    • 5W 1% THD+N(8Ω,3.6V)
    • 10W 1% THD+N(4Ω,12V)
  • 保护特性:
    • 实时 I/V 检测扬声器保护
    • 扬声器热保护和过冲保护
    • 短路和开路负载保护
    • 热保护和过流保护
  • 高级音频处理
    • 专用实时 DSP,具有:
      • 10 频带均衡器
      • 3 频带动态均衡器
      • 动态范围压缩
      • 心理声学低音
  • 灵活的接口和控制:
    • I2S/TDM:8 个通道(32 位),运行速率达 96KSPS
    • I2C:可选择地址,快速模式+
    • 芯片间通信总线 (DSBGA)
    • 8kHz 至 96kHz 采样速率
  • 电源效率和灵活性:
    • 功率为 1W 时效率达 83.5%
    • 硬件关断 VBAT 电流低于 1uA
    • 升压旁路模式
  • 电源和管理
    • VBAT:2.5V 至 5.5V
    • VDD:1.62V 至 1.95V
    • PVDD:VBAT 至 13V (QFN)
    • PVDD:VBAT 至 15V(QFN,VBAT < 3.5V)

    • PVDD:VBAT 至 16V (DSBGA)
    • IOVDD:1.65V 至 3.6V
    • VBAT 跟踪峰值电压限制器
    • 高级欠压保护功能

2 应用

  • 智能手机、平板电脑和笔记本电脑
  • 智能音箱(带语音助理)
  • 蓝牙和无线音箱
  • 智能家居
  • IP 摄像机

3 说明

TAS2563 是一款经过优化、可将高峰值功率高效地驱动到小型扬声器的数字输入 D 级音频放大器。该 D 类放大器能够在 3.6V 的电池电压下使用集成式 11.5V H 类升压功能将 6.1W 峰值功率提供给 4Ω 负载,或在升压旁路模式下使用外部 12V 电源将 10W 峰值功率提供给 4Ω 负载。

片上低延迟 DSP 支持德州仪器 (TI) 的 SmartAmp 扬声器保护算法。集成的电流和电压检测功能可对扬声器进行实时监测,从而在改变峰值声压级 (SPL) 的同时保持扬声器不受损坏。

集成的超前 H 级升压功能可在播放期间动态调整升压电压,从而提高电池供电型系统的效率并延长电池寿命。对于稳压壁式供电型系统,TAS2563 还具有升压旁路模式,支持高达 16V 的电源电压以实现更高的输出功率。

两个 PDM 麦克风输入简化了双向音频系统的音频信号链,能够将数字麦克风与主机处理器连接起来。电池跟踪峰值电压限制器具有欠压保护功能,可以优化放大器在整个充电周期中的余量,从而防止系统关断。

器件信息(1)
器件型号封装封装尺寸(标称值)
TAS2563DSBGA 2.5mm × 3mm
TAS2563QFN4.5mm x 4mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
GUID-EC119251-1BF4-4DD3-BC3C-EE2416568268-low.gif简化版原理图

4 Pin Configuration and Functions

GUID-E118263F-E7D9-410E-8691-B76BC2E56297-low.gifFigure 4-1 YBG Package42-Ball DSBGATop View
GUID-97D0F758-FFEC-4758-AAE0-3702546ED8AD-low.gifFigure 4-2 RPP Package32-pin QFNTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME DSBGA NO. QFN NO.
ADDR_SPICLK C4 19 I I2C Mode - Address selection pin See General I2C operation. SPI Mode - SPI clock
DREG B6 2 P Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load.
FSYNC B3 5 I I2S word clock or TDM frame sync for ASI1 and ASI2 channels.
GNDB E1, E2, E3 14 P Boost ground. Connect to PCB GND plane.
GNDD F4 28 P Digital ground. Connect to PCB GND plane.
GND E4 N/A P Analog ground. Connect to PCB GND plane.
GNDP E5,E6 27 P Power stage ground. Connect to PCB GND plane.
GPIO D6 22 IO General purpose input-ouput or MCLK base on register configuration.
GREG D4 13 P High-side gate CP regulator output. Do not connect to external load.
IOVDD A6 32 P 3.3-V/1.8-V IOVDD Supply
IRQZ C5 18 O Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up is not used.
OUT_N F6 26 O Class-D negative output for receiver channel.
OUT_P F5 21 O Class-D positive output for receiver channel.
PDMCLK A1 9 IO PDM clock.
PDMD A2 24 IO PDM data.
PVDD G4, G5, G6 25 P Power stage supply.
SBCLK1 B2 6 I ASI1 channel I2S/TDM serial bit clock.
SBCLK2 A5 I ASI2 channel I2S/TDM serial bit clock.
SDA_MOSI B5 3 IO I2C Mode: I2C Data Pin. Pull up to IOVDD with a resistor. SPI Mode: Serial data input pin.
SDIN1 C2 11 I ASI1 channel I2S/TDM serial data input.
SDIN2 A4 I ASI2 channel I2S/TDM serial data input.
SDOUT1 C1 10 IO ASI1 channel I2S/TDM serial data output.
SDOUT2 A3 IO ASI2 channel I2S/TDM serial data output.
SDZ B1 7 I Active low hardware shutdown.
SCL_SELZ B4 4 IO I2C Mode: I2C clock pin. Pull up to IOVDD with a resistor. SPI Mode: active low chip select.
SPII2CZ_MISO C3 12 IO Pin is queried on power-up. Short to GND for I2C Mode. Pull to IOVDD with resistor for SPI mode. SPI serial data output pin.
SW F1, F2, F3 15 P Boost converter switch input.
VBAT D1, D2 30 P Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with a cap.
VBST G1, G2, G3 16 P Boost converter output. Do not connect to external load.
VDD C6 31 P Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to GND with cap.
VSNS_N D3 29 I Voltage sense negative input. Connect to Class-D OUT_N output after Ferrite bead filter.
VSNS_P D5 20 I Voltage sense positive input. Connect to Class-D OUT_P output after Ferrite bead filter.
NC 1, 8, 17 No Connect.
(1) I = Input, P = Power, O = Output

5 Specifications

 

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