• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TPS3703-Q1具有延时时间和手动复位功能的过压和欠压复位 IC

    • ZHCSIZ9D November   2018  – March 2021 TPS3703-Q1

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • TPS3703-Q1具有延时时间和手动复位功能的过压和欠压复位 IC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD
      2. 8.3.2 SENSE
      3. 8.3.3 RESET
      4. 8.3.4 Capacitor Time (CT)
      5. 8.3.5 Manual Reset ( MR)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(MIN))
      2. 8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Voltage Threshold Accuracy
      2. 9.1.2 CT Reset Time Delay
        1. 9.1.2.1 Factory-Programmed Reset Delay Timing
        2. 9.1.2.2 Programmable Reset Delay-Timing
      3. 9.1.3 RESET Latch Mode
      4. 9.1.4 Adjustable Voltage Thresholds
      5. 9.1.5 Immunity to SENSE Pin Voltage Transients
        1. 9.1.5.1 Hysteresis
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: RESET Latch Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Evaluation Module
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPS3703-Q1具有延时时间和手动复位功能的过压和欠压复位 IC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合面向汽车应用的 AEC-Q100 标准：
    • 温度等级 1：–40°C 至 +125°C，TA
    • 器件 HBM ESD 分类等级 2
    • 器件 CDM ESD 分类等级 C7B
  • 提供功能安全
    • 可帮助进行功能安全系统设计的文档
  • 输入电压范围：1.7V 至 5.5V
  • 欠压锁定 (UVLO)：1.7V
  • 低静态电流：7µA（最大值）
  • 高阈值精度：
    • ±0.25%（典型值）
    • ±0.7%（-40°C 至 +125°C）
  • 固定窗口阈值电平
    • 50mV 阶跃（500mV 至 1.3V）
    • 1.5V、1.8V、2.5V、2.8V、2.9V、3.3V、5V
    • 仅使用 UV 阈值
    • 窗口公差范围为 ±3% 至 ±7%
  • 用户可调的电压阈值电平
  • 内部毛刺抑制和迟滞
  • 固定延时时间选项：50µs、1ms、5ms、10ms、20ms、100ms、200ms
  • 使用单个外部电容器的可编程延时时间选项
  • 漏极开路低电平有效 UV 和 OV 监控器
  • RESET 电压锁存输出模式

2 应用

  • 高级驾驶辅助系统 (ADAS)
  • ADAS 域控制器
  • 汽车信息娱乐系统和仪表组
  • 数字驾驶舱
  • 混合动力汽车/电动汽车
GUID-76F47A7A-3946-45E6-A5AF-5373FEEE652A-low.gif集成式过压和欠压检测

3 说明

TPS3703-Q1 器件是一款集成式过压 (OV) 和欠压 (UV) 监控器或复位 IC，采用业界最小的 6 引脚 DSE 封装。这款高精度的电压监控器非常适合采用低电压电源轨的系统，并具有非常小的电源容差裕度。低阈值迟滞可防止在受监控的电压处于正常工作范围内时发出虚假复位信号。并且内置有毛刺抑制功能和噪声滤波器，进一步消除了错误信号所导致的错误复位。

TPS3703-Q1 不需要使用任何外部电阻器来设置过压和欠压复位阈值，因此进一步优化了整体精度、成本、解决方案大小并提高了安全系统的可靠性。电容器时间 (CT) 引脚用于在每个器件的两个可用复位延时时间之间进行选择，还可以连接一个电容器以调整复位延时时间。单独的 SENSE 输入引脚和 VDD 引脚可实现高可靠性系统所需的冗余。

此器件的低典型静态电流规格为 4.5µA（典型值）。TPS3703-Q1 符合 AEC-Q100 1 级标准，适用于汽车应用。

器件信息(1)
器件型号封装封装尺寸（标称值）
TPS3703-Q1WSON (6)1.50mm x 1.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-C084FD53-C357-4E21-A85C-F6C96C4DEA79-low.gif典型过压精度分布

4 Revision History

Changes from Revision C (February 2020) to Revision D (March 2021)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 包含了“功能安全”要点Go
  • Replaced Device Comparison Table with device nomenclature legendGo

Changes from Revision B (September 2019) to Revision C (February 2020)

  • Changed reset time delay nomenclature (tD): J to M by A to HGo

Changes from Revision A (May 2019) to Revision B (September 2019)

  • 仅删除了整篇文档中的 OVGo
  • 将整个文档中的阈值公差更改为窗口公差Go
  • Added new voltage variants for window and UV only.Go
  • Added pinout description for package.Go
  • Changed functional block diagram for clarity between variants. Go
  • Added UV only normal operation condition. Go
  • Changed equation to correctly reflect resistor divider. Go
  • Changed to R1 from RSENSE Go

Changes from Revision * (November 2018) to Revision A (May 2019)

  • 将“预告信息”更改为“量产数据”发布Go

5 Device Comparison

Figure 5-1 shows the device nomenclature of the TPS3703-Q1. For all possible voltages, window tolerance, time delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for details and availability of other options; minimum order quantities apply.

Figure 5-1 Device Nomenclature Legend

6 Pin Configuration and Functions

GUID-AC7249A5-3939-4CDA-81AF-DAA71DF8ECB5-low.gifFigure 6-1 DSE Package,6-Pin WSON,Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 SENSE I Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if monitoring VDD supply voltage.
2 VDD I Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to this pin.
3 CT I Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or leaving it floating. Delay time can be programmed by connecting an external capacitor reference to ground.
4 RESET O Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally overvoltage threshold (VIT+) or below the undervoltage threshold (VIT–). See the timing diagram in Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.
5 GND — Ground
6 MR I Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not in use.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VoltageVDD–0.36V
VRESET–0.36
VCT–0.36
VSENSE–0.36
VMR–0.36
CurrentIRESET±40mA
Temperature (2)Continuous total power dissipationSee the Thermal Information
Operating junction temperature, TJ–40150°C
Operating free-air temperature, TA–40150
Storage temperature, Tstg–65150
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale