DATA SHEET
TPS568230 4.5V 至 18V 输入、8A 同步降压稳压器
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1 特性
- 输入电压范围：4.5V 至 18V
- D-CAP3™架构控制，可实现快速瞬态响应
- 输出电压范围：0.6V 至 7V
- 0.6V ±1% 基准电压 (25°C)
- 支持 8A 的连续输出电流
- 集成 19.5mΩ 和 9.5mΩ RDS(on) 内部功率 MOSFET
- ULQ™（超低静态电流）功能，可实现较长的电池寿命
- 可选择运行模式：
- 强制连续导通模式 (FCCM)
- Out-of-Audio™(OOA) 模式
- 高级 Eco-Mode™
- 可选 600kHz、800kHz 和 1MHz 开关频率
- 支持高达 90% 的负荷运行
- 可调节软启动时间（通过 SS 引脚调节）
- 电源正常状态输出
- 内置输出放电功能
- 逐周期过流保护
- 可提供故障保护的非锁存保护
- 小型 3.0mm × 3.0mm HotRod™QFN 封装
2 应用
- 数字电视、机顶盒、游戏机
- 服务器、存储和网络负载点
- 工业计算机和工厂自动化 应用
- 具有典型 5V、12V、15V 输入的分布式电源系统
3 说明
TPS568230 是一款配备了集成 MOSFET 且具有成本效益、高电压输入、高效的同步降压转换器。
TPS568230 具有 ULQ™（超低静态电流）功能，可实现低偏置电流。其工作电源输入电压范围为 4.5V 至 18V。该器件使用 DCAP3™ 控制模式提供快速瞬态响应、良好的线路和负载调节，无需外部补偿，并支持低等效串联电阻 (ESR) 输出电容器，如专用聚合物和超低 ESR 陶瓷电容器。
TPS568230 具有完整的过压、欠压、过流、过热以及欠压锁定保护功能。它结合了电源正常信号、输出放电功能和大负荷运行功能。
TPS568230 配备了 MODE 引脚，用于选择所需的运行模式。为了在轻负载条件下实现高效率，可选择 OOA 模式和高级 Eco-mode™。OOA 模式不允许器件低于可闻频率（低于 25kHz 开关频率）。FCCM 还符合严格的输出电压纹波要求。
TPS568230 同时支持内部和外部软启动时间选项。内部固定软启动时间为 1.3ms。更长的软启动时间可通过在 SS 引脚上连接外部电容器来实现。
TPS568230 采用 20 引脚 3.0mm x 3.0mm HotRod™封装，额定结温范围为 -40oC 至 125oC。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| TPS568230 | VQFN (20) | 3.00mm × 3.00mm |
- 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
Device Images
典型应用
效率与输出电流 ECO 模式
4 修订历史记录
Changes from B Revision (March 2019) to C Revision
- Added VENH min value 1.21VGo
- Changed VENH typical value from 1.2V to 1.31VGo
- Changed VENL min value from 0.8V to 0.95VGo
- Changed VENLtypical value from 1.05V to 1.11VGo
- Added VENL max value 1.19V Go
Changes from A Revision (February 2019) to B Revision
- Changed SW negative voltage for DC change from -2V to -1VGo
Changes from * Revision (October 2018) to A Revision
- Changed 将销售状态从“预告信息”更改为“生产数据”。Go
5 Pin Configuration and Functions
RJE Package
20-Pin VQFN
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BST | 1 | I | Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between BST and SW, 0.1uF is recommended. |
| VIN | 2,3,4,5 | P | Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and GND. |
| SW | 6,19,20 | O | Switch node terminal. Connect the output inductor to this pin. |
| GND | 7,8,18,Pad | G | Power GND terminal for the controller circuit and the internal circuitry. |
| PGOOD | 9 | O | Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over voltage or if the device is under thermal shutdown, EN shutdown or during soft start. |
| SS | 11 | I | Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the soft-start time is about 1.3ms. |
| NC | 10,16 | Not connect. Can be connected to GND plane for better thermal achieved. | |
| EN | 12 | I | Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal pull down current to disable converter if leave this pin open. |
| AGND | 13 | G | Ground of internal analog circuitry. Connect AGND to GND plane with a short trace. |
| FB | 14 | I | Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND. |
| MODE | 15 | I | Switching frequency and light load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND, the different MODE options are shown in Table 1 |
| VCC | 17 | O | 5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 1-μF capacitor. |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Input voltage | VIN | –0.3 | 22 | V | |
| VBST | –0.3 | 27 | V | ||
| VBST-SW | –0.3 | 6 | V | ||
| MODE, FB, SS | –0.3 | 6 | V | ||
| EN | –0.3 | 4 | V | ||
| GND, AGND | –0.3 | 0.3 | V | ||
| Output voltage | SW | –1 | 22 | V | |
| SW (10-ns transient) | –3 | 23 | V | ||
| PGOOD | –0.3 | 6 | V | ||
| TJ | Operating junction temperature | –40 | 150 | °C | |
| Tstg | Storage temperature | –55 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22- V C101(2) | ±500 | V | ||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)6.4 Thermal Information
| THERMAL METRIC(1) | TPS568230 | UNIT | |
|---|---|---|---|
| RJE (VQFN) | |||
| 20 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 44.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 32.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 13.3 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1.3 | °C/W |
| ψJB | Junction-to-board characterization parameter | 13.5 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 16.1 | °C/W |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted| PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT | ||||||
| VIN | Input voltage range | VIN | 4.5 | 18 | V | |
| IVIN | VIN supply current | No load, VEN=3.3V, non-switching | 105 | uA | ||
| IVINSDN | Shutdown supply current | No load, VEN=0V | 2 | uA | ||
| VCC OUTPUT | ||||||
| VCC | VCC output voltage | VVIN>5.0V | 4.85 | 5 | 5.15 | V |
| VVIN=4.5V | 4.5 | V | ||||
| ICC | VCC current limit | 20 | mA | |||
| FEEDBACK VOLTAGE | ||||||
| VFB | FB voltage | TJ = 25°C | 594 | 600 | 606 | mV |
| TJ = -40°C to 125°C | 592 | 600 | 611 | mV | ||
| DUTY CYCLE and FREQUENCY CONTROL | ||||||
| FSW | Switching frequency | TJ = 25°C , FSW=600kHz,Vo=1V | 600 | kHz | ||
| TON(MIN) | SW minumum on time | TJ = 25°C | 60 | ns | ||
| TOFF(MIN) | SW minimum off time | VFB = 0.5 V | 190 | ns | ||
| MOSFET and DRIVERS | ||||||
| RDS(ON)H | High side switch resistance | TJ = 25°C | 19.5 | mΩ | ||
| RDS(ON)L | Low side switch resistance | TJ = 25°C | 9.5 | mΩ | ||
| OOA FUNCTION | ||||||
| TOOA | OOA mode operation period | 28 | us | |||
| OUTPUT DISCHARGE and SOFT START | ||||||
| RDIS | Discharge resistance | TJ=25°C, VEN=0V | 420 | Ω | ||
| TSS | Soft start time | Internal soft-start time,SS floating | 1.3 | ms | ||
| ISS | Soft start charge current | 5 | uA | |||
| POWER GOOD | ||||||
| TPGDLY | PG start-up delay | PG from low to high | 1 | ms | ||
| VPGTH | PG threshold | VFB falling (fault) | 85 | % | ||
| VFB rising (good) | 90 | % | ||||
| VFB rising (fault) | 115 | % | ||||
| VFB falling (good) | 110 | % | ||||
| VPG_L | PG sink current capability | IOL =4mA | 0.4 | V | ||
| IPGLK | PG leak current | VPGOOD =5.5V | 1 | uA | ||
| CURRENT LIMIT | ||||||
| IOCL | Over current threshold | Valley current set point | 8.1 | 9.8 | 12 | A |
| INOCL | Negative over current threshold | 3.9 | A | |||
| LOGIC THRESHOLD | ||||||
| VENH | EN high-level input voltage | 1.21 | 1.31 | 1.4 | V | |
| VENL | EN low-level input voltage | 0.95 | 1.11 | 1.19 | V | |
| IEN | Enable internal pull down current | VEN=0.8V | 2 | µA | ||
| OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION | ||||||
| VOVP | OVP trip threshold | 125 | % | |||
| tOVPDLY | OVP prop deglitch | TJ=25°C | 20 | us | ||
| VUVP | UVP trip threshold | 60 | % | |||
| tUVPDLY | UVP prop deglitch | 256 | us | |||
| TUVPDEL | Output hiccup delay relative to SS time | 256 | us | |||
| TUVPEN | Output hiccup enable delay relative to SS time | 7 | cycle | |||
| UVLO | ||||||
| VUVLOVIN | VIN UVLO threshold | Wake up | 4.2 | 4.4 | V | |
| Shutdown | 3.6 | 3.8 | V | |||
| Hysteresis | 0.4 | V | ||||
| OVER TEMPERATURE PROTECTION | ||||||
| TOTP | OTP trip threshold(1) | Shutdown temperature | 150 | °C | ||
| TOTPHSY | OTP hysteresis(1) | Hysteresis | 20 | °C | ||
6.6 Typical Characteristics
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
| VEN = 3.3 V |
1.
Figure 3. Feedback Voltage vs Junction Temperature 
1.
Figure 5. Enable Off Voltage vs Junction Temperature 
1.
Figure 7. Low-Side RDS(on) vs Junction Temperature 
1.
Figure 9. UVP Threshold vs Junction Temperature 
1.
Figure 11. Valley Current Limit vs Junction Temperature 
1.
Figure 13. Efficiency, Eco-mode, FSW = 600 kHz 
1.
Figure 15. Efficiency, FCCM, FSW = 600 kHz 
1.
Figure 17. Efficiency, OOA-mode, FSW = 1 MHz 
1.
Figure 19. Load Regulation, Eco-mode, FSW = 600 kHz 
1.
Figure 21. FSW Load Regulation, OOA-mode, FSW = 600 kHz 
1.
Figure 23. FSW Load Regulation, Eco-mode, FSW = 800 kHz 
1.
Figure 25. FSW Load Regulation, FCCM, FSW = 800 kHz 
1.
Figure 27. FSW Load Regulation, FCCM, FSW = 800 kHz 
| VEN = 0 V |
1.
Figure 4. Enable On Voltage vs Junction Temperature 
1.
Figure 6. High-Side RDS(on) vs Junction Temperature 
1.
Figure 8. OVP Threshold vs Junction Temperature 
1.
Figure 10. Discharge Resistor vs Junction Temperature 
1.
Figure 12. Soft-Start Time vs Junction Temperature 
1.
Figure 14. Efficiency, OOA-mode, FSW = 600 kHz 
1.
Figure 16. Efficiency, Eco-mode, FSW = 1 MHz 
1.
Figure 18. Efficiency, FCCM, FSW = 1 MHz 
1.
Figure 20. FSW Load Regulation, Eco-mode, FSW = 600 kHz 
1.
Figure 22. FSW Load Regulation, FCCM, FSW = 600 kHz 
1.
Figure 24. FSW Load Regulation, OOA-mode, FSW = 800 kHz 
1.
Figure 26. FSW Load Regulation, FCCM, FSW = 600 kHz 
1.
Figure 28. FSW Load Regulation, FCCM, FSW = 1 MHz 7 Detailed Description
7.1 Overview
The TPS568230 is 8-A integrated FET synchronous buck converter which operates from 4.5V to 18V input voltage (VIN), and the output is from 0.6V to 7V. The proprietary D-CAP3™ mode enables low external component count, ease of design, optimization of the power design for cost, size and efficiency. The key feature of the TPS568230 is ultra-low quiescent current (ULQ™) mode. This feature is beneficial for long battery life in system standby mode. The device employs D-CAP3™ mode control that provides fast transient response with no external compensation components and an accurate feedback voltage. The control topology provides seamless transition between CCM operating mode at higher load condition and DCM operation at lighter load condition. Eco-mode™ allows the TPS568230 to maintain high efficiency at light load. OOA (out of audio) mode makes switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. FCCM mode has the constant switching frequency at both light and heavy load. The TPS568230 is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
