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  • 采用超小型封装的 ISO1500 3kVRMS 基础型隔离式 RS-485/RS-422 收发器

    • ZHCSIV2C September   2018  – September 2019 ISO1500

      PRODUCTION DATA.  

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  • 采用超小型封装的 ISO1500 3kVRMS 基础型隔离式 RS-485/RS-422 收发器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: Driver
    10. 6.10 Electrical Characteristics: Receiver
    11. 6.11 Supply Current Characteristics: Side 1(ICC1)
    12. 6.12 Supply Current Characteristics: Side 2(ICC2)
    13. 6.13 Switching Characteristics: Driver
    14. 6.14 Switching Characteristics: Receiver
    15. 6.15 Insulation Characteristics Curves
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 8.3.2 Failsafe Receiver
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Glitch-Free Power Up and Power Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Data Rate and Bus Length
        2. 9.2.2.2 Stub Length
        3. 9.2.2.3 Bus Loading
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

采用超小型封装的 ISO1500 3kVRMS 基础型隔离式 RS-485/RS-422 收发器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合或超出 TIA/EIA-485-A 要求
  • 半双工收发器
  • 低 EMI 1Mbps 数据速率
  • 总线 I/O 保护
    • ±16kV HBM ESD
  • 1.71V 至 5.5V 逻辑侧电源 (VCC1)，4.5V 至 5.5V 总线侧电源 (VCC2)
  • 1/8 单位负载：多达 256 个总线节点
  • 失效防护接收器（总线开路、短路和空闲）
  • 100kV/µs（典型值）高共模瞬态抗扰度
  • 扩展温度范围为 -40°C 至 +125°C
  • 适用于热插拔功能的无干扰加电和断电
  • 超小型 SSOP (DBQ-16) 封装
  • 安全相关认证：
    • 符合 DIN VDE V 0884-11:2017-01 标准的 4242VPK VIOTM 和 566VPK VIORM
    • 符合 UL 1577 标准且长达 1 分钟的 3000 VRMS 隔离
    • IEC 60950-1、IEC 62368-1 和 IEC 61010-1 认证
    • CQC、TUV 和 CSA 认证
    • VDE、UL、CQC 和 TUV 认证完成；等待 CSA 审批

2 应用

  • 电表
  • 保护继电器
  • 工厂自动化与控制
  • HVAC 系统和楼宇自动化
  • 电机驱动器

3 说明

ISO1500 器件是适用于 TIA/EIA RS-485 和 RS-422 应用的电隔离差动线路 收发器。该器件采用超小型 16 引脚 SSOP 封装，具有一个 3 通道数字隔离器和一个 RS-485 收发器。该收发器的总线引脚受到 IEC ESD 接触放电和 IEC EFT 事件保护。接收器输出具有针对总线开路、短路和空闲情况的失效防护。与其他集成的隔离式 RS-485 解决方案或采用光耦合器和非隔离式 RS-485 收发器的分立式实施相比，ISO1500 的小解决方案尺寸可极大地减少所需的布板空间。

该器件用于长距离通信。隔离会破坏通信节点之间的接地回路，从而获得更大的共模电压范围。经测试，每个器件的对称隔离层可在总线收发器和逻辑电平接口之间按照 UL 1577 标准提供为时 1 分钟的 3000VRMS 隔离。

ISO1500 器件可由 1 侧的 1.71V 至 5.5V 电压供电，从而使器件可与低压 FPGA 和 ASIC 相连接。2 侧的电源电压范围为 4.5V 至 5.5V。该器件支持 -40°C 至 +125°C 的宽工作环境温度范围。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ISO1500 SSOP (16) 4.90mm × 3.90mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简化原理图

ISO1500 iso1500-simplified-application-schematic.gif

4 修订历史记录

Changes from B Revision (May 2019) to C Revision

  • Changed 证书相关信息 特性 部分中的 VDE 和 CSA 安全相关认证说明Go
  • Added footnote to Pin function table for NC pinGo
  • Changed Insulation Specifications table with test condition for VIOSM and qPD (Partial discharge)Go
  • Changed certificate related info in Safety-Related Certifications sectionGo

Changes from A Revision (December 2018) to B Revision

  • Added 向特性列表中添加了 HBM ESDGo

Changes from * Revision (September 2018) to A Revision

  • Changed 将器件状态从“预告信息”更改为“生产数据”Go

5 Pin Configuration and Functions

DBQ Package
16-Pin SSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
A 12 I/O Transceiver noninverting input or output (I/O) on the bus side
B 13 I/O Transceiver inverting input or output (I/O) on the bus side
D 6 I Driver input
DE 5 I Driver enable. This pin enables the driver output when high and disables the driver output when low or open.
GND1 2 — Ground connection for VCC1
8
GND2 9 — Ground connection for VCC2
15
NC(1) 7 — No internal connection
11
14
R 3 O Receiver output
RE 4 I Receiver enable. This pin disables the receiver output when high or open and enables the receiver output when low.
VCC1 1 — Logic-side power supply
VCC2 10 — Transceiver-side power supply. These pins are not connected internally and must be shorted externally on PCB.
16
(1) Device functionality is not affected if NC pins are connected to supply or ground on PCB

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC1 Supply voltage, side 1 -0.5 6 V
VCC2 Supply voltage, side 2 -0.5 6 V
VIO Logic voltage level (D, DE, RE, R) -0.5 VCC1+0.5(3) V
IO Output current on R pin -15 15 mA
VBUS Voltage on bus pins (A, B, Y, Z w.r.t GND2) -18 18 V
TJ Junction temperature -40 150 ℃
TSTG Storage temperature -65 150 ℃
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001		 All pins except bus pins(1) ±4000 V
Bus terminals to GND2(1) ±16000 V
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101		 All pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC1 Supply Voltage, Side 1, 1.8-V operation 1.71 1.89 V
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation 2.25 5.5 V
VCC2 Supply Voltage, Side 2 4.5 5.5 V
VI Common mode voltage at any bus terminal: A or B -7 12 V
VIH High-level input voltage (D, DE, RE inputs) 0.7*VCC1 VCC1 V
VIL Low-level input voltage (D, DE, RE inputs) 0 0.3*VCC1 V
VID Differential input voltage -12 12 V
IO Output current, Driver -60 60 mA
IOR Output current, Receiver -4 4 mA
RL Differential load resistance 54 Ω
1/tUI Signaling rate 1 Mbps
TA Operating ambient temperature -40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) ISO1500 UNIT
DBQ (SSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 112.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.2 °C/W
RθJB Junction-to-board thermal resistance 64.0 °C/W
ΨJT Junction-to-top characterization parameter 32.1 °C/W
ΨJB Junction-to-board characterization parameter 63.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance -- °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) VCC1 = VCC2 = 5.5 V, TA=125°C, TJ = 150°C, A-B load = 54 Ω ||50pF, Load on R=15pF
Input a 500kHz 50% duty cycle square wave to D pin with VDE=VCC1, VRE=GND1		 278 mW
PD1 Maximum power dissipation (side-1) 28 mW
PD2 Maximum power dissipation (side-2) 250 mW

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
DBQ-16
IEC 60664-1
CLR External clearance (1) Side 1 to side 2 distance through air >3.7 mm
CPG External creepage (1) Side 1 to side 2 distance across package surface >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 300 VRMS I-III
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 400 VRMS
DC voltage 566 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 4242 VPK
VIOSM Maximum surge isolation voltage
ISO1500 (3) 		Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 10000 VPK (qualification) 4000 VPK
qpd Apparent charge (4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
 Vpd(m) = 1.6 × VIORM , tm = 10 s
 		 ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
 Vpd(m) = 1.875 × VIORM , tm = 1 s
 		 ≤ 5
CIO Barrier capacitance, input to output (5) VIO = 0.4 × sin (2 πft), f = 1 MHz ~1 pF
RIO Insulation resistance, input to output (5) VIO = 500 V,  TA = 25°C > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 150°C > 1011
VIO = 500 V at  TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1500 is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to DIN VDE V 0884-11:2017- 01 Plan to certify according to IEC 60950-1, IEC 62368-1 Recognized under UL 1577 Component Recognition Program Certified according to GB4943.1-2011 Certified according to EN 61010-1:2010/A1:2019, EN 60950-1:2006/A2:2013 and EN 62368-1:2014
Maximum transient isolation voltage,
4242 VPK;
Maximum repetitive peak isolation voltage,
566 VPK;
Maximum surge isolation voltage,
4000 VPK 		CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., for pollution degree 2, material group I: 370 VRMS 
 		 Single protection,
3000 VRMS 		Basic insulation, Altitude ≤ 5000 m, Tropical Climate,
400 VRMS maximum working voltage		 EN 61010-1:2010/A1:2019,
300 VRMS basic isolation
----------------
EN 60950-1:2006/A2:2013 and EN 62368-1:2014, 400 VRMS basic isolation
Certificate number: 40040142 Certificate planned File number: E181974 Certificate number: CQC18001199097 Client ID number: 77311

6.8 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DBQ-16 PACKAGE
IS Safety input, output, or supply current RθJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 201 mA
RθJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 308
RθJA = 67.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 403
RθJA = 67.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 1 586
PS Safety input, output, or total power RθJA = 67.9°C/W, TJ = 150°C, TA = 25°C, see Figure 2 1105 mW
TS Maximum safety temperature 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. 

The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
 

6.9 Electrical Characteristics: Driver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs are over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential-output voltage magnitude Open circuit voltage, unloaded bus,
4.5 V ≤ VCC2 ≤ 5.5 V		 1.5 4.3 VCC2 V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see Figure 19)		 1.5 2.5 V
RL = 100 Ω (see Figure 20), RS-422 load 2 2.9 V
RL = 54 Ω (see Figure 20), RS-485 load,
4.5 V < VCC2 < 5.5 V		 1.5 2.5 V
Δ|VOD| Change in differential output voltage between two states RL = 54 Ω or RL = 100 Ω, see Figure 20 –50 50 mV
VOC Common-mode output voltage RL = 54 Ω or RL = 100 Ω, see Figure 20 0.5 × VCC2 3 V
ΔVOC(SS) change in steady-state common-mode output voltage between two states RL = 54 Ω or RL = 100 Ω, see Figure 20 –50 50 mV
VOC(PP) Peak-to-peak common-mode output voltage RL = 54 Ω or RL = 100 Ω, see Figure 20 300 mV
IOS Short-circuit output current VD = VCC1 or VD = VGND1, VDE = VCC1,
–7 V ≤ VO ≤ 12 V, see Figure 28 		–175 175 mA
Ii Input current VD and VDE = 0 V or VD and VDE = VCC1 –10 10 µA
CMTI Common-mode transient immunity VD= VCC1 or GND1, VCM = 1200V, See Figure 22 85 100 kV/µs

6.10 Electrical Characteristics: Receiver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max are over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ii1 Bus input current VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, One bus input at –7 V or 12 V, other input at 0 V –100 100 µA
VTH+ Positive-going input threshold voltage –7 V ≤ Common mode voltage on bus terminals ≤ 12 V See (1) –100 –50 mV
VTH– Negative-going input threshold voltage –7 V ≤ Common mode voltage on bus terminals ≤ 12 V –200 –145 See (1) mV
Vhys Input hysteresis (VTH+ – VTH–) –7 V ≤ Common mode voltage on bus terminals ≤ 12 V 20 45 mV
VOH Output high voltage on the R pin VCC1=5V+/-10%, IOH = –4 mA, VID = 200 mV VCC1 – 0.4 V
VCC1=3.3V+/-10%, IOH = –2 mA, VID = 200 mV VCC1 – 0.3 V
VCC1=2.5V+/-10%, 1.8V+/-5%, IOH = –1 mA, VID = 200 mV VCC1 – 0.2 V
VOL Output low voltage on the R pin VCC1=5V+/-10%, IOL = 4 mA, VID = –200 mV 0.4 V
VCC1=3.3V+/-10%, IOL = 2 mA, VID = –200 mV 0.3 V
VCC1=2.5V+/-10%, 1.8V+/-5%, IOL = 1 mA, VID = –200 mV 0.2 V
IOZ Output high-impedance current on the R pin VR = 0 V or VR = VCC1, VRE = VCC1 –1 1 µA
Ii Input current on the RE pin VRE = 0 V or VRE = VCC1 –10 10 µA
CMTI Common-mode transient immunity VID = 1.5 V or -1.5 V, VCM= 1200 V , See Figure 22 85 100 kV/µs
(1) Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–.

6.11 Supply Current Characteristics: Side 1(ICC1)

 Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side supply current VD = VCC1, VCC1 = 5 V ± 10% 2.6 4.4 mA
Logic-side supply current VD = VCC1, VCC1 = 3.3 V ± 10% 2.6 4.4 mA
Logic-side supply current D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10% 3.2 5.1 mA
Logic-side supply current D = 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10% 3.2 5.1 mA
DRIVER ENABLED, RECEIVER ENABLED
Logic-side supply current VRE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% 2.6 4.4 mA
Logic-side supply current VRE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% 2.6 4.4 mA
Logic-side supply current VRE = VGND1, D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF 3.4 5.2 mA
Logic-side supply current VRE = VGND1, D= 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF 3.2 5.2 mA
DRIVER DISABLED, RECEIVER ENABLED
Logic-side supply current V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10% 1.5 3.1 mA
Logic-side supply current V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10% 1.5 3.1 mA
Logic-side supply current (A-B) =1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF 1.7 3.2 mA
Logic-side supply current (A-B) = 1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF 1.7 3.2 mA
DRIVER DISABLED, RECEIVER DISABLED
Logic-side supply current VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% 1.5 3.1 mA
Logic-side supply current VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% 1.5 3.1 mA
(1) CL(R) is the load capacitance on the R pin.

6.12 Supply Current Characteristics: Side 2(ICC2)

 VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER ENABLED, BUS UNLOADED
Bus-side supply current VD = VCC1, VCC2 = 5 V ± 10% 2.5 4.4 mA
DRIVER ENABLED, BUS LOADED
Bus-side supply current VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10% 52 70 mA
Bus-side supply current D =1Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10% 60 80 mA
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply current VD = VCC1, VCC2 = 5 V ± 10% 2.4 3.9 mA

6.13 Switching Characteristics: Driver

Typical specs are at VCC1=3.3V, VCC2=5V, TA=27℃ (Min/Max specs over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1Mbps DEVICE
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 21 210 300 ns
tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 21 210 300 ns
PWD Pulse width distortion(1), |tPHL – tPLH| RL = 54 Ω, CL = 50 pF, see Figure 21 3 30 ns
tPHZ, tPLZ Disable time See Figure 23, and Figure 24 160 250 ns
tPZH, tPZL Enable time See Figure 23, and Figure 24 200 400 ns
(1) Also known as pulse skew.

 
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