具有 ±1V 双极输入和 2.5V 基准电压输出的 AMC1035 Δ-Σ 调制器
- ZHCSIP8B August 2018 – April 2020 AMC1035
  
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具有 ±1V 双极输入和 2.5V 基准电压输出的 AMC1035 Δ-Σ 调制器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

针对电压和温度感应进行了优化的 Δ-Σ 调制器：
- ±1V 输入电压范围
- 高差分输入电阻：1.6GΩ（典型值）
- 集成 2.5V、±5mA 基准，可实现比例测量
出色的直流性能：
- 失调电压误差：±0.5mV（最大值）
- 温漂：±6µV/°C（最大值）
- 增益误差：±0.25%（最大值）
- 增益漂移：±45ppm/°C（最大值）
- 比例增益漂移：±15ppm/°C（最大值）
可选曼彻斯特编码式或未编码式位流输出
完整的额定工作温度范围：–40°C 至 +125°C

2 应用

工业应用中的交流电压和温度感应：

3 说明

AMC1035 是一款精密 Δ-Σ 调制器，可在 3.0V 至 5.5V 的单电源下运行，且具有 9MHz 至 21MHz 的时钟信号。在曼彻斯特模式下，额定时钟范围为 9MHz 至 11MHz。该器件的差分 ±1V 输入结构经过优化，可适应工业应用中的典型高噪声环境。
AMC1035 可选择曼彻斯特编码式输出位流，这样便无需考虑接收器件的设置和保留时间要求并减少总体电路布局工作。当用于与数字滤波器（例如集成到 TMS320F28004x、TMS320F2807x 或 TMS320F2837x 微控制器系列中）一起抽取输出位流时，该器件可在 82kSPS 的数据速率下实现具有 87dB 动态范围的 16 位分辨率。

AMC1035 的内部基准源支持比例电路架构，可最大限度降低电源电压变化和温漂对测量精度的负面影响。

AMC1035 还可用于与数字隔离器和隔离电源一起实现交流电力线电压检测。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
AMC1035	SOIC (8)	4.9mm x 3.9mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

应用示例

4 修订历史记录

Changes from A Revision (November 2018) to B Revision

Deleted PSRR specification for T_A > 85°C from Reference Output section of Electrical Characteristics tableGo
Changed SINAD equationGo

Changes from * Revision (August 2018) to A Revision

Changed 将文档状态从“预告信息”更改为“生产数据”Go

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	MCE	I	Manchester coding enabled, active high, with internal pulldown resistor (typical value: 200 kΩ). The polarity of this signal must not be changed when the clock signal is applied.
2	AINP	I	Noninverting analog input.
3	AINN	I	Inverting analog input.
4	REFOUT	O	Reference output: 2.5 V nominal, maximum ±5-mA sink and source capability.
5	GND	—	Ground reference.
6	DOUT	O	Modulator bitstream data output, updated with the rising edge of the clock signal present on CLKIN. This pin is a Manchester coded output if MCE is pulled high. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.
7	CLKIN	I	Modulator clock input: 9 MHz to 21 MHz with an internal pulldown resistor (typical value: 200 kΩ). The clock signal must be applied continuously for proper device operation; see the Clock Input section for additional details.
8	VDD	—	Power supply, 3.0 V to 5.5 V. See the Power Supply Recommendations section for decoupling recommendations.

6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, VDD to GND	–0.3	7	V
Analog input voltage at AINP, AINN	GND – 5	VDD + 0.5	V
Analog output voltage at REFOUT	GND – 0.5	VDD + 0.5	V
Digital input voltage at CLKIN or MCE	GND – 0.5	VDD + 0.5	V
Digital output voltage at DOUT	GND – 0.5	VDD + 0.5	V
Input current to any pin except supply pins	–10	10	mA
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
VDD	Supply voltage	VDD to GND	3.0	3.3	5.5	V
ANALOG INPUT
V_Clipping	Differential input voltage before clipping output	V_IN = V_AINP – V_AINN		±1.25		V
V_FSR	Specified linear differential full-scale voltage	V_IN = V_AINP – V_AINN	–1		1	V
	Absolute common-mode input voltage⁽¹⁾	(V_AINP + V_AINN) / 2 to GND	–2		VDD	V
V_CM	Operating common-mode input voltage⁽²⁾	(V_AINP + V_AINN) / 2 to GND, 3.0 V ≤ VDD < 4 V, V_AINP = V_AINN	–1.4		VDD – 1.4	V
		(V_AINP + V_AINN) / 2 to GND, 3.0 V ≤ VDD < 4.5 V, \|V_AINP – V_AINN\| = 1.25 V	–0.8		VDD – 2.4
		(V_AINP + V_AINN) / 2 to GND, 4 V ≤ VDD ≤ 5.5 V, V_AINP = V_AINN	–1.4		2.7
		(V_AINP + V_AINN) / 2 to GND, 4.5 V ≤ VDD ≤ 5.5 V, \|V_AINP – V_AINN\| = 1.25 V	–0.8		2.1
DIGITAL INPUT
	Input voltage	V_MCE or V_CLKIN to GND	GND		VDD	V
TEMPERATURE RANGE
T_A	Operating ambient temperature		–40	25	125	°C

(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage V_CM for normal operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) See the Analog Input section for more details.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		AMC1035	UNIT
		D (SOIC)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	120	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	52	°C/W
R_θJB	Junction-to-board thermal resistance	61	°C/W
ψ_JT	Junction-to-top characterization parameter	10	°C/W
ψ_JB	Junction-to-board characterization parameter	60	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

minimum and maximum specifications apply from T_A = –40°C to +125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN = GND, and sinc³ filter with OSR = 256 (unless otherwise noted); typical specifications are at T_A = 25°C, CLKIN = 20 MHz, and VDD = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_CMuv⁽¹⁾	Negative common-mode undervoltage detection level⁽²⁾	(V_AINP + V_AINN) / 2, V_AINP = V_AINN			–1.45	V
V_CMuv⁽¹⁾	Negative common-mode undervoltage detection level⁽²⁾	(V_AINP + V_AINN) / 2, \|V_AINP – V_AINN\| = 1.25 V			–0.85	V
V_CMov⁽¹⁾	Positive common-mode overvoltage detection level⁽²⁾	3.0 V ≤ VDD < 4 V, V_AINP = V_AINN		VDD – 1.35		V
		3.0 V ≤ VDD < 4.5 V, \|V_AINP – V_AINN\| = 1.25 V		VDD – 2.35
		4 V ≤ VDD ≤ 5.5 V, V_AINP = V_AINN	2.75
		4.5 V ≤ VDD ≤ 5.5 V, \|V_AINP – V_AINN\| = 1.25 V	2.15
R_IN	Single-ended input resistance	AINN = GND	0.1	0.4		GΩ
R_IND	Differential input resistance		0.16	1.6		GΩ
C_IN	Single-ended input capacitance	AINN = GND		2		pF
C_IND	Differential input capacitance			2		pF
I_IB	Input bias current	AINP = AINN = GND, (I_AINP + I_AINN) / 2	–10	±3	10	nA
TCI_IB	Input bias current thermal drift	AINP = AINN = GND, (I_AINP + I_AINN) / 2		±5		pA/°C
I_IO	Input offset current	I_IO = I_AINP – I_AINN	–5	±1	5	nA
CMRR	Common-mode rejection ratio	AINP = AINN, f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–104		dB
CMRR	Common-mode rejection ratio	AINP = AINN, f_IN from 0.1 Hz to 50 kHz, –0.5 V ≤ V_IN ≤ 0.5 V		–88		dB
DC ACCURACY
	Resolution⁽³⁾		16			Bits
INL	Integral nonlinearity⁽⁴⁾	Resolution: 16 bits	–12	±2	12	LSB
E_O	Offset error	Initial, at T_A = 25°C, AINP = AINN = GND	–0.5	±0.03	0.5	mV
TCE_O	Offset error thermal drift⁽⁵⁾		–6	±0.1	6	µV/°C
E_G	Gain error	Initial, at T_A = 25°C	–0.25%	±0.02%	0.25%
E_G	Gain error	Initial, at T_A = 25°C, ratiometric mode	–0.3%	±0.02%	0.3%
TCE_G	Gain error thermal drift⁽⁶⁾		–45	±20	45	ppm/°C
TCE_G	Gain error thermal drift⁽⁶⁾	Ratiometric mode	–15	±4	15	ppm/°C
PSRR	Power-supply rejection ratio	AINP = AINN = GND, at dc		–90		dB
PSRR	Power-supply rejection ratio	AINP = AINN = GND, 10 kHz, 100-mV ripple		–84		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	81	87		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	77	83		dB
THD	Total harmonic distortion	f_IN = 1 kHz		–87	–78	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	78	87		dB
REFERENCE OUTPUT
V_REFOUT	Reference output voltage	Initial, at T_A = 25°C, no load	2.495	2.5	2.505	V
TCV_REFOUT	Reference output voltage drift		–50	±20	50	ppm/°C
I_REFOUT	Reference output current	C_LOAD < 1 nF⁽⁷⁾	–5		5	mA
	Load regulation	Load to GND or VDD		0.15	0.35	mV/mA
I_SC	Short-circuit current	REFOUT to GND		23		mA
I_SC	Short-circuit current	REFOUT to VDD		–21		mA
PSRR	Power-supply rejection ratio		–200	±30	200	µV/V
DIGITAL INPUTS (CMOS Logic With Schmitt-Trigger)
I_IN	Input current	GND ≤ V_IN ≤ VDD			35	μA
C_IN	Input capacitance			3		pF
V_IH	High-level input voltage		0.7 × VDD		VDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × VDD	V
DIGITAL OUTPUT: CMOS
C_LOAD	Output load capacitance	f_CLKIN = 21 MHz		15	30	pF
V_OH	High-level output voltage	I_OH = –20 µA	VDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	VDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
POWER SUPPLY
I_VDD	High-side supply current	3.0 V ≤ VDD ≤ 3.6 V, I_REFOUT = 0 mA, MCE = 0, C_LOAD = 15 pF		5.2	6.8	mA
		3.0 V ≤ VDD ≤ 3.6 V, I_REFOUT = 0 mA, MCE = 1, C_LOAD = 15 pF⁽⁸⁾		4.6	6.1
		4.5 V ≤ VDD ≤ 5.5 V, I_REFOUT = 0 mA, MCE = 0, C_LOAD = 15 pF		6.4	8.3
		4.5 V ≤ VDD ≤ 5.5 V, I_REFOUT = 0 mA, MCE = 1, C_LOAD = 15 pF⁽⁸⁾		5.4	7.2

(1) See the Analog Input section for more details.

(2) The common-mode overvoltage detection level has a typical hysteresis of 35 mV.

(3) The filter output is truncated to 16 bits. 16 bits of no missing codes is specified by design.

(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(5) Offset error drift is calculated using the box method, as described by the following equation: AMC1035 ec_eodrift_bas654.gif

(6) Gain error drift is calculated using the box method, as described by the following equation: AMC1035 ec_egdrift_bas654.gif

(7) Capacitive load with a value ≥ 1nF requires series resistor to be connected to the REFOUT pin. See the Reference Output section for more details.

(8) Typical value is specified at f_CLKIN = 10 MHz, maximum value is specified at f_CLKIN = 11 MHz.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_CLKIN	CLKIN clock frequency	MCE = 0	9	20	21	MHz
f_CLKIN	CLKIN clock frequency	MCE = 1	9	10	11	MHz
Duty_Cycle	CLKIN clock duty cycle⁽¹⁾		40%	50%	60%
t_H1	DOUT hold time after rising edge of CLKIN	MCE = 0, C_LOAD = 15 pF	6			ns
t_H2	DOUT hold time after rising edge of CLKIN	MCE = 1, C_LOAD = 15 pF	6		23	ns
t_H3	DOUT hold time after falling edge of CLKIN	MCE = 1, C_LOAD = 15 pF	10		26	ns
t_D1	Rising edge of CLKIN to DOUT valid delay	MCE = 0, C_LOAD = 15 pF			25	ns
t_D2	Rising edge of CLKIN to DOUT valid delay	MCE = 1, C_LOAD = 15 pF	11		27	ns
t_D3	Falling edge of CLKIN to DOUT valid delay	MCE = 1, C_LOAD = 15 pF	15		30	ns
t_r	DOUT rise time	10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, C_LOAD = 15 pF		2.5	5	ns
t_r	DOUT rise time	10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, C_LOAD = 15 pF		1.5	3.5	ns
t_f	DOUT fall time	90% to 10%, 3.0 V ≤ VDD ≤ 3.6 V, C_LOAD = 15 pF		2.5	5.8	ns
t_f	DOUT fall time	90% to 10%, 4.5 V ≤ VDD ≤ 5.5 V, C_LOAD = 15 pF		1.8	4.4	ns
t_ASTART	Analog startup time	VDD step to 3.0 V, 0.1% settling, CLKIN applied		0.25		ms

(1) The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.

Figure 1. Digital Interface Timing

Figure 2. Device Startup Timing

6.7 Typical Characteristics

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN = 20 MHz, MCE = 0, and sinc³ filter with OSR = 256 (unless otherwise noted)

VDD = 5.5 V

Figure 3. Input Bias Current vs
Common-Mode Input Voltage

Figure 5. Integral Nonlinearity vs Input Voltage

Figure 7. Offset Error vs Supply Voltage

Figure 9. Offset Error vs Clock Frequency

Figure 11. Gain Error vs Temperature

Figure 13. Gain Error vs Clock Frequency

Figure 15. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Supply Voltage

Figure 17. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Clock Frequency

Figure 19. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Amplitude

Figure 21. Total Harmonic Distortion vs Temperature

Figure 23. Total Harmonic Distortion vs
Input Signal Frequency

Figure 25. Spurious-Free Dynamic Range vs Supply Voltage

Figure 27. Spurious-Free Dynamic Range vs
Clock Frequency

Figure 29. Spurious-Free Dynamic Range vs
Input Signal Amplitude

4096-point FFT, V_IN = 2 V_PP

Figure 31. Frequency Spectrum With 5-kHz Input Signal

Figure 33. Reference Output Voltage vs Temperature

Figure 35. Supply Current vs Temperature

Figure 4. Common-Mode Rejection Ratio vs
Input Signal Frequency

Figure 6. Integral Nonlinearity vs Temperature

Figure 8. Offset Error vs Temperature

Figure 10. Gain Error vs Supply Voltage

Figure 12. Ratiometric Gain Error vs Temperature

Figure 14. Power-Supply Rejection Ratio vs
Ripple Frequency

Figure 16. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Temperature

Figure 18. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Frequency

Figure 20. Total Harmonic Distortion vs Supply Voltage

Figure 22. Total Harmonic Distortion vs Clock Frequency

Figure 24. Total Harmonic Distortion vs
Input Signal Amplitude

Figure 26. Spurious-Free Dynamic Range vs Temperature

Figure 28. Spurious-Free Dynamic Range vs
Input Signal Frequency

4096-point FFT, V_IN = 2 V_PP

Figure 30. Frequency Spectrum With 1-kHz Input Signal

Figure 32. Reference Output Voltage vs Supply Voltage

Figure 34. Supply Current vs Supply Voltage

Figure 36. Supply Current vs Clock Frequency

7 Detailed Description

7.1 Overview

The differential analog input (comprised of input signals AINP and AINN) of the AMC1035 is a chopper-stabilized buffer, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 9 MHz to 21 MHz. The time average of this serial bitstream output is proportional to the analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1035. The 1.6-GΩ differential input resistance of the analog input stage supports low gain-error signal sensing in high-voltage applications using resistive dividers. The external clock input simplifies the synchronization of multiple measurement channels on the system level. The extended frequency range of up to 21 MHz supports higher performance levels compared to the other solutions available on the market.