TPS563249 是一款采用 SOT-23 封装的简单易用型 3A 同步降压转换器。
该器件经过优化,最大限度地减少了运行所需的外部组件并可实现低待机电流。
此开关稳压器采用 D-CAP3 模式控制,能够提供快速瞬态响应,并且在无需外部补偿组件的情况下支持诸如高分子聚合物等低等效串联电阻 (ESR) 输出电容以及超低 ESR 陶瓷电容器。
TPS563249 采用强制连续导通模式 (FCCM) 运行,在轻载工作期间保持固定的 1.4MHz 开关频率,并可消除系统干扰。TPS563249 采用 6 引脚 1.6mm × 2.9mm SOT (DDC) 封装,额定结温范围为 –40°C 至 125°C。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPS563249 | SOT-23-THIN (6) | 1.60mm x 2.90mm |
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日期 | 修订版本 | 说明 |
---|---|---|
2018 年 12 月 | * | 初始发行版。 |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 5 | I | Enable input control. Active high and must be pulled up to enable the device. |
GND | 1 | — | Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive VFB to this GND at a single point. |
SW | 2 | O | Switch node connection between high-side NFET and low-side NFET. |
VBST | 6 | O | Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins. |
VFB | 4 | I | Converter feedback input. Connect to output voltage with feedback resistor divider. |
VIN | 3 | I | Input voltage supply pin. The drain terminal of high-side power NFET. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN | –0.3 | 19 | V |
VBST | –0.3 | 24.5 | V | |
VBST (10 ns transient) | –0.3 | 26.5 | V | |
VBST (vs SW) | –0.3 | 5.5 | V | |
VFB | –0.3 | 5.5 | V | |
SW | –2 | 19 | V | |
SW (10 ns transient) | –3.5 | 21 | V | |
EN | -0.3 | VIN + 0.3 | V | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Supply input voltage range | 4.5 | 17 | V | ||
EN | EN Input voltage range | –0.1 | VIN | V | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS563249 | UNIT | |
---|---|---|---|
DDC (SOT) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 117.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 57.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 31.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 11.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 31.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CURRENT | |||||||
IVIN(SDN) | Shutdown supply current | VIN current, EN = 0 V, TJ = 25°C | 2.5 | 10 | µA | ||
LOGIC THRESHOLD | |||||||
VENH | Enable threshold | Rising | 1.27 | 1.34 | V | ||
VENL | Enable threshold | Falling | 1.08 | 1.15 | V | ||
REN | EN pin resistance to GND | VEN = 1 V | 800 | 1000 | 1200 | kΩ | |
VFB VOLTAGE AND DISCHARGE RESISTANCE | |||||||
VFB | FB voltage | TJ = 25°C | 594 | 600 | 606 | mV | |
588 | 600 | 612 | mV | ||||
IFB | FB input current | VFB = 0.7 V | 0 | ±50 | nA | ||
MOSFET | |||||||
RDS(on)h | High-side switch resistance | TJ = 25°C | 70 | mΩ | |||
RDS(on)l | Low-side switch resistance | TJ = 25°C | 30 | mΩ | |||
CURRENT LIMIT | |||||||
Iocl_h_source | High side FET source Current limit | 5.5 | 6.3 | 7.1 | A | ||
Iocl_l_source | Low side FET source Current limit | 3.1 | 3.9 | 4.7 | A | ||
Iocl_l_sink | Low side FET sink Current limit | 1.1 | 1.7 | A | |||
THERMAL SHUTDOWN | |||||||
TSDN | Thermal shutdown threshold(1) | Shutdown temperature | 160 | °C | |||
Hysteresis | 25 | ||||||
ON-TIME TIMER CONTROL | |||||||
tON(MIN) | Minimum on time(1) | VIN = 12 V, load = 3 A | 50 | ns | |||
tOFF(MIN) | Minimum off time | 250 | ns | ||||
SOFT START | |||||||
tss | Soft-start time | Internal soft-start time | 1.7 | ms | |||
FREQUENCY | |||||||
Fsw | Switching frequency | 1250 | 1400 | 1550 | kHz | ||
OUTPUT UNDERVOLTAGE PROTECTION | |||||||
VUVP | Output UVP threshold | Hiccup detect (H > L) | 65% | ||||
tUVPDLY | UVP propagation delay | 0.36 | ms | ||||
tHIC | UVP protection Hiccup Time before restart | 25 | ms | ||||
UVLO | |||||||
UVLO | UVLO threshold | Wake up VIN voltage | 4.2 | 4.4 | V | ||
Shutdown VIN voltage | 3.6 | 3.8 | |||||
Hysteresis VIN voltage | 0.4 |
0.9 V Efficiency | L = 0.56 µH | (Wurth:744383560056) |
1.2 V Efficiency | L = 0.68 µH | (Wurth:744383560068) |
1.8 V Efficiency | L = 1 µH | (Wurth:744311100) |
3.3 V Efficiency | L = 1.5 µH | (Wurth:744311150) |
1.05 V Efficiency | L = 0.56 µH | (Wurth:744383560056) |
1.5 V Efficiency | L = 0.68 µH | (Wurth:744383560068) |
2.5 V Efficiency | L = 1 µH | (Wurth:744311100) |
5 V Efficiency | L = 1.5 µH | (Wurth:744311150) |
The TPS563249 is a 3-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output capacitance required to meet a specific level of performance.
The main control loop of the TPS563249 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.
The TPS563249 has an internal 1.7-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point.