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  • TPS563249 17V、3A、恒定 1.4MHz 同步降压稳压器

    • ZHCSI44A April   2018  – December 2018 TPS563249

      PRODUCTION DATA.  

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  • TPS563249 17V、3A、恒定 1.4MHz 同步降压稳压器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      TPS563249 效率
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Soft Start and Pre-Biased Soft Start
      3. 7.3.3 Current Protection
      4. 7.3.4 Undervoltage Lockout (UVLO) Protection
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 Dropout
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS563249 17V、3A、恒定 1.4MHz 同步降压稳压器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 在 3A 转换器集成了 70mΩ 和 30mΩ FET
  • D-CAP3™模式控制，用于快速瞬态响应
  • 输入电压范围：4.5V 至 17V
  • 输出电压范围：0.6V 至 7V
  • 强制连续导通模式
  • 恒定 1.4MHz 开关频率
  • 低关断电流（低于 10µA）
  • 1% 反馈电压精度 (25°C)
  • 从预偏置输出电压中启动
  • 逐周期过流限制
  • 断续模式过流保护
  • 非锁存欠压保护 (UVP) 和热关断 (TSD) 保护
  • 固定软启动时间：1.7ms

2 应用

  • 宽带调制解调器
  • 接入点网络
  • 无线路由器
  • 安全监控
  • 电视、机顶盒

3 说明

TPS563249 是一款采用 SOT-23 封装的简单易用型 3A 同步降压转换器。

该器件经过优化，最大限度地减少了运行所需的外部组件并可实现低待机电流。

此开关稳压器采用 D-CAP3 模式控制，能够提供快速瞬态响应，并且在无需外部补偿组件的情况下支持诸如高分子聚合物等低等效串联电阻 (ESR) 输出电容以及超低 ESR 陶瓷电容器。

TPS563249 采用强制连续导通模式 (FCCM) 运行，在轻载工作期间保持固定的 1.4MHz 开关频率，并可消除系统干扰。TPS563249 采用 6 引脚 1.6mm × 2.9mm SOT (DDC) 封装，额定结温范围为 –40°C 至 125°C。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS563249 SOT-23-THIN (6) 1.60mm x 2.90mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

空白

空白

简化原理图

TPS563249 Simplified_Schem_FP_SLVSE54.gif

TPS563249 效率

TPS563249 1st_Page_Eff_SLVSE54_2p0.gif

4 修订历史记录

日期 修订版本 说明
2018 年 12 月 * 初始发行版。

5 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 5 I Enable input control. Active high and must be pulled up to enable the device.
GND 1 — Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive VFB to this GND at a single point.
SW 2 O Switch node connection between high-side NFET and low-side NFET.
VBST 6 O Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.
VFB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider.
VIN 3 I Input voltage supply pin. The drain terminal of high-side power NFET.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 19 V
VBST –0.3 24.5 V
VBST (10 ns transient) –0.3 26.5 V
VBST (vs SW) –0.3 5.5 V
VFB –0.3 5.5 V
SW –2 19 V
SW (10 ns transient) –3.5 21 V
EN -0.3 VIN + 0.3 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply input voltage range 4.5 17 V
EN EN Input voltage range –0.1 VIN V
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS563249 UNIT
DDC (SOT)
6 PINS
RθJA Junction-to-ambient thermal resistance 117.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.3 °C/W
RθJB Junction-to-board thermal resistance 31.2 °C/W
ψJT Junction-to-top characterization parameter 11.2 °C/W
ψJB Junction-to-board characterization parameter 31.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN(SDN) Shutdown supply current VIN current, EN = 0 V, TJ = 25°C 2.5 10 µA
LOGIC THRESHOLD
VENH Enable threshold Rising 1.27 1.34 V
VENL Enable threshold Falling 1.08 1.15 V
REN EN pin resistance to GND VEN = 1 V 800 1000 1200 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB FB voltage TJ = 25°C 594 600 606 mV
588 600 612 mV
IFB FB input current VFB = 0.7 V 0 ±50 nA
MOSFET
RDS(on)h High-side switch resistance TJ = 25°C 70 mΩ
RDS(on)l Low-side switch resistance TJ = 25°C 30 mΩ
CURRENT LIMIT
Iocl_h_source High side FET source Current limit 5.5 6.3 7.1 A
Iocl_l_source Low side FET source Current limit 3.1 3.9 4.7 A
Iocl_l_sink Low side FET sink Current limit 1.1 1.7 A
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 160 °C
Hysteresis 25
ON-TIME TIMER CONTROL
tON(MIN) Minimum on time(1) VIN = 12 V, load = 3 A 50 ns
tOFF(MIN) Minimum off time 250 ns
SOFT START
tss Soft-start time Internal soft-start time 1.7 ms
FREQUENCY
Fsw Switching frequency 1250 1400 1550 kHz
OUTPUT UNDERVOLTAGE PROTECTION
VUVP Output UVP threshold Hiccup detect (H > L) 65%
tUVPDLY UVP propagation delay 0.36 ms
tHIC UVP protection Hiccup Time before restart 25 ms
UVLO
UVLO UVLO threshold Wake up VIN voltage 4.2 4.4 V
Shutdown VIN voltage 3.6 3.8
Hysteresis VIN voltage 0.4
(1) Not production tested.

6.6 Typical Characteristics

VIN = 12 V (unless otherwise noted)
TPS563249 Ishutdown_SLVSE54.gif
Figure 1. Shutdown Current vs Junction Temperature
TPS563249 EN_Rising_SLVSE54.gif
Figure 3. EN Rising threshold vs Junction Temperature
TPS563249 HighSideRdson_SLVSE54.gif
Figure 5. High-Side Rds(On) vs Junction Temperature
TPS563249 Dropout_3.3V_SLVSE54_2p0.gif
Figure 7. Dropout for 3.3 V Output Voltage
TPS563249 Eff of 0.9Vout_2p0.gif
0.9 V Efficiency L = 0.56 µH (Wurth:744383560056)
Figure 9. Efficiency vs Output Current, VOUT = 0.9 V
TPS563249 Eff of 1.2Vout_2p0.gif
1.2 V Efficiency L = 0.68 µH (Wurth:744383560068)
Figure 11. Efficiency vs Output Current, VOUT = 1.2 V
TPS563249 Eff of 1.8Vout_2p0.gif
1.8 V Efficiency L = 1 µH (Wurth:744311100)
Figure 13. Efficiency vs Output Current, VOUT = 1.8 V
TPS563249 Eff of 3.3Vout_2p0.gif
3.3 V Efficiency L = 1.5 µH (Wurth:744311150)
Figure 15. Efficiency vs Output Current, VOUT= 3.3 V
TPS563249 FB_Voltage_SLVSE54.gif
Figure 2. VFB Voltage vs Junction Temperature
TPS563249 EN_Falling_SLVSE54.gif
Figure 4. EN Falling threshold vs Junction Temperature
TPS563249 LowSideRdson_SLVSE54.gif
Figure 6. Low-Side Rds(On) vs Junction Temperature
TPS563249 Dropout_5V_SLVSE54_2p0.gif
Figure 8. Dropout for 5 V Output Voltage
TPS563249 Eff of 1.05Vout_2p0.gif
1.05 V Efficiency L = 0.56 µH (Wurth:744383560056)
Figure 10. Efficiency vs Output Current, VOUT = 1.05 V
TPS563249 Eff of 1.5Vout_2p0.gif
A.
1.5 V Efficiency L = 0.68 µH (Wurth:744383560068)
Figure 12. Efficiency vs Output Current, VOUT = 1.5 V
TPS563249 Eff of 2.5Vout_2p0.gif
A.
2.5 V Efficiency L = 1 µH (Wurth:744311100)
Figure 14. Efficiency vs Output Current, VOUT= 2.5 V
TPS563249 Eff of 5Vout_2p0.gif
5 V Efficiency L = 1.5 µH (Wurth:744311150)
Figure 16. Efficiency vs Output Current, VOUT = 5 V

7 Detailed Description

7.1 Overview

The TPS563249 is a 3-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output capacitance required to meet a specific level of performance.

7.2 Functional Block Diagram

TPS563249 FBD_new_SLVSE54.gif

7.3 Feature Description

7.3.1 Adaptive On-Time Control and PWM Operation

The main control loop of the TPS563249 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.

7.3.2 Soft Start and Pre-Biased Soft Start

The TPS563249 has an internal 1.7-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converters ramp up smoothly into regulation point.

 
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