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  • TPS65023x 电源管理 IC (PMIC)，具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS

    • ZHCSI15L June   2006  – May 2018 TPS65023 , TPS65023B

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  • TPS65023x 电源管理 IC (PMIC)，具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 6.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 6.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 6.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 6.11 I2C Timing Requirements for TPS65023B
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power-Good Monitoring
      9. 7.3.9  Low-Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Reset + Control Signals
        1. 7.5.1.1 DEFLDO1 and DEFLDO2
        2. 7.5.1.2 Interrupt Management and the INT Pin
      2. 7.5.2 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (Read Only)
      2. 7.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
      3. 8.1.3 Reset Condition of DCDC1
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for Supply Voltages Below 3.0 V
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS65023x 电源管理 IC (PMIC)，具有 3 个直流/直流转换器、3 个 LDO、I2C 接口和 DVS

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 适用于处理器内核的 90% 效率的 1.7A 降压转换器 (VDCDC1)
  • 用于系统电压的 95% 效率的 1.2A 降压转换器 (VDCDC2)
  • 用于存储器电压的 92% 效率的 1.0A 降压转换器 (VDCDC3)
  • 用于支持实时时钟 (VRTC) 的 30mA LDO 和开关
  • 2 个 200mA 通用 LDO
  • 用于处理器内核的动态电压管理
  • 可使用两个数字输入引脚进行 LDO 电压预选
  • 外部可调复位延迟时间
  • 电池备用功能
  • 用于电感转换器的单独使能引脚
  • 兼容 I2C 的串行接口
  • 在特性列表中增加了兼容 I2C™设置和保持计时：
    • TPS65023：300ns
    • TPS65023B：100ns
  • 85μA 静态电流
  • 低波纹 PFM 模式
  • 热关断保护
  • 40 引脚 5mm × 5mm WQFN 封装

2 应用

  • 数字媒体播放器
  • 互联网音频播放器
  • 数码相机
  • 智能手机
  • 电源 DaVinci™DSP 系列解决方案

3 说明

TPS65023x 器件 是一种集成式电源管理 IC，适用于 由一节
锂离子或锂离子聚合物电池供电并需要多个电源轨的应用。TPS65023x 器件具有三个高效的降压转换器，用于在基于处理器的系统中提供内核电压、外设、I/O 以及存储器电源轨。内核转换器可通过串行接口实现动态电压变化，从而使系统实现动态节能。这三个降压转换器会在轻负载时进入低功耗模式，从而在可能的最宽负载电流范围内实现最高效率。

TPS65023x 还集成了两个可通过外部输入引脚启用的通用 200mA LDO 稳压器。每个 LDO 可在 1.5V 至 6.5V 输入电压范围内正常运行，从而使得它们可以由其中一个降压转换器供电，也可以由电池直接供电。用户可使用 DEFLDO1 和 DEFLDO2 引脚通过数字方式将这两个 LDO 的默认输出电压设置为四个不同的电压组合。串行接口可用于动态电压调节和屏蔽中断，或用于停用、启用和设置 LDO 输出电压。该接口符合快速模式和标准模式 I2C 规格，可实现高达 400kHz 的传输频率。TPS65023x 采用 40 引脚 WQFN 封装，并在 –40°C 至 85°C 的自然通风温度范围内运行。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS65023 WQFN (40) 5.00mm × 5.00mm
TPS65023B
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

简化原理图

TPS65023 TPS65023B Keygraphic.gif

4 修订历史记录

Changes from K Revision (December 2015) to L Revision

  • Changed 更改了数据表的标题Go
  • Replaced references of TI PowerPAD IC package with thermal pad Go
  • Added 增加了器件支持 和文档支持 部分Go
  • Changed 静电放电注意事项 声明Go

Changes from J Revision (September 2011) to K Revision

  • Added 添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from I Revision (July 2010) to J Revision

  • Added Thermal Information Table and deleted Dissipation Ratings TableGo

Changes from H Revision (December 2009) to I Revision

  • Added I2C 的 串行 接口Go
  • Added TPS65023B 器件规格Go
  • 添加了 TPS65023B 器件的订购信息。Go
  • Added specs for TPS65023B deviceGo
  • Changed "VBACKUP threshold" test condition typographical error from "VBACKUP falling" to "VBACKUP rising"Go
  • Added specs for TPS65023B deviceGo
  • Added Differences table for TPS65023 and TPS65023B devicesGo

Changes from G Revision (October 2008) to H Revision

  • Changed IO(DCDC1) MAX from: 1500 mA to: 1700 mAGo
  • Added High level input voltage for the SDAT pinGo
  • Changed IO from:1500 mA MIN to 1700 mA Go
  • Changed IO maximum from:1.5 A to: 1.7 A for VDCDC1 fixed and adjustable output voltage test condition specs.Go
  • Changed IO maximum from: 1500 mA to: 1700 mA for VDCDC1 Load Regulation test conditionGo
  • Changed VDCDC1 "soft-start ramp time" spec to: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC2 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC3 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed FBD graphic to show 1700 mA for DCDC1 Buck ConverterGo
  • Changed text string from: "1.2 V or 1.8 V" to: "1.2 V to 1.6 V" in the STEP-DOWN CONVERTERS.,VDCDC1.... description.Go
  • Changed graphic entity to the one used in the Application Note SLVA273Go

Changes from F Revision (July 2007) to G Revision

  • Changed the Interrupt Management and the INT Pin section.Go

Changes from E Revision (January 2007) to F Revision

  • Changed text string from: "If it is tied to VCC, the default is 2.5 V" To: "If it is tied to VCC, the default is 3.3 V"Go

Changes from D Revision (December 2006) to E Revision

  • Changed LDO1 output voltage range from: 3.3 to: 3.3Go
  • Changed text string from: "VDCDC2 converter defaults to 1.8 V or 2.5 V" to: "VDCDC2 converter defaults to 1.8 V or 3.3 V"Go

Changes from C Revision (October 2006) to D Revision

  • Changed Typical Configuration for Ti DaVinci ProcessorsGo

Changes from B Revision (June 2006) to C Revision

  • Changed from: AD Coupled to: AD Coupled - Figure 16Go
  • Changed from: AD Coupled to: AD Coupled - Figure 17Go

Changes from A Revision (June 2006) to B Revision

  • Changed 从 97% 效率的 1.5A 降压转换器更改为 90% 效率的 1.7A 降压转换器Go
  • Changed 从 6mm × 6mm QFN 封装更改为 5mm × 5mm QFN 封装Go
  • Changed 从 RHA 封装更改为 RSB 封装Go
  • Changed from:O(DCDC2) to: IO(DCDC1)Go
  • Changed Forward current limit - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Added VINDCDC3 = 3.6 V to Maximum output currentGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Figure 3 (DVS Timing)Go
  • Changed Figure 11 (Graph - DCDC2: OUTPUT VOLTAGE)Go
  • Added Figure 12 (Graph - DCDC3: OUTPUT VOLTAGE )Go
  • Changed Figure 20 (Graph - VDCDC2 OUTPUT VOLTAGE RIPPLE)Go
  • Added Reset Condition of DCDC1 InformationGo
  • Changed Typical Configuration for Ti DaVinci ProcessorsGo
  • Changed from: TPS65023 typically use a 3.3 μH output inductor to: TPS65023 typically use a 2.2 μH output inductorGo
  • Changed from: VDCDC3 to: VDCDC1Go
  • Changed from: VDEFDCDC3 to: DEFDCDC1Go
  • Changed from: 2.5 V to 3.3 V (Table 20)Go

Changes from * Revision (May 2006) to A Revision

  • Changed Electrical Characteristics: VDCDC1 Step-Down ConverterGo
  • Changed Electrical Characteristics: VDCDC3 Step-Down Converter Go
  • Changed CON_CTRL Register Address - Column B0 default value changed from 1 to 0.Go
  • Changed VDCDC# to VDCDC1Go

5 Pin Configuration and Functions

RSB Package
40-Pin WQFN
Top View
TPS65023 TPS65023B pin_out_lvs613.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND1 40 — Analog ground. All analog ground pins are connected internally on the chip.
AGND2 17 — Analog ground. All analog ground pins are connected internally on the chip.
DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2 32 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3 1 I Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V.
L1 7 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 35 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3 4 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1 8 — Power ground for VDCDC1 converter
PGND2 34 — Power ground for VDCDC2 converter
PGND3 3 — Power ground for VDCDC3 converter
VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block.
VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VINDCDC1 6 I Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC.
VINDCDC2 36 I Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC.
VINDCDC3 5 I Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC.
Thermal Pad — — Connect the power pad to analog ground
LDO REGULATOR SECTION
DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
LDO_EN 22 I Enable input for LDO1 and LDO2. A logic high enables the LDOs and a logic low disables the LDOs.
VBACKUP 15 I Connect the backup battery to this input pin
VINLDO 19 I Input voltage for LDO1 and LDO2
VLDO1 20 O Output voltage of LDO1
VLDO2 18 O Output voltage of LDO2
VRTC 16 O Output voltage of the LDO and switch for the real time clock
VSYSIN 14 I Input of system voltage for VRTC switch
CONTROL AND I2C SECTION
HOT_RESET 11 I Push button input that reboots or wakes up the processor through the RESPWRON output pin.
INT 28 O Open-drain output
LOW_BAT 21 O Open-drain output of LOW_BAT comparator
LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output.
PWRFAIL 31 O Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output
RESPWRON 27 O Open-drain system reset output
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data and address
TRESPWRON 26 I Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage on all pins except AGND and PGND pins with respect to AGND –0.3 7 V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA
Peak current at all other pins 1000 mA
Continuous total power dissipation See Thermal Information
TA Operating free-air temperature –40 85 °C
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Input voltage step-down converters
(VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail		 2.5 6 V
VO Output voltage for VDCDC1 step-down converter(1) 0.6 VINDCDC1 V
Output voltage for VDCDC2 step-down converter(1) 0.6 VINDCDC2
Output voltage for VDCDC3 step-down converter(1) 0.6 VINDCDC3
VI Input voltage for LDOs (VINLDO1, VINLDO2) 1.5 6.5 V
VO Output voltage for LDOs (VLDO1, VLDO2) 1 VINLDO1–2 V
IO(DCDC1) Output current at L1 1700 mA
Inductor at L1(2) 1.5 2.2 μH
CI(DCDC1) Input capacitor at VINDCDC1 (2) 10 μF
CO(DCDC1) Output capacitor at VDCDC1 (2) 10 22 μF
IO(DCDC2) Output current at L2 1200 mA
Inductor at L2 (2) 1.5 2.2 μH
CI(DCDC2) Input capacitor at VINDCDC2 (2) 10 μF
CO(DCDC2) Output capacitor at VDCDC2 (2) 10 22 μF
IO(DCDC3) Output current at L3 1000 mA
Inductor at L3 (2) 1.5 2.2 μH
CI(DCDC3) Input capacitor at VINDCDC3(2) 10 μF
CO(DCDC3) Output capacitor at VDCDC3 (2) 10 22 μF
CI(VCC) Input capacitor at VCC (2) 1 μF
Ci(VINLDO) Input capacitor at VINLDO (2) 1 μF
CO(VLDO1-2) Output capacitor at VLDO1, VLDO2 (2) 2.2 μF
IO(VLDO1-2) Output current at VLDO1, VLDO2 200 mA
CO(VRTC) Output capacitor at VRTC (2) 4.7 μF
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(3) 1 10 Ω
(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, and DEFDCDC1
(2) See Application Information section for more information.
(3) Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly.

6.4 Thermal Information

THERMAL METRIC(1) TPS65023x UNIT
RSB (WQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 32.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.3 °C/W
RθJB Junction-to-board thermal resistance 13.6 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 5.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023
VIH High level input voltage (except the SDAT pin) Resistor pullup at SCLK = 4.7 kΩ, pulled to VRTC 1.3 VCC V
VIH High level input voltage for the SDAT pin Resistor pullup at SDAT = 4.7 kΩ, pulled to VRTC 1.45 VCC V
VIL Low level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.4 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023B
VIH High level input voltage for the SCLK pin Rpullup at SCLK = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V		 1.4 VCC V
VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V		 1.69 VCC V
VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 4.5 V		 1.55 VCC V
VIL Low level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.35 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS: HOT_RESET, DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH High-level input voltage 1.3 VCC V
VIL Low-level input voltage 0 0.4 V
IIB Input bias current 0.01 0.1 μA
tdeglitch Deglitch time at HOT_RESET 25 30 35 ms
CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT)
VOH High-level output voltage 6 V
VOL Low-level output voltage IIL = 5 mA 0 0.3 V
Duration of low pulse at RESPWRON External capacitor 1 nF 100 ms
ICONST Internal charge / discharge current on pin TRESPWRON Used for generating RESPWRON delay 1.7 2 2.3 μA
TRESPWRON_LOWTH Internal lower comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.225 0.25 0.275 V
TRESPWRON_UPTH Internal upper comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.97 1 1.103 V
Resetpwron threshold VRTC falling –3% 2.4 3% V
Resetpwron threshold VRTC rising –3% 2.52 3% V
ILK Leakage current Output inactive high 0.1 μA
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
VI Input voltage range for LDO1, 2 1.5 6.5 V
VO(LD01) LDO1 output voltage range 1 3.15 V
VO(LDO2) LDO2 output voltage range 1 3.3 V
IO Maximum output current for LDO1, LDO2 VI = 1.8 V, VO = 1.3 V 200 mA
VI = 1.5 V, VO = 1.3 V 120
I(SC) LDO1 and LDO2 short-circuit current limit V(LDO1) = GND, V(LDO2) = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV
IO = 50 mA, VINLDO = 1.5 V 65 150
IO = 200 mA, VINLDO = 1.8 V 300
Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO1, 2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA 		–1% 1%
Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High-level input voltage 1.3 VCC V
VIL Low-level input voltage 0 0.1 V
Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
T(SD) Thermal shutdown Increasing junction temperature 160 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –2% 2.35 2% V
V(UVLO_HYST) Internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)		 Falling threshold –1% 1 1% V
Hysteresis 40 50 60 mV
Propagation delay 25-mV overdrive 10 μs
POWER-GOOD
V(PGOODF) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8%
V(PGOODR) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3%
(1) Typical values are at TA = 25°C, unless otherwise noted.

6.6 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
I(q) Operating quiescent current, PFM All 3 DCDC converters enabled, zero load, and no switching, LDOs enabled VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 85 100 μA
All 3 DCDC converters enabled, zero load, and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 78 90
DCDC1 and DCDC2 converters enabled, zero load, and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 57 70
DCDC1 converter enabled, zero load, and no switching, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 43 55
II Current into VCC; PWM All 3 DCDC converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 2 3 mA
DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 1.5 2.5
DCDC1 converter enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 0.85 2
I(q) Quiescent current All converters disabled, LDOs off VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 23 33 μA
VCC = 2.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V		 3.5 5 μA
VCC = 3.6 V, VBACKUP = 0 V;
V(VSYSIN) = 0 V		 43 μA
(1) Typical values are at TA = 25°C, unless otherwise noted.

6.7 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VBACKUP, VSYSIN, VRTC
I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP		 20 33 μA
I(SD) Operating quiescent current VBACKUP < V_VBACKUP, current into VBACKUP 2 3 μA
VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 V
IO Output current for VRTC VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA
VRTC short-circuit current limit VRTC = GND; VSYSIN = VBACKUP = 0 V 100 mA
Maximum output current at VRTC for RESPWRON = 1 VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V		 30 mA
VO Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V; IO = 0 mA –1% 1%
Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA –1% 1%
Load regulation VRTC IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V		 –3% 1%
Regulation time for VRTC Load change from 10% to 90% 10 μs
Ilkg Input leakage current at VSYSIN VSYSIN < V_VSYSIN 2 μA
rDS(on) of VSYSIN switch 12.5 Ω
rDS(on) of VBACKUP switch 12.5 Ω
Input voltage range at VBACKUP(1) 2.73 3.75 V
Input voltage range at VSYSIN(1) 2.73 3.75 V
VSYSIN threshold VSYSIN falling –3% 2.55 3% V
VSYSIN threshold VSYSIN rising –3% 2.65 3% V
VBACKUP threshold VBACKUP falling –3% 2.55 3% V
VBACKUP threshold VBACKUP rising –3% 2.65 3% V
VINLDO
I(q) Operating quiescent current Current per LDO into VINLDO
for LDO_CTRL = 0x0		 16 30 μA
I(SD) Shutdown current Total current for both LDOs into VINLDO, VLDO = 0 V 0.1 1 μA
(1) Based on the requirements for the Intel PXA270 processor.
(2) Typical values are at TA = 25°C, unless otherwise noted.

6.8 Electrical Characteristics: VDCDC1 Step-Down Converter

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VI Input voltage range, VINDCDC1 2.5 6 V
IO Maximum output current 1700 mA
I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 125 261 mΩ
Ilkg P-channel leakage current VINDCDC1 = 6 V 2 μA
rDS(on) N-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 130 260 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
Forward current limit (P-channel and
N-channel) 		2.5 V < VI(MAIN) < 6 V 1.94 2.19 2.44 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
Fixed output voltage FPWMDCDC1 = 0 All VDCDC1 VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO  ≤ 1.7 A 		–2% 2%
Fixed output voltage FPWMDCDC1 = 1 VINDCDC1 = 2.5 V to 6 V;
0 mA ≤ IO  ≤ 1.7 A		 –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 0 VINDCDC1 = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO  ≤ 1.7 A –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 1 VINDCDC1 = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO  ≤ 1.7 A –1% 1%
Line Regulation VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA 0% V
Load Regulation IO = 10 mA to 1700 mA 0.25% A
tStart Start-up time Time from active EN to start switching 145 175 200 μs
tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT 400 750 1000 μs
Internal resistance from L1 to GND 1 MΩ
VDCDC1 discharge resistance DCDC1 discharge = 1 300 Ω
(1) Typical values are at TA = 25°C, unless otherwise noted.

 
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