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  • TPS54418 2.95V 至 6V 输入、4A 输出、2MHz、同步降压 SWIFT™ 转换器

    • ZHCSI04E September   2009  – April 2018 TPS54418

      PRODUCTION DATA.  

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  • TPS54418 2.95V 至 6V 输入、4A 输出、2MHz、同步降压 SWIFT™ 转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与输出电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Small Signal Model for Loop Response
      2. 7.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 7.4.3 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Step One: Select the Switching Frequency
        2. 8.2.2.2  Step Two: Select the Output Inductor
        3. 8.2.2.3  Step Three: Choose the Output Capacitor
        4. 8.2.2.4  Step Four: Select the Input Capacitor
        5. 8.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 8.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 8.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 8.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 8.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 8.2.2.9.1 Output Voltage Limitations
        10. 8.2.2.10 Step 10: Select Loop Compensation Components
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计
      2. 11.1.2 开发支持
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS54418 2.95V 至 6V 输入、4A 输出、2MHz、同步降压 SWIFT™ 转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 两个可在 4A 负载下获得高效率的 30mΩ（典型值）MOSFET
  • 开关频率：200kHz 至 2MHz
  • 整个温度范围内的电压基准：0.8V ± 1%
  • 同步至外部时钟
  • 可调软启动/定序
  • 欠压 (UV) 和过压 (OV) 电源正常输出
  • 低运行和关断静态电流
  • 安全启动至预偏置输出电压
  • 逐周期电流限制、过热和频率折返保护
  • 工作结温范围：-40°C 至 150°C
  • 耐热增强型 3mm x 3mm 16 引脚超薄型四方扁平无引线 (WQFN) 封装
  • 使用 TPS54418 并借助 WEBENCH® 电源设计器创建定制设计方案

2 应用

  • 低压、高密度电源系统
  • 针对高性能 DSP、FPGA、ASIC 和微处理器的负载点调节
  • 宽带、网络互联及光纤通信基础设施

3 说明

TPS54418 器件一款全功能 6V、4A 同步降压电流模式转换器，具有两个集成的 MOSFET。

TPS54418 器件集成了 MOSFET、通过实施电流模式控制来减少外部组件数量、通过启用高达 2MHz的开关频率来减小电感尺寸，并借助小型 3mm x 3mm 热增强型 QFN 封装尽量减小器件封装尺寸，从而实现小型设计。

TPS54418 器件可在整个温度范围内为多种负载提供电压基准 (VREF) 精度达 ±1% 的精确调节。

通过集成型 30mΩ MOSFET 和典型值为 350μA 的电源电流可使效率得到最大限度提升。通过使用 EN 引脚进入关断模式，关断电源电流可减少至 2µA。

欠压闭锁在内部设定为 2.6V，但可通过使能引脚上的电阻网络设定阈值将之提高。输出电压启动斜坡由软启动引脚控制。一个开漏电源正常信号表示输出处于其标称电压值的 93% 至 107% 之内。频率折返和热关断功能在过流情况下保护器件不受损坏。

要获得更多 SWIFT ™文档，请参见 TI 网站 www.ti.com.cn/swift。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS54418 WQFN (16) 3.00mm × 3.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化原理图

TPS54418 simp_app_slvs946.gif

效率与输出电流间的关系

TPS54418 eff_fp_slvs946.gif

4 修订历史记录

Changes from D Revision (December 2014) to E Revision

  • 更新标题Go

Changes from C Revision (July 2013) to D Revision

  • 添加了 ESD 额定值 表、特性 说明 部分，器件功能模式 部分，应用和实施 部分，电源相关建议 部分，布局 部分，器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from B Revision (August 2012) to C Revision

  • Added Figure 22 to Typical Characteristics sectionGo
  • Added clarity to Fixed Frequency PWM Control sectionGo
  • Added clarity to Soft-Start Pin sectionGo
  • Added clarity to Synchronize Using the RT/CLK Pin sectionGo
  • Added Step Five: Minimum Load DC COMP Voltage sectionGo
  • Added clarity to the Step Six: Choose the Soft-Start Capacitor sectionGo

5 Pin Configuration and Functions

RTE Package
16 Pin WQFN
(TOP VIEW)
TPS54418 pinout_rte16_slvs974.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
AGND 5 G Analog ground should be electrically connected to GND close to the device.
BOOT 13 I A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP 7 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.
EN 15 I Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors.
GND 3 G Power ground. This pin should be electrically connected directly to the power pad under the device.
4
PH 10 O The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier MOSFET.
11
12
PWRGD 14 O An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-voltage or EN shut down.
RT/CLK 8 I/O Resistor Timing or External Clock input pin.
SS 9 I/O Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft
VIN 1 I Input supply voltage, 2.95 V to 6 V.
2
16
VSENSE 6 I Inverting node of the transconductance (gm) error amplifier.
Thermal Pad G GND pin should be connected to the exposed power pad for proper operation. This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.
(1) I = Input, O = Output, G = Ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage EN, PWRGD, VIN –0.3 7 V
RT/CLK –0.3 6
COMP, SS, VSENSE –0.3 3
BOOT VPH+ 8 V
Output voltage BOOT-PH 8 V
PH –0.6 7
PH (10 ns transient) –2 7
Source current EN, RT/CLK 100 µA
Sink current COMP, SS 100 µA
PWRGD 10 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

 
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