LMR36006 4.2V 至 60V、0.6A 超小型同步降压转换器
- ZHCSI01C April 2018 – October 2019 LMR36006
  
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LMR36006 4.2V 至 60V、0.6A 超小型同步降压转换器

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1 特性

专为可靠耐用的应用而设计
- 高达 66V 的输入瞬态保护
- 结温范围为 –40°C 至 +150°C
- 保护功能：热关断、输入欠压锁定、逐周期电流限制和断续短路保护
- 在 0.6A 负载下具有 0.2V 压降（典型值）
适合可扩展的工业电源
- 与以下器件引脚兼容：
  - LMR36015（60V、1.5A）
  - LMR33620/LMR33630（36V、2A 或 3A）
- 1MHz、2.1MHz 频率选项
在整个负载范围内具有低功率耗散
- 1MHz（24V_IN、5V_OUT、0.6A）时的效率为 87%
- 1MHz（12V_IN、5V_OUT、0.6A）时的效率为 92%
- 在 PFM 模式中提高了轻负载效率
- 低至 26µA 的工作静态电流
小型 2mm × 3mm HotRod™ 封装
解决方案只需很少的外部组件
LMR36006-Q1 和 LMR36015-Q1 具有 400kHz 和 2.1MHz 频率、可调节输出和固定的 3.3V_OUT
进行了优化，可满足超低 EMI 要求
- 符合 CISPR25 5 类标准
- Hotrod™封装可最大限度减少开关节点振铃
- 并行输入路径可最大限度减少寄生电感
- 扩频频谱可降低峰值辐射发射
使用 LMR36006 并借助 WEBENCH® 电源设计器创建定制设计方案

2 应用

3 说明

LMR36006 稳压器是一款易于使用的同步降压直流/直流转换器。该器件具有集成高侧和低侧功率 MOSFET，可在 4.2V 至 60V 的宽输入电压范围内提供高达 0.6A 的输出电流。容差高达 66V。这种瞬态电压耐受能力降低了防止过压所需的设计工作量，并满足 IEC 61000-4-5 的浪涌抗扰度要求。

LMR36006 采用峰值电流模式控制机制来提供最佳的效率和输出电压精度。精密使能支持直接连接到宽输入电压或对器件启动和关断进行精确控制，因此提供了灵活性。附带内置滤波和延迟功能的电源正常状态标志可提供系统状态的真实指示，免去了使用外部监控器的麻烦。

LMR36006 采用 HotRod™ 封装，实现了低噪声、更高的效率和最小的封装裸片比率。此器件需要极少外部组件，其引脚设计可实现简单的 PCB 布局。LMR36006 的小解决方案尺寸和功能集旨在简化各种终端设备的实施，这些终端设备包括超小型现场发送器和视觉传感器等具有严苛空间要求的应用。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LMR36006	VQFN-HR (12)	2.00mm x 3.00mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

LMR36006 typical-characteristic-5vout-1mhz-600ma-efficiency-frontpage.gif

简化原理图

4 修订历史记录

Changes from B Revision (February 2019) to C Revision

添加了 EMI 说明，目标位置：特性Go
Added Figure 33 through Figure 42Go

Changes from A Revision (November 2018) to B Revision

Updated package quantities in Device Comparison Table. Go

Changes from * Revision (April 2018) to A Revision

首次发布生产数据数据表Go

5 Device Comparison Table

ORDERABLE PART NUMBER	OUTPUT VOLTAGE	FPWM	f_SW	PACKAGE QUANTITY
LMR36006BRNXT	Adjustable	No	1 MHz	250
LMR36006BRNXR	Adjustable	No	1 MHz	3000
LMR36006CRNXT	Adjustable	No	2.1 MHz	250
LMR36006CRNXR	Adjustable	No	2.1 MHz	3000

6 Pin Configuration and Functions

RNX Package

12-Pin VQFN-HR

Top View

Pin Functions

NO.	NAME	TYPE	DESCRIPTION
1, 11	PGND	G	Power ground terminal. Connect to system ground and AGND. Connect to C_IN with short wide traces.
2, 10	VIN	P	Input supply to regulator. Connect to C_IN with short wide traces.
3	NC	—	Connect the SW pin to NC on the PCB. This simplifies the connection from the C_BOOT capacitor to the SW pin. This pin has no internal connection to the regulator.
4	BOOT	P	Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this pin to the SW pin. Connect the SW pin to NC on the PCB. This simplifies the connection from the C_BOOT capacitor to the SW pin.
5	VCC	P	Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.
6	AGND	G	Analog ground for regulator and system. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB.
7	FB	A	Feedback input to regulator. Connect to tap point of feedback voltage divider. DO NOT FLOAT. DO NOT GROUND.
8	PG	A	Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. Goes low when EN = Low. Can be open or grounded when not used.
9	EN	A	Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; DO NOT FLOAT.
12	SW	P	Regulator switch node. Connect to power inductor. Connect the SW pin to NC on the PCB. This simplifies the connection from the C_BOOT capacitor to the SW pin.
A = Analog, P = Power, G = Ground

7 Specifications

7.1 Absolute Maximum Ratings

Over operating junction temperature range of -40°C to 150°C (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN to PGND	–0.3	66	V
Input voltage	EN to AGND	–0.3	66.3	V
Input voltage	FB to AGND	–0.3	5.5	V
Input voltage	PG to AGND	–0.3	22	V
Input voltage	AGND to PGND	–0.3	0.3	V
Output voltage	SW to PGND	–0.3	66.3	V
Output voltage	SW to PGND less than 10-ns transients	–3.5	66.3	V
Output voltage	CBOOT to SW	–0.3	5.5	V
Output voltage	VCC to AGND	–0.3	5.5	V
Junction Temperature T_J		-40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM)⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM)⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40 ℃ to 150 ℃ (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN to PGND	4.2	60	V
	EN to PGND⁽²⁾	0	60	V
	PG to PGND⁽²⁾	0	18	V
Output current	I_OUT	0	0.6	A

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMR36006	UNIT
		RNX (VQFN-HR)
		12 PINS
R_θJA	Junction-to-ambient thermal resistance	72.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	35.9	°C/W
R_θJB	Junction-to-board thermal resistance	23.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.8	°C/W
ψ_JB	Junction-to-board characterization parameter	23.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Limits apply over operating junction temperature (T_J ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits⁽¹⁾ are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 24 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
I_Q-nonSW	Operating quiescent current (non-switching)⁽²⁾	V_EN= 3.3 V (PFM variant only)	18	26	36	µA
I_SD	Shutdown quiescent current; measured at VIN pin	V_EN= 0 V		5		µA
ENABLE (EN PIN)
V_EN-VCC-H	Enable input high level for V_CC output	V_ENABLE rising			1.14	V
V_EN-VCC-L	Enable input low level for V_CCoutput	V_ENABLE falling	0.3			V
V_EN-VOUT-H	Enable input high level for V_OUT	V_ENABLE rising	1.157	1.231	1.3	V
V_EN-VOUT-HYS	Enable input hysteresis for V_OUT	Hysteresis below V_ENABLE-H; falling		110		mV
I_LKG-EN	Enable input leakage current	V_EN = 3.3V		0.2		nA
INTERNAL LDO (VCC PIN)
V_CC	Internal V_CC voltage	6 V ≤ V_IN ≤ 60 V	4.75	5	5.25	V
V_{CC-UVLO-Rising}	Internal V_CC undervoltage lockout	V_CC rising	3.6	3.8	4.0	V
V_{CC-UVLO-Falling}	Internal V_CC undervoltage lockout	V_CC falling	3.1	3.3	3.5	V
VOLTAGE REFERENCE (FB PIN)
V_FB	Feedback voltage		0.985	1	1.015	V
I_LKG-FB	Feedback leakage current	FB = 1 V		0.2		nA
CURRENT LIMITS AND HICCUP
I_SC	High-side current limit⁽³⁾		0.8	1	1.2	A
I_LS-LIMIT	Low-side current limit⁽³⁾		0.6	0.8	0.95	A
I_L-ZC	Zero cross detector threshold	PFM variants only		0.02		A
I_PEAK-MIN	Minimum inductor peak current⁽³⁾			0.18		A
POWER GOOD (PGOOD PIN)
V_PG-HIGH-UP	Power-Good upper threshold - rising	% of FB voltage	105%	107%	110%
V_PG-LOW-DN	Power-Good lower threshold - falling	% of FB voltage	90%	93%	95%
V_PG-HYS	Power-Good hysteresis (rising & falling)	% of FB voltage		2%
T_PG	Power-Good rising/falling edge deglitch delay		80	140	200	µs
V_PG-VALID	Minimum input voltage for proper Power-Good function				2	V
R_PG	Power-Good on-resistance	V_EN = 2.5 V		80	165	Ω
R_PG	Power-Good on-resistance	V_EN = 0 V		35	90	Ω
OSCILLATOR
F_OSC	Internal oscillator frequency	2.1-MHz variant	1.95	2.1	2.35	MHz
F_OSC	Internal oscillator frequency	1-MHz variant	0.85	1	1.15	MHz
MOSFETS
R_DS-ON-HS	High-side MOSFET ON-resistance	I_OUT= 0.5 A		225	435	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	I_OUT= 0.5 A		150	280	mΩ

(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

7.6 Timing Requirements

		MIN	NOM	MAX	UNIT
t_ON-MIN	Minimum switch on-time		55	83	ns
t_OFF-MIN	Minimum switch off-time		53	73	ns
t_ON-MAX	Maximum switch on-time		7	12	µs
t_SS	Internal soft-start time	3	4.5	6	ms

7.7 System Characteristics

The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical (TYP) column apply to T_J = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of T_J = –40℃ to 150℃. These specifications are not ensured by production testing.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Operating input voltage range		4.2		60	V
V_OUT	Adjustable output voltage regulation⁽¹⁾	PFM operation	–1.5%		2.5%
I_SUPPLY	Input supply current when in regulation	V_IN = 24 V, V_OUT = 3.3 V, I_OUT = 0 A, R_FBT = 1 MΩ, PFM variant		26		µA
D_MAX	Maximum switch duty cycle⁽²⁾			98%
V_HC	FB pin voltage required to trip short-circuit hiccup mode			0.4		V
t_HC	Time between current-limit hiccup burst			94		ms
t_D	Switch voltage dead time			2		ns
T_SD	Thermal shutdown temperature	Shutdown temperature		170		°C
T_SD	Thermal shutdown temperature	Recovery temperature		158		°C

(1) Deviation in V_OUT from nominal output voltage value at V_IN = 24 V, I_OUT = 0 A to 0.6A

(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: F_MIN = 1 / (t_ON-MAX + t_OFF-MIN). D_MAX = t_ON-MAX /(t_ON-MAX + t_OFF-MIN).

7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: T_A = 25°C. V_IN = 24 V.

V_FB = 1 V

Figure 1. Non-Switching Input Supply Current

V_IN = 24 V

Figure 3. High Side Current Limit

Figure 5. Reference Voltage Drift

EN = 0 V

Figure 2. Shutdown Supply Current

V_IN = 24 V

Figure 4. Low Side Current Limit

I_OUT = 0 A	V_OUT = 3.3 V
ƒ_SW = 1000 kHz

Figure 6. I_PEAK-MIN

8 Detailed Description

8.1 Overview

The LMR36006 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial applications. The regulator automatically switches modes between PFM and PWM depending on load. At heavy loads, the device operates in PWM at a constant switching frequency. At light loads the mode changes to PFM, with diode emulation allowing DCM. This reduces the input supply current and keeps efficiency high. The device features internal loop compensation which reduces design time and requires fewer external components than externally compensated regulators.

The LMR36006 is designed with a flip-chip or HotRod™ technology, greatly reducing the parasitic inductance of pins. In addition, the layout of the device allows for reduction in the radiated noise generated by the switching action through partial cancellation of the current generated magnetic field. As a result the switch-node waveform exhibits less overshoot and ringing.

Figure 7. Switch Node Waveform

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power-Good Flag Output

The power-good flag function (PG output pin) of the LMR36006 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than t_PG do not trip the power-good flag. Power-good operation can best be understood by reference to Figure 8 and Figure 9. Note that during initial power-up a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the power-good function.

The power-good output consists of an open drain NMOS; requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or V_OUT, through an appropriate resistor, as desired. If this function is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4 mA.

Figure 8. Static Power-Good Operation

LMR36006 LMR360XX-pgood-plot-02-snvsay7.gif

Figure 9. Power-Good-Timing Behavior

8.3.2 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use of an external voltage divider to provide an adjustable input UVLO (see the section). Applying a voltage of ≥ V_EN-VCC-H causes the device to enter standby mode, powering the internal VCC, but not producing an output voltage. Increasing the EN voltage to V_EN-OUT-H (V_EN-H in Figure 10) fully enables the device, allowing it to enter start-up mode and beginning the soft-start period. When the EN input is brought below V_EN-OUT-H (V_EN-H in Figure 10) by V_EN-OUT-HYS (V_EN-HYS in Figure 10), the regulator stops running and enters standby mode. Further decrease in the EN voltage to below V_EN-VCC-L completely shuts down the device. This behavior is shown in Figure 10. The EN input may be connected directly to VIN if this feature is not needed. This input must not be allowed to float. The values for the various EN thresholds can be found in the Electrical CharacteristicsElectrical Characteristics table.

The LMR36006 utilizes a reference-based soft start that prevents output voltage overshoots and large inrush currents as the regulator is starting up. A typical start-up waveform is shown in Figure 11 along with typical timings. The rise time of the output voltage is about 4 ms.

LMR36006 LMR360XX-EN-threshold-plot-snvsay7.gif

Figure 10. Precision Enable Behavior

LMR36006 waveform-05-startup-3pt3vout-snvu580.png

Figure 11. Typical Start-up Behavior
V_IN = 24 V, V_OUT = 3.3 V, I_OUT = 0.6 A

8.3.3 Current Limit and Short Circuit

The LMR36006 incorporates valley current limit for normal overloads and for short-circuit protection. In addition the high-side power MOSFET is protected from excessive current by a peak current limit circuit. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement diode emulation mode (DEM) at light loads (see Glossary).

During overloads the low-side current limit, I_LIMIT, determines the maximum load current that the LMR36006 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall below I_LIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until the current falls below I_LIMIT. This is somewhat different than the more typical peak current limit and results in Equation 1 for the maximum load current.

Equation 1. LMR36006 Ilim3_eq3.gif

where

f_SW = switching frequency
L = inductor value

If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters into hiccup mode. In this mode the device stops switching for t_HC or about 94 ms, and then goes through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 12 as long as the short-circuit condition persists. This mode of operation helps to reduce the temperature rise of the device during a hard short on the output. Of course the output current is greatly reduced during hiccup mode. Once the output short is removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 12.

The high-side-current limit trips when the peak inductor current reaches I_SC. This is a cycle-by-cycle current limit and does not produce any frequency or load current fold back. It is meant to protect the high-side MOSFET from excessive current. Under some conditions, such as high input voltages, this current limit may trip before the low-side protection. Under this condition, I_SC determines the maximum output current. Note that I_SC varies with duty cycle.

LMR36006 waveform-04-short-600ma-snvsay7.png

Figure 12. Short-Circuit Transient and Recovery

8.3.4 Undervoltage Lockout and Thermal Shutdown

The LMR36006 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin). When VCC reaches 3.8 V (typ.), the device receives the EN signal and starts switching. When VCC falls below 3.3 V (typ.), the device shuts down, regardless of EN status. Because the LDO is in dropout during these transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.

Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction temperature reaches about 170°C, the device shuts down; re-start occurs when the temperature falls to about 158°C .

8.4 Device Functional Modes

8.4.1 Auto Mode

In auto mode the device moves between PWM and PFM as the load changes. At light loads the regulator operates in PFM. At higher loads the mode changes to PWM.

In PWM the regulator operates as a constant frequency, current mode, full synchronous converter using PWM to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and low output voltage ripple.

In PFM the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The duration of the burst depends on how long it takes the inductor current to reach I_PEAK-MIN. The frequency of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The actual switching frequency and output voltage ripple depends on the input voltage, output voltage, and load. Typical switching waveforms in PFM and PWM are shown in Figure 13 and Figure 14.See the Application Curves for output voltage variation with load in auto mode.

LMR36006 waveform-05-pfm-30mA-06b-snvsay7.jpg

Figure 13. Typical PFM Switching Waveforms
V_IN = 24 V, V_OUT = 5 V, I_OUT = 30 mA

LMR36006 waveform-06-pwm-600mA-06B-snvsay7.jpg

Figure 14. Typical PWM Switching Waveforms
V_IN = 24 V, V_OUT = 5 V, I_OUT = 600 mA, ƒ_S = 1000 kHz

8.4.2 Dropout

The dropout performance of any buck regulator is affected by the R_DSON of the power MOSFETs, the DC resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is reduced to near the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value. Beyond this point the switching may become erratic and/or the output voltage falls out of regulation. To avoid this problem the LMR36006 automatically reduces the switching frequency to increase the effective duty cycle and maintain regulation. In this data sheet the dropout voltage is defined as the difference between the input and output voltage when the output has dropped by 1% of its nominal value. Under this condition the switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure 15 and Figure 16.

LMR36006 D003-tc-drop-out-down-snvsay7-rtm.gif

Figure 15. Overall Dropout Characteristic
V_OUT = 5 V

Figure 16. Typical ƒ_SW vs Output Current
ƒ_SW = 1000 kHz

8.4.3 Minimum Switch On-Time

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times associated with the control circuits. This imposes a minimum switch duty cycle and therefore a minimum conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend the minimum controllable duty cycle, the LMR36006 automatically reduces the switching frequency when the minimum on-time limit is reached. In this way the converter can regulate the lowest programmable output voltage at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before frequency foldback occurs is found in Equation 2. As the input voltage is increased, the switch on-time (duty cycle) reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops, while the on-time remains fixed.

Equation 2. LMR36006 Ton_eq2.gif

LMR36006 LMR36006C-5vout-foldback-snvsb48.gif

Figure 17. Switching Frequency vs Input Voltage
V_OUT = 3.3 V

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.