TPS6282x 具有 1% 输出精度的 2.4V 至 5.5V 输入、1A/2A/3A/4A 降压转换器
- ZHCSHY6I March 2018 – March 2024 TPS62824 , TPS62824A , TPS62825 , TPS62825A , TPS62826 , TPS62826A , TPS62827 , TPS62827A
  
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TPS6282x 具有 1% 输出精度的 2.4V 至 5.5V 输入、1A/2A/3A/4A 降压转换器

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1 特性

可作为集成电感器的电源模块：TPSM82821、TPSM82822 和 TPSM82823
DCS-Control 拓扑
1% 反馈或输出电压精度（整个温度范围）
效率高达 97%
26mΩ 和 25mΩ 内部功率 MOSFET
2.4V 至 5.5V 输入电压范围
运行静态电流 4μA
2.2MHz 开关频率
0.6V 至 4V 可调节输出电压
可实现轻负载效率的省电模式
100% 占空比，可实现超低压降
有源输出放电
电源正常状态输出
热关断保护
断续短路保护
强制 PWM 版本可支持 CCM 运行
使用 TPS6282x 并借助 WEBENCH® Power Designer 创建定制设计方案

2 应用

3 说明

TPS6282x 是易于使用的同步直流/直流降压转换器系列，具有仅 4μA 的超低静态电流。该器件基于 DCS 控制拓扑，可实现快速瞬态响应。由于具有内部基准，该产品可在 -40°C 至 125°C 的结温范围内以 1% 的高反馈电压精度将输出电压调节到 0.6V 以下。该系列器件具有引脚对引脚和 BOM 对 BOM 兼容性。整个设计需要一个小型 470nH 电感器、一个 4.7µF 输入电容器以及两个 10µF 输出电容器（或一个 22µF 输出电容器）。

TPS6282x 具有两种型号。第一种型号可自动进入省电模式，在超轻负载条件下保持高效率，从而延长系统电池的运行时间。第二种型号可实现强制 PWM 运行，以维持连续导通模式，从而确保超低的输出电压纹波和准固定开关频率。该器件具有电源正常信号和内部软启动电路。该器件能够以 100% 模式运行。在故障保护方面，该器件加入了断续短路保护以及热关断功能。该器件采用 6 引脚 1.5mm x 1.5mm QFN 封装，可实现超高功率密度设计。

器件信息

器件型号	封装⁽¹⁾	封装尺寸⁽²⁾
TPS6282xx	DMQ（VSON-HR，6）	1.5mm × 1.5mm

(1) 有关更多信息，请参阅节 11。

(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

典型应用原理图

V_IN = 5V 时的效率

4 Device Options

PART NUMBER	OUTPUT VOLTAGE	OPERATION MODE	OUTPUT CURRENT
TPS62824DMQ	Adjustable	PSM/PWM	1A
TPS62825DMQ	Adjustable		2A
TPS6282518DMQ	1.8V
TPS6282533DMQ	3.3V
TPS62826DMQ	Adjustable		3A
TPS6282618DMQ	1.8V		3A
TPS62827DMQ	Adjustable		4A
TPS62824ADMQ	Adjustable	Forced-PWM	1A
TPS62825ADMQ	Adjustable		2A
TPS62826ADMQ	Adjustable		3A
TPS62827ADMQ	Adjustable		4A

5 Pin Configuration and Functions

Figure 5-1 DMQ Package, 6-Pin VSON-HR (Bottom View)

Table 5-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
EN	1	I	Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low disables the device. Do not leave floating.
PG	2	O	Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5V. If unused, leave the pin floating.
FB	3	I	Feedback pin. For the fixed output voltage versions, this pin must be connected to the output.
GND	4		Ground pin
SW	5	PWR	Switch pin of the power stage
VIN	6	PWR	Input voltage pin

(1) I = input, O = output, PWR = power

6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Voltage at Pins ⁽²⁾	VIN, FB, EN, PG	–0.3	6	V
	SW (DC)⁽⁴⁾	–0.3	V_IN + 0.3
	SW (DC, in current limit)	–1.0	V_IN + 0.3
	SW (AC, less than 10ns) ⁽³⁾	–2.5	10
	SW (AC, PFM Mode, less than 100ns) ⁽³⁾	–1.0	V_IN + 1.0
Temperature	Operating junction temperature, T_J	–40	150	°C
Temperature	Storage temperature, T_stg	–65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to network ground terminal.

(3) While switching.

(4) After disabling the device, the SW voltage may exceed the MIN specification until the inductor and output capacitor are fully discharged.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage range, TPS62824x, TPS62825x and TPS62826x	2.4	5.5	V
V_IN	Input voltage range, TPS62827x	2.5	5.5	V
V_OUT	Output voltage range	0.6	4.0	V
I_OUT	Output current range, TPS62824x	0	1	A
I_OUT	Output current range, TPS62825x	0	2	A
I_OUT	Output current range, TPS62826x	0	3	A
I_OUT	Output current range, TPS62827x	0	4	A
I_{SINK_PG}	Sink current at PG pin		1	mA
V_PG	Pull-up resistor voltage		5.5	V
T_J	Operating junction temperature	-40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DEVICE		UNIT
		TPS6282x, JEDEC	TPS62826EVM-794
		6 pins	6 pins
R_θJA	Junction-to-ambient thermal resistance	129.5	71.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	103.9	n/a ⁽²⁾	°C/W
R_θJB	Junction-to-board thermal resistance	33.1	n/a ⁽²⁾	°C/W
ψ_JT	Junction-to-top characterization parameter	3.8	3.9	°C/W
ψ_JB	Junction-to-board characterization parameter	33.1	38.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Not applicable to an EVM.

6.5 Electrical Characteristics

T_J = -40 °C to 125 °C, and V_IN = 2.4 V to 5.5 V. Typical values are at T_J = 25 °C and V_IN = 5 V , unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Quiescent current	EN = High, no load, device not switching		4	10	µA
I_Q	Quiescent current	EN = High, no load, FPWM devices		8		mA
I_SD	Shutdown current	EN = Low, T_J = -40 ℃ to 85 ℃		0.05	0.5	µA
V_UVLO	Under voltage lock out threshold	V_IN falling	2.1	2.2	2.3	V
V_UVLO	Under voltage lock out hysteresis	V_IN rising		160		mV
T_JSD	Thermal shutdown threshold	T_J rising		150		°C
T_JSD	Thermal shutdown hysteresis	T_J falling		20		°C
LOGIC INTERFACE EN
V_IH	High-level threshold voltage		1.0			V
V_IL	Low-level threshold voltage				0.4	V
I_EN,LKG	Input leakage current into EN pin	EN = High		0.01	0.1	µA
SOFT START, POWER GOOD
t_SS	Soft start time	Time from EN high to 95% of V_OUT nominal, TPS62827		1.75		ms
t_SS	Soft start time	Time from EN high to 95% of V_OUT nominal, TPS62824x/5x/6x/7A		1.25		ms
V_PG	Power good lower threshold	V_PG rising, V_FB referenced to V_FB nominal	94	96	98	%
	Power good lower threshold	V_PG falling, V_FB referenced to V_FB nominal	90	92	94	%
	Power good upper threshold	V_PG rising, V_FB referenced to V_FB nominal	108	110	112	%
	Power good upper threshold	V_PG falling, V_FB referenced to V_FB nominal	103	105	107	%
V_PG,OL	Low-level output voltage	I_sink = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5.0 V		0.01	0.1	µA
t_PG,DLY	Power good deglitch delay	PG rising edge		100		µs
t_PG,DLY	Power good deglitch delay	PG falling edge		20		µs
OUTPUT
V_OUT	Output voltage accuracy	TPS6282533, PWM mode	3.267	3.3	3.333	V
V_OUT	Output voltage accuracy	TPS6282x18, PWM mode	1.78	1.8	1.82	V
V_FB	Feedback regulation voltage	PWM mode	594	600	606	mV
I_FB,LKG	Feedback input leakage current for adjustable output voltage	V_FB = 0.6 V		0.01	0.05	µA
R_FB	Internal resistor divider connected to FB pin, for fixed output votlage	TPS6282518, TPS6282618, TPS6282533		7.5		MΩ
I_DIS	Output discharge current	V_SW = 0.4V; EN = LOW	75	400		mA
	Load regulation	I_OUT= 0.5 A to 3 A, V_OUT = 1.8 V		0.1		%/A
POWER SWITCH
R_DS(on)	High-side FET on-resistance			26		mΩ
R_DS(on)	Low-side FET on-resistance			25		mΩ
I_LIM	High-side FET switch current limit, DC	TPS62824A	1.7	2.1	2.4	A
		TPS62825x	2.74	3.3	3.9	A
		TPS62826x	3.7	4.3	5.0	A
		TPS62827x	4.8	5.6	6.4	A
I_LIM	Low-side FET negative current limit, DC	TPS62824A/5A/6A/7A		–1.6		A
f_SW	PWM switching frequency	I_OUT= 1 A, V_OUT = 1.8 V		2.2		MHz

6.6 Typical Characteristics

Figure 6-1 High-Side FET On-Resistance

Figure 6-3 Shutdown Current

Figure 6-5 Output Discharge Current

Figure 6-2 Low-Side FET On-Resistance

Figure 6-4 Quiescent Current

7 Detailed Description

7.1 Overview

The TPS6282x are synchronous step-down converters based on the DCS-Control topology with an adaptive constant on-time control and a stabilized switching frequency. The devices operate in PWM (pulse width modulation) mode for medium to heavy loads and in PSM (power save mode) at light load conditions, keeping the output voltage ripple small. The nominal switching frequency is about 2.2MHz with a small and controlled variation over the input voltage range. As the load current decreases, the converter enters PSM, reducing the switching frequency to keep efficiency high over the entire load current range. Because combining both PWM and PSM within a single building block, the transition between modes is seamless and without effect on the output voltage. In forced-PWM devices, the converter maintains a continuous conduction mode operation and keeps the output voltage ripple very low across the whole load range and at a nominal switching frequency of 2.2MHz. The devices offer both excellent dc voltage and fast load transient regulation, combined with a very low output voltage ripple.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Pulse Width Modulation (PWM) Operation

At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with stabilized switching frequency. To achieve a stable switching frequency in a steady state condition, the on-time is calculated as:

Equation 1.

$T_{O N} = \frac{V_{O U T}}{V_{I N}} \times 450 n s$

In forced-PWM devices, the device always operates in pulse width modulation in continuous conduction mode (CCM).

7.3.2 Power Save Mode (PSM) Operation

To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to discontinuous conduction mode (DCM). This event happens when the output current becomes smaller than half of the ripple current of the inductor. The device operates now with a fixed on-time and the switching frequency further decreases proportional to the load current. Use the following equation to calculate:

Equation 2.

$f_{P S M} = \frac{2 \times I_{O U T}}{T_{O N}^{2} \times \frac{V_{I N}}{V_{O U T}} [\frac{V_{I N} - V_{O U T}}{L}]}$

In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output capacitance. At duty cycles larger than 90%, the device can not enter PSM. The device maintains output regulation in PWM mode.

7.3.3 Minimum Duty Cycle and 100% Mode Operation

There is no limitation for small duty cycles, because even at very low duty cycles, the switching frequency is reduced as needed to always make sure of a proper regulation.

If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is determined by the voltage drop across the high-side FET and the DC resistance of the inductor. The minimum VIN that is needed to maintain a specific VOUT value is estimated as:

Equation 3.

$V_{I N, m i n} = V_{O U T} + I_{O U T, M A X} \times (R_{D S (o n)} + R_{L})$

where

V_IN,MIN = Minimum input voltage to maintain an output voltage
I_OUT,MAX = Maximum output current
R_DS(on) = High-side FET ON-resistance
R_L = Inductor ohmic resistance (DCR)

7.3.4 Soft Start

About 250μs after EN goes High, the internal soft-start circuitry controls the output voltage during start-up. This action avoids excessive inrush current and makes sure of a controlled output voltage ramp. This action also prevents unwanted voltage drops from high-impedance power sources or batteries. The TPS6282x can start into a prebiased output.