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TPS6282x 是易于使用的同步直流/直流降压转换器系列,具有仅 4μA 的超低静态电流。该器件基于 DCS 控制拓扑,可实现快速瞬态响应。由于具有内部基准,该产品可在 -40°C 至 125°C 的结温范围内以 1% 的高反馈电压精度将输出电压调节到 0.6V 以下。该系列器件具有引脚对引脚和 BOM 对 BOM 兼容性。整个设计需要一个小型 470nH 电感器、一个 4.7µF 输入电容器以及两个 10µF 输出电容器(或一个 22µF 输出电容器)。
TPS6282x 具有两种型号。第一种型号可自动进入省电模式,在超轻负载条件下保持高效率,从而延长系统电池的运行时间。第二种型号可实现强制 PWM 运行,以维持连续导通模式,从而确保超低的输出电压纹波和准固定开关频率。该器件具有电源正常信号和内部软启动电路。该器件能够以 100% 模式运行。在故障保护方面,该器件加入了断续短路保护以及热关断功能。该器件采用 6 引脚 1.5mm x 1.5mm QFN 封装,可实现超高功率密度设计。
PART NUMBER | OUTPUT VOLTAGE | OPERATION MODE | OUTPUT CURRENT |
---|---|---|---|
TPS62824DMQ | Adjustable | PSM/PWM | 1A |
TPS62825DMQ | Adjustable | 2A | |
TPS6282518DMQ | 1.8V | ||
TPS6282533DMQ | 3.3V | ||
TPS62826DMQ | Adjustable | 3A | |
TPS6282618DMQ | 1.8V | ||
TPS62827DMQ | Adjustable | 4A | |
TPS62824ADMQ | Adjustable | Forced-PWM | 1A |
TPS62825ADMQ | Adjustable | 2A | |
TPS62826ADMQ | Adjustable | 3A | |
TPS62827ADMQ | Adjustable | 4A |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 1 | I | Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low disables the device. Do not leave floating. |
PG | 2 | O | Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5V. If unused, leave the pin floating. |
FB | 3 | I | Feedback pin. For the fixed output voltage versions, this pin must be connected to the output. |
GND | 4 | Ground pin | |
SW | 5 | PWR | Switch pin of the power stage |
VIN | 6 | PWR | Input voltage pin |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage at Pins (2) | VIN, FB, EN, PG | –0.3 | 6 | V |
SW (DC)(4) | –0.3 | VIN + 0.3 | ||
SW (DC, in current limit) | –1.0 | VIN + 0.3 | ||
SW (AC, less than 10ns) (3) | –2.5 | 10 | ||
SW (AC, PFM Mode, less than 100ns) (3) | –1.0 | VIN + 1.0 | ||
Temperature | Operating junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±500 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage range, TPS62824x, TPS62825x and TPS62826x | 2.4 | 5.5 | V | |
VIN | Input voltage range, TPS62827x | 2.5 | 5.5 | V | |
VOUT | Output voltage range | 0.6 | 4.0 | V | |
IOUT | Output current range, TPS62824x | 0 | 1 | A | |
IOUT | Output current range, TPS62825x | 0 | 2 | A | |
IOUT | Output current range, TPS62826x | 0 | 3 | A | |
IOUT | Output current range, TPS62827x | 0 | 4 | A | |
ISINK_PG | Sink current at PG pin | 1 | mA | ||
VPG | Pull-up resistor voltage | 5.5 | V | ||
TJ | Operating junction temperature | -40 | 125 | °C |
THERMAL METRIC(1) | DEVICE | UNIT | ||
---|---|---|---|---|
TPS6282x, JEDEC | TPS62826EVM-794 | |||
6 pins | 6 pins | |||
RθJA | Junction-to-ambient thermal resistance | 129.5 | 71.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 103.9 | n/a (2) | °C/W |
RθJB | Junction-to-board thermal resistance | 33.1 | n/a (2) | °C/W |
ψJT | Junction-to-top characterization parameter | 3.8 | 3.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 33.1 | 38.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ | Quiescent current | EN = High, no load, device not switching | 4 | 10 | µA | |
IQ | Quiescent current | EN = High, no load, FPWM devices | 8 | mA | ||
ISD | Shutdown current | EN = Low, TJ = -40 ℃ to 85 ℃ | 0.05 | 0.5 | µA | |
VUVLO | Under voltage lock out threshold | VIN falling | 2.1 | 2.2 | 2.3 | V |
Under voltage lock out hysteresis | VIN rising | 160 | mV | |||
TJSD | Thermal shutdown threshold | TJ rising | 150 | °C | ||
Thermal shutdown hysteresis | TJ falling | 20 | °C | |||
LOGIC INTERFACE EN | ||||||
VIH | High-level threshold voltage | 1.0 | V | |||
VIL | Low-level threshold voltage | 0.4 | V | |||
IEN,LKG | Input leakage current into EN pin | EN = High | 0.01 | 0.1 | µA | |
SOFT START, POWER GOOD | ||||||
tSS | Soft start time | Time from EN high to 95% of VOUT nominal, TPS62827 | 1.75 | ms | ||
Time from EN high to 95% of VOUT nominal, TPS62824x/5x/6x/7A | 1.25 | ms | ||||
VPG | Power good lower threshold | VPG rising, VFB referenced to VFB nominal | 94 | 96 | 98 | % |
VPG falling, VFB referenced to VFB nominal | 90 | 92 | 94 | % | ||
Power good upper threshold | VPG rising, VFB referenced to VFB nominal | 108 | 110 | 112 | % | |
VPG falling, VFB referenced to VFB nominal | 103 | 105 | 107 | % | ||
VPG,OL | Low-level output voltage | Isink = 1 mA | 0.4 | V | ||
IPG,LKG | Input leakage current into PG pin | VPG = 5.0 V | 0.01 | 0.1 | µA | |
tPG,DLY | Power good deglitch delay | PG rising edge | 100 | µs | ||
PG falling edge | 20 | |||||
OUTPUT | ||||||
VOUT | Output voltage accuracy | TPS6282533, PWM mode | 3.267 | 3.3 | 3.333 | V |
VOUT | Output voltage accuracy | TPS6282x18, PWM mode | 1.78 | 1.8 | 1.82 | V |
VFB | Feedback regulation voltage | PWM mode | 594 | 600 | 606 | mV |
IFB,LKG | Feedback input leakage current for adjustable output voltage | VFB = 0.6 V | 0.01 | 0.05 | µA | |
RFB | Internal resistor divider connected to FB pin, for fixed output votlage | TPS6282518, TPS6282618, TPS6282533 | 7.5 | MΩ | ||
IDIS | Output discharge current | VSW = 0.4V; EN = LOW | 75 | 400 | mA | |
Load regulation | IOUT = 0.5 A to 3 A, VOUT = 1.8 V | 0.1 | %/A | |||
POWER SWITCH | ||||||
RDS(on) | High-side FET on-resistance | 26 | mΩ | |||
Low-side FET on-resistance | 25 | mΩ | ||||
ILIM | High-side FET switch current limit, DC | TPS62824A | 1.7 | 2.1 | 2.4 | A |
TPS62825x | 2.74 | 3.3 | 3.9 | A | ||
TPS62826x | 3.7 | 4.3 | 5.0 | A | ||
TPS62827x | 4.8 | 5.6 | 6.4 | A | ||
ILIM | Low-side FET negative current limit, DC | TPS62824A/5A/6A/7A | –1.6 | A | ||
fSW | PWM switching frequency | IOUT = 1 A, VOUT = 1.8 V | 2.2 | MHz |
The TPS6282x are synchronous step-down converters based on the DCS-Control topology with an adaptive constant on-time control and a stabilized switching frequency. The devices operate in PWM (pulse width modulation) mode for medium to heavy loads and in PSM (power save mode) at light load conditions, keeping the output voltage ripple small. The nominal switching frequency is about 2.2MHz with a small and controlled variation over the input voltage range. As the load current decreases, the converter enters PSM, reducing the switching frequency to keep efficiency high over the entire load current range. Because combining both PWM and PSM within a single building block, the transition between modes is seamless and without effect on the output voltage. In forced-PWM devices, the converter maintains a continuous conduction mode operation and keeps the output voltage ripple very low across the whole load range and at a nominal switching frequency of 2.2MHz. The devices offer both excellent dc voltage and fast load transient regulation, combined with a very low output voltage ripple.
At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with stabilized switching frequency. To achieve a stable switching frequency in a steady state condition, the on-time is calculated as:
In forced-PWM devices, the device always operates in pulse width modulation in continuous conduction mode (CCM).
To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to discontinuous conduction mode (DCM). This event happens when the output current becomes smaller than half of the ripple current of the inductor. The device operates now with a fixed on-time and the switching frequency further decreases proportional to the load current. Use the following equation to calculate:
In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output capacitance. At duty cycles larger than 90%, the device can not enter PSM. The device maintains output regulation in PWM mode.
There is no limitation for small duty cycles, because even at very low duty cycles, the switching frequency is reduced as needed to always make sure of a proper regulation.
If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is determined by the voltage drop across the high-side FET and the DC resistance of the inductor. The minimum VIN that is needed to maintain a specific VOUT value is estimated as:
where
About 250μs after EN goes High, the internal soft-start circuitry controls the output voltage during start-up. This action avoids excessive inrush current and makes sure of a controlled output voltage ramp. This action also prevents unwanted voltage drops from high-impedance power sources or batteries. The TPS6282x can start into a prebiased output.
The switch current limit prevents the device from drawing excessive current in case of externally-caused overcurrent or short-circuit condition. Due to an internal propagation delay (typically 60ns), the actual AC peak current can exceed the static current limit during that time.
If the current limit threshold is reached, the device delivers maximum output current. Detecting this condition for 32 switching cycles (about 13μs), the device turns off the high-side MOSFET for about 100μs which allows the inductor current to decrease through the low-side MOSFET body diode and then restarts again with a soft start cycle. As long as the overload condition is present, the device hiccups that way, limiting the output power.
In forced PWM devices, a negative current limit (ILIMN) is enabled to prevent excessive current flowing backwards to the input. When the inductor current reaches ILIMN, the low-side MOSFET turns off and the high-side MOSFET turns on and kept on until TON time expires.
The undervoltage lockout (UVLO) function prevents misoperation of the device if the input voltage drops below the UVLO threshold. The undervoltage lockout is set to about 2.2V with a hysteresis of typically 160mV.
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 150°C (typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. After TJ has decreased enough, the device resumes normal operation.
The device starts operation when Enable (EN) is set High. The input threshold levels are typically 0.9V for rising and 0.7V for falling signals. Do not leave EN floating. Shutdown is forced if EN is pulled Low with a shutdown current of typically 50nA. During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off and the output voltage is actively discharged through the SW pin by a current sink. Therefore VIN must remain present for the discharge to function.
The TPS6282x has a built-in power-good (PG) function. The PG pin goes high impedance when the output voltage has reached the nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low (see Table 7-1). The PG function is formed with a window comparator, which has an upper and lower voltage threshold. The PG pin is an open-drain output and is specified to sink up to 1mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. The PG rising edge has a 100µs blanking time and the PG falling edge has a deglitch delay of 20µs.
DEVICE CONDITIONS | LOGIC STATUS | ||
---|---|---|---|
HIGH Z | LOW | ||
Enable | EN = High, VFB ≥ 0.576V | √ | |
EN = High, VFB ≤ 0.552V | √ | ||
EN = High, VFB ≤ 0.63V | √ | ||
EN = High, VFB ≥ 0.66V | √ | ||
Shutdown | EN = Low | √ | |
Thermal Shutdown | TJ > TJSD | √ | |
UVLO | 0.7V < VIN < VUVLO | √ | |
Power Supply Removal | VIN < 0.7V | √ |
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
The following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference.
For this design example, use the parameters listed in Table 8-1 as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage, TPS62826x | 2.4V to 5.5V |
Input voltage, TPS62827x | 2.5V to 5.5V |
Output voltage | 1.8V |
Output ripple voltage | < 20mV |
Maximum output current, TPS62826x | 3A |
Maximum output current, TPS62827x | 4A |
Table 8-2 lists the components used for the example.
REFERENCE | DESCRIPTION | MANUFACTURER |
---|---|---|
C1 | 4.7µF, Ceramic capacitor, 6.3V, X7R, size 0603, JMK107BB7475MA | Taiyo Yuden |
C2, TPS62824x/5x/6x/7A | 2 × 10µF, Ceramic capacitor, 10V, X7R, size 0603, GRM188Z71A106MA73D | Murata |
C2, TPS62827 | 3 × 10µF, Ceramic capacitor, 10V, X7R, size 0603, GRM188Z71A106MA73D | Murata |
C3 | 120pF, Ceramic capacitor, 50V, size 0402 | Std |
L1 | 0.47µH, Power Inductor, XFL4015-471MEB | Coilcraft |
R1 | Depending on the output voltage, 1%, size 0402 | Std |
R2 | 100kΩ, Chip resistor, 1/16W, 1%, size 0402 | Std |
R3 | 100kΩ, Chip resistor, 1/16W, 1%, size 0402 | Std |
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The output voltage is set by an external resistor divider according to Equation 4:
R2 must not be higher than 100kΩ to achieve high efficiency at light load while providing acceptable noise sensitivity. Equation 5 shows how to compute the value of the feedforward capacitor for a given R2 value. For the recommended 100k value for R2, a 120pF feedforward capacitor is used.
For the fixed output voltage versions, connect the FB pin to the output. R1, R2, and C3 are not needed. The fixed output voltage devices have an internal feedforward capacitor.
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 8-3 outlines possible inductor and capacitor value combinations for most applications. Checked cells represent combinations that are proven for stability by simulation and lab test. check further combinations for each individual application.
NOMINAL L [µH](2) | NOMINAL COUT [µF](3) | |||
---|---|---|---|---|
10 | 2 × 10 or 22 | 47 | 100 | |
0.33 | ||||
0.47 | + | +(1) | + | |
1.0 |
The main parameter for the inductor selection is the inductor value and then the saturation current of the inductor. To calculate the maximum inductor current under static load conditions, Equation 6 is given.
where
TI recommends to choose a saturation current for the inductor that is approximately 20% to 30% higher than IL,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate inductor. Table 8-5 lists recommended inductors.
INDUCTANCE [µH] | CURRENT RATING [A] | DIMENSIONS [L × W × H mm] | MAX. DC RESISTANCE [mΩ] | MFR PART NUMBER(1) |
---|---|---|---|---|
0.47 | 4.8 | 2.0 × 1.6 × 1.0 | 32 | HTEN20161T-R47MDR, Cyntec |
4.6 | 2.0 × 1.2 × 1.0 | 25 | HTEH20121T-R47MSR, Cyntec | |
4.8 | 2.0 × 1.6 × 1.0 | 32 | DFE201610E - R47M, MuRata | |
4.8 | 2.0 × 1.6 × 1.0 | 32 | DFE201210S - R47M, MuRata | |
5.1 | 2.0 × 1.6 × 1.0 | 34 | TFM201610ALM-R47MTAA, TDK | |
5.2 | 2.0 × 1.6 × 1.0 | 25 | TFM201610ALC-R47MTAA, TDK | |
6.6 | 4.0 × 4.0 × 1.6 | 8.36 | XFL4015-471ME, Coilcraft | |
8.0 | 3.5 × 3.2 × 2.0 | 10.85 | XEL3520-471ME, Coilcraft | |
6.8 | 4.5 × 4 × 1.8 | 11.2 | WE-LHMI-744373240047, Würth |
The input capacitor is the low-impedance energy source for the converters which helps provide stable operation. TI recommends a low-ESR multilayer ceramic capacitor for best filtering and must be placed between VIN and GND as close as possible to those pins. For most applications, a minimum effective input capacitance of 3µF must be present, though a larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep the low resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends using X7R or X5R dielectrics. Considering the DC-bias derating the capacitance, the minimum effective output capacitance is 10µF for TPS62824x, TPS62825x, TPS62826x. and TPS62827A and 20µF for TPS62827.
A feed forward capacitor is required for the adjustable version, as described in Setting the Output Voltage. This capacitor is not required for the fixed output voltage versions.
VIN = 5.0V, VOUT = 1.8V, TA = 25°C, BOM = Table 8-2, unless otherwise noted.
VOUT = 0.6V |
VOUT = 0.6V | F-PWM devices |
VOUT = 1.2V |
VOUT = 1.2V | F-PWM devices |
VOUT = 1.8V |
VOUT = 1.8V | F-PWM devices |
VOUT = 2.5V |
VOUT = 2.5V | F-PWM devices |
VOUT = 3.3V |
VOUT = 3.3V | F-PWM devices |
VIN = 3.3V | TPS62824, TPS62825, TPS62826 |
VIN = 3.3V | TPS62824A/5A/6A/7A |
VIN = 3.3V | TPS62827 |
VOUT = 1.2V | θJA= 71.4°C/W |
VOUT = 2.5V | θJA= 71.4°C/W |
IOUT = 1.0A | TPS62824/5/6/7 |
IOUT = 1.0A | TPS62824A/5A/6A/7A |
Load = 0.6Ω | TPS62826 |
Load = 0.6Ω | TPS62826A/7A |
Load = 1.8Ω | TPS6282x |
IOUT = 0.05A to 1A | TPS62824/5/6/7 |
IOUT = 0.05A to 1A | TPS62824A/5A/6A/7A |
IOUT = 1A | TPS6282x |
VOUT = 0.6V |
VOUT = 0.6V | F-PWM devices |
VOUT = 1.2V |
VOUT = 1.2V | F-PWM devices |
VOUT = 1.8V |
VOUT = 1.8V | F-PWM devices |
VOUT = 2.5V |
VOUT = 2.5V | F-PWM devices |
VOUT = 3.3V |
VOUT = 3.3V | F-PWM devices |
IOUT = 1.0A | TPS62824, TPS62825, TPS62826 |
IOUT = 1.0A | TPS62824A/5A/6A/7A |
IOUT = 1.0A | TPS62827 |
VOUT = 1.8V | θJA= 71.4°C/W |
VOUT = 3.3V | θJA= 71.4°C/W |
IOUT = 0.1A | TPS62824/5/6/7 |
No load | TPS62824A/5A/6A/7A |
TPS62824/5/6 |
TPS62824A/5A/6A/7A |
TPS6282x |
IOUT = 1A to 2A | TPS62825/6/7 |
IOUT = 1A to 2A | TPS62825A/6A/7A |
IOUT = 1A | TPS6282x |
The device is designed to operate from an input voltage supply range from 2.4V to 5.5V. Make sure that the input power supply has a sufficient current rating for the application.