DAC7568、DAC8168 和 DAC8568 分别为 12 位、14 位和 16 位低功耗、电压输出、八通道数模转换器 (DAC)。这些器件包括一个 2.5V、2ppm/°C 内部基准电压(默认禁用),可提供 2.5V 或 5V 的满量程输出电压范围。内部基准电压初始精度为 0.004%,而且可在 VREFIN/VREFOUT 引脚上提供高达 20mA 的电流。这些器件具有单调性,可提供出色的线性并降低有害的代码至代码转换时的瞬态电压(毛刺脉冲)。它们使用一个运行时钟速率高达 50MHz 的多用途 3 线制串口。此接口与标准 SPI™、 QSPI™、 Microwire™,以及数字信号处理器 (DSP) 接口兼容。
DAC7568、DAC8168 和 DAC8568 包含一个上电复位电路,此电路确保 DAC 输出在零电平或中间电平时上电,并在一段有效代码被写入器件前保持此状态。这些器件包含一个由串口访问的断电特性,这将器件在电压为 5V 时的流耗减少至 0.18μA(典型值)。3V 时的功耗(包括内部基准)通常为 2.9mW,在断电模式下可降低至低于 1μW。低功耗、内部基准电压和小封装尺寸使得这些器件非常适合于便携式、电池供电类设备。
DAC7568、DAC8168 和 DAC8568 互为功能兼容型直接替代产品,可提供 TSSOP-16 和 TSSOP-14 封装。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
DAC7568 | TSSOP (14) | 5.00mm x 4.40mm |
TSSOP (16) | 5.00mm x 4.40mm | |
DAC8168 | TSSOP (14) | 5.00mm x 4.40mm |
TSSOP (16) | 5.00mm x 4.40mm | |
DAC8568 | TSSOP (16) | 5.00mm x 4.40mm |
Changes from E Revision (January 2014) to F Revision
Changes from D Revision (May 2012) to E Revision
Changes from C Revision (February 2011) to D Revision
Changes from B Revision (November 2010) to C Revision
Changes from A Revision (April 2009) to B Revision
PRODUCT | MAXIMUM RELATIVE ACCURACY (LSB) | MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) | MAXIMUM REFERENCE DRIFT
(ppm/°C) |
OUTPUT VOLTAGE
FULL-SCALE RANGE |
RESET TO | RESOLUTION |
---|---|---|---|---|---|---|
DAC8568A | ±12 | ±1 | 25 | 2.5V | Zero | 16 |
DAC8568B | ±12 | ±1 | 25 | 2.5V | Midscale | 16 |
DAC8568C | ±12 | ±1 | 5 | 5V | Zero | 16 |
DAC8568D | ±12 | ±1 | 5 | 5V | Midscale | 16 |
DAC8168A | ±4 | ±0.5 | 25 | 2.5V | Zero | 14 |
DAC8168C | ±4 | ±0.5 | 5 | 5V | Zero | 14 |
DAC7568A | ±1 | ±0.25 | 25 | 2.5V | Zero | 12 |
DAC7568C | ±1 | ±0.25 | 5 | 5V | Zero | 12 |
16-PIN | 14-PIN | NAME | DESCRIPTION |
---|---|---|---|
1 | — | LDAC | Load DACs. |
2 | 1 | SYNC | Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input. |
3 | 2 | AVDD | Power-supply input, 2.7V to 5.5V |
4 | 3 | VOUTA | Analog output voltage from DAC A |
5 | 4 | VOUTC | Analog output voltage from DAC C |
6 | 5 | VOUTE | Analog output voltage from DAC E |
7 | 6 | VOUTG | Analog output voltage from DAC G |
8 | 7 | VREFIN/
VREFOUT |
Positive reference input / reference output 2.5V if internal reference used.(1) |
9 | — | CLR | Asynchronous clear input. |
10 | 8 | VOUTH | Analog output voltage from DAC H |
11 | 9 | VOUTF | Analog output voltage from DAC F |
12 | 10 | VOUTD | Analog output voltage from DAC D |
13 | 11 | VOUTB | Analog output voltage from DAC B |
14 | 12 | GND | Ground reference point for all circuitry on the device |
15 | 13 | DIN | Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input. |
16 | 14 | SCLK | Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input. |