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  • 具有 2.5V、2ppm/°C 内部基准电压的 DAC7568、DAC8168、DAC8568 12/14/16 位、8 通道、超低毛刺、电压输出数模转换器

    • ZHCSHR4F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

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  • 具有 2.5V、2ppm/°C 内部基准电压的 DAC7568、DAC8168、DAC8568 12/14/16 位、8 通道、超低毛刺、电压输出数模转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements
    4. 7.4 Typical Characteristics: Internal Reference
    5. 7.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 7.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 7.7 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Digital-to-Analog Converter (DAC)
      2. 8.2.2  Resistor String
      3. 8.2.3  Output Amplifier
      4. 8.2.4  Internal Reference
      5. 8.2.5  Serial Interface
      6. 8.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 8.2.7  SYNC Interrupt
      8. 8.2.8  Power-on Reset to Zero Scale or Midscale
      9. 8.2.9  Clear Code Register and CLR Pin
      10. 8.2.10 Software Reset Function
      11. 8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 8.3 Device Functional Modes
      1. 8.3.1 Enable/Disable Internal Reference
        1. 8.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 8.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 8.3.2 LDAC Functionality
      3. 8.3.3 Power-Down Modes
        1. 8.3.3.1 DAC Power-Down Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications - Microprocessor Interfacing
      1. 9.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Internal Reference
            1. 9.2.1.1.1.1 Supply Voltage
            2. 9.2.1.1.1.2 Temperature Drift
            3. 9.2.1.1.1.3 Noise Performance
            4. 9.2.1.1.1.4 Load Regulation
            5. 9.2.1.1.1.5 Long-Term Stability
            6. 9.2.1.1.1.6 Thermal Hysteresis
          2. 9.2.1.1.2 DAC Noise Performance
          3. 9.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 9.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 9.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 静态性能
          1. 11.1.1.1.1  分辨率
          2. 11.1.1.1.2  最低有效位 (LSB)
          3. 11.1.1.1.3  最高有效位 (MSB)
          4. 11.1.1.1.4  相对精度或积分非线性 (INL)
          5. 11.1.1.1.5  微分非线性 (DNL)
          6. 11.1.1.1.6  满量程误差
          7. 11.1.1.1.7  偏移误差
          8. 11.1.1.1.8  零代码误差
          9. 11.1.1.1.9  增益误差
          10. 11.1.1.1.10 满量程误差漂移
          11. 11.1.1.1.11 偏移误差漂移
          12. 11.1.1.1.12 零代码误差漂移
          13. 11.1.1.1.13 增益温度系数
          14. 11.1.1.1.14 电源抑制比 (PSRR)
          15. 11.1.1.1.15 单调性
        2. 11.1.1.2 动态性能
          1. 11.1.1.2.1  压摆率
          2. 11.1.1.2.2  输出电压稳定时间
          3. 11.1.1.2.3  代码更改/数模转换毛刺脉冲能量
          4. 11.1.1.2.4  数字馈通
          5. 11.1.1.2.5  通道到通道直流串扰
          6. 11.1.1.2.6  通道到通道交流串扰
          7. 11.1.1.2.7  信噪比 (SNR)
          8. 11.1.1.2.8  总谐波失真 (THD)
          9. 11.1.1.2.9  无杂散动态范围 (SFDR)
          10. 11.1.1.2.10 信噪比和失真率 (SINAD)
          11. 11.1.1.2.11 DAC 输出噪声密度
          12. 11.1.1.2.12 DAC 输出噪声
          13. 11.1.1.2.13 满量程范围 (FSR)
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

具有 2.5V、2ppm/°C 内部基准电压的 DAC7568、DAC8168、DAC8568 12/14/16 位、8 通道、超低毛刺、电压输出数模转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 相对精度：
    • DAC7568（12 位）：0.3 LSB INL
    • DAC8168（14 位）：1 LSB INL
    • DAC8568（16 位）：4 LSB INL
  • 毛刺脉冲能量：0.1nV-s
  • 内部基准电压：
    • 2.5V 基准电压（默认为禁用）
    • 0.004% 初始精度（典型值）
    • 2ppm/°C 温漂（典型值）
    • 5ppm/°C 温漂（最大值）
    • 20mA 灌电流/拉电流能力
  • 上电复位至零电平或中间电平
  • 超低功耗运行：1.25mA/5V（包括内部基准电流）
  • 宽电源范围：+2.7V 至 +5.5V
  • 在整个温度范围内具有单调性
  • 具有施密特触发输入的低功耗串口：高达 50MHz
  • 支持轨至轨运行的片上输出缓冲放大器
  • 温度范围：-40°C 至 +125°C

2 应用

  • 便携式仪表
  • 闭环伺服控制/流程控制
  • 数据采集系统
  • 可编程衰减、数字增益和失调电压调节
  • 可编程电压源和电流源

3 说明

DAC7568、DAC8168 和 DAC8568 分别为 12 位、14 位和 16 位低功耗、电压输出、八通道数模转换器 (DAC)。这些器件包括一个 2.5V、2ppm/°C 内部基准电压（默认禁用），可提供 2.5V 或 5V 的满量程输出电压范围。内部基准电压初始精度为 0.004%，而且可在 VREFIN/VREFOUT 引脚上提供高达 20mA 的电流。这些器件具有单调性，可提供出色的线性并降低有害的代码至代码转换时的瞬态电压（毛刺脉冲）。它们使用一个运行时钟速率高达 50MHz 的多用途 3 线制串口。此接口与标准 SPI™、 QSPI™、 Microwire™，以及数字信号处理器 (DSP) 接口兼容。

DAC7568、DAC8168 和 DAC8568 包含一个上电复位电路，此电路确保 DAC 输出在零电平或中间电平时上电，并在一段有效代码被写入器件前保持此状态。这些器件包含一个由串口访问的断电特性，这将器件在电压为 5V 时的流耗减少至 0.18μA（典型值）。3V 时的功耗（包括内部基准）通常为 2.9mW，在断电模式下可降低至低于 1μW。低功耗、内部基准电压和小封装尺寸使得这些器件非常适合于便携式、电池供电类设备。

DAC7568、DAC8168 和 DAC8568 互为功能兼容型直接替代产品，可提供 TSSOP-16 和 TSSOP-14 封装。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
DAC7568 TSSOP (14) 5.00mm x 4.40mm
TSSOP (16) 5.00mm x 4.40mm
DAC8168 TSSOP (14) 5.00mm x 4.40mm
TSSOP (16) 5.00mm x 4.40mm
DAC8568 TSSOP (16) 5.00mm x 4.40mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

框图

DAC7568 DAC8168 DAC8568 fbd_bas430.gif

4 修订历史记录

Changes from E Revision (January 2014) to F Revision

  • 将数据表更新至 SDS 标准 Go
  • Added External reference current grades and updated typ values Go
  • Added Reference input impedance grades and updated typ values Go
  • Changed IDD Normal mode, internal reference switched on, AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND maximum value from 2.0mA to 2.5mAGo

Changes from D Revision (May 2012) to E Revision

  • Changed bit value in last three rows of Power-Down Commands section in from '0' to '1'Go

Changes from C Revision (February 2011) to D Revision

  • Changed Logic Input HIGH Voltage parameter test condition into two rowsGo

Changes from B Revision (November 2010) to C Revision

  • Changed Output Voltage parameter min/max values from 2.4895 and 2.5005 to 2.4975 and 2.5025, respectivelyGo
  • Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectivelyGo

Changes from A Revision (April 2009) to B Revision

  • Changed Logic Input LOW Voltage parameter maximum value from 0.8 to 0.3 × AVDDGo
  • Changed Logic Input HIGH Voltage parameter minimum value from 1.8 to 0.7 × AVDDGo
  • Updated Figure 122Go

5 Device Comparison Table

PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) MAXIMUM REFERENCE DRIFT
(ppm/°C)		 OUTPUT VOLTAGE
FULL-SCALE RANGE		 RESET TO RESOLUTION
DAC8568A ±12 ±1 25 2.5V Zero 16
DAC8568B ±12 ±1 25 2.5V Midscale 16
DAC8568C ±12 ±1 5 5V Zero 16
DAC8568D ±12 ±1 5 5V Midscale 16
DAC8168A ±4 ±0.5 25 2.5V Zero 14
DAC8168C ±4 ±0.5 5 5V Zero 14
DAC7568A ±1 ±0.25 25 2.5V Zero 12
DAC7568C ±1 ±0.25 5 5V Zero 12

6 Pin Configuration and Functions

PW PACKAGE
TSSOP-16
(TOP VIEW)
DAC7568 DAC8168 DAC8568 pin_16_bas430.gif
PW PACKAGE
TSSOP-14
(TOP VIEW)
DAC7568 DAC8168 DAC8568 pin_14_bas430.gif

Pin Functions

16-PIN 14-PIN NAME DESCRIPTION
1 — LDAC Load DACs.
2 1 SYNC Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input.
3 2 AVDD Power-supply input, 2.7V to 5.5V
4 3 VOUTA Analog output voltage from DAC A
5 4 VOUTC Analog output voltage from DAC C
6 5 VOUTE Analog output voltage from DAC E
7 6 VOUTG Analog output voltage from DAC G
8 7 VREFIN/
VREFOUT		 Positive reference input / reference output 2.5V if internal reference used.(1)
9 — CLR Asynchronous clear input.
10 8 VOUTH Analog output voltage from DAC H
11 9 VOUTF Analog output voltage from DAC F
12 10 VOUTD Analog output voltage from DAC D
13 11 VOUTB Analog output voltage from DAC B
14 12 GND Ground reference point for all circuitry on the device
15 13 DIN Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input.
16 14 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
(1) Grades A and B, external VREFIN (max) ≤ AVDD; grades C and D, external VREFIN (max) ≤ AVDD/2.

7 Specifications

 
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