DATA SHEET
UCC24612 高频同步整流器控制器
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1 特性
- 支持有源钳位反激式、QR、DCM、CCM 反激式和 LLC 等各种拓扑
- MOSFET VDS 感应高达 230V
- 工作频率高达 1MHz
- UCC24612-1 为 1MHz
- UCC24612-2 为 800kHz
- 宽 VDD 范围允许从 5V 至 28V 输出系统的直接偏置
- 具有比例栅极驱动器的 4A 灌电流、1A 拉电流栅极驱动器
- 自适应最短关闭时间，可提高抗噪能力
- 循环极限预关闭可提高 CCM 效率
- 高侧或低侧可配置
- 实现自动轻负载和睡眠模式管理，待机电流为 320µA
- 16ns 典型关闭传播延迟
- 9.5V 栅极驱动器钳位，可减少驱动损耗
2 应用
- 交流/直流适配器
- USB Type-C 和电力输送交流适配器
- 服务器和电信电源
- 交流/直流辅助电源
3 说明
UCC24612 是用于标准和逻辑电平 N 沟道 MOSFET 功率器件的高性能同步整流器控制器和驱动器。通过实施接近理想的二极管仿真，UCC24612 可减少输出整流器的损耗，并间接减少初级侧损耗。漏极到源极 (VDS) 传感控制方案允许 UCC24612 使用多个拓扑结构，例如有源钳位反激式、QR/DCM/CCM 反激式和 LLC 等。
集成 特性 可简化设计工作，使 UCC24612 在各种频率下都 应用中 ，并表现卓越。较宽的 VDD 和 VD 工作电压范围便于在输出电压高达 28V 的系统中轻松实施。通过自适应最短关闭时间可提高效率和抗噪能力。变体器件 UCC24612-1 和 UCC24612-2 具有不同的最短导通时间，以提高抗噪能力。通过比例栅极驱动器和连续导通模式 (CCM) 循环极限预关闭进一步增强了 CCM 模式下的稳健运行能力。
UCC24612 具有多个可提高效率的 特性 。具有较短传播延迟的快速比较器可减少开关损耗。9.5V 栅极驱动器钳位可降低 MOSFET 驱动损耗。频率相关待机模式可进一步降低待机功耗。这些 特性 可帮助 UCC24612 成为符合诸如美国能源部 (DoE) 第 VI 级和行为规范 (CoC) 第 2 级等严格效率标准的更大系统的一部分。
UCC24612 采用 SOT23-5 封装。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| UCC24612 | SOT23 (5) | 3.00mm x 3.00mm |
- 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
Device Images
具有高侧 SR 的反激式
具有低侧 SR 的反激式
4 修订历史记录
| 日期 | 修订版本 | 说明 |
|---|---|---|
| 2017 年 2018 | A | 第一版. |
5 Pin Configuration and Functions
5-Pin SOT-23
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| REG | 3 | O |
REG is the device bias pin. An internal linear regulator from VDD to REG generates a well regulated 9.5-V voltage. It is recommend to put a 2.2-µF bypass capacitor from REG pin to VS pin. |
| VD | 5 | I |
MOSFET drain voltage sensing input. Connect this pin to SR MOSFET drain pin. The layout should avoid sharing the VD pin trace with the power path to minimize the impact of parasitic inductance. |
| VDD | 4 | I |
Internal linear regulator input. Connect this pin to the output voltage when in low-side SR configuration. Use R-C-D circuit or other circuits to generate bias voltage from SR MOSFET drain when using high-side SR configuration, referring to Power Supply Recommendations for details. |
| VG | 1 | O |
VG (controlled MOSFET gate drive), connect VG to the gate of the controlled MOSFET through a small series resistor using short PC board tracks to achieve optimal switching performance. The VG output can achieve >1-A peak source current when High and >4-A peak sink current when Low when connected to a large N-channel power MOSFET. Due to the weak internal pull up after initial fast turn on, avoid putting a resistor less than 50 kΩ between VG to VS . |
| VS | 2 | - |
VS is the internal ground reference of the UCC24612. It is also used to sense the voltage drop across the SR MOSFET. The layout should avoid sharing the VS pin trace with the power path to minimize the impact of parasitic inductance. |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input voltage (3) | VDD | –0.3 | 30 | V |
| VD | –0.7 | 230 | V | |
| VG | –0.3 | VREG | V | |
| VD for IVD ≤ –10 mA | –1.0 | 230 | V | |
| REG | 12 | V | ||
| Output current, peak | VG(2) pulsed, tPULSE ≤ 4 ms, duty cycle ≤ 1% | ±4 | A | |
| TJ | Operating junction temperature | –40 | 125 | °C |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In normal use, VG is connected to the gate of a power MOSFET through a small resistor. When used this way, VG current is limited by the UCC24612 and no absolute maximum output current considerations are required. The series resistor shall be selected to minimize overshoot and ringing due to series inductance of the VG output and power-MOSFET gate-drive loop. Continuous VG current is subject to the maximum operating junction temperature limitation.
(3) Input voltages more negative than indicated may exist on any listed pin without excess stress or damage to the device if the pin’s input current magnitude is limited to less than -10mA.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, except pin 5 (1) | ±2,000 | V |
| Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, pin 5 (1) | ±1,500 | V | ||
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | V | ||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VVDD | VDD input voltage | 4 | 28 | V | |
| CVDD | VDD bypass capacitor | 1 | µF | ||
| CREG | REG bypass capacitor | 1.5 | 2.2 | µF | |
| TJ | Junction temperature | –40 | 125 | °C | |
| fS_MAX | Maximum switching frequency UCC24612-1 | 770 | 1000 | kHz | |
| Maximum switching frequency UCC24612-2 | 625 | 800 | |||
