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  • TPS51116 全套 DDR、DDR2、DDR3、DDR3L、LPDDR3 和 DDR4 电源解决方案同步降压控制器、3A LDO、缓冲基准

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  • TPS51116 全套 DDR、DDR2、DDR3、DDR3L、LPDDR3 和 DDR4 电源解决方案同步降压控制器、3A LDO、缓冲基准
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1. 3.1 典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Ratings
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ SMPS, Light Load Condition
      2. 7.3.2  Low-Side Driver
      3. 7.3.3  High-Side Driver
      4. 7.3.4  Current Sensing Scheme
      5. 7.3.5  PWM Frequency and Adaptive On-Time Control
      6. 7.3.6  VDDQ Output Voltage Selection
      7. 7.3.7  VTT Linear Regulator and VTTREF
      8. 7.3.8  Controling Outputs Using the S3 and S5 Pins
      9. 7.3.9  Soft-Start Function and Powergood Status
      10. 7.3.10 VDDQ and VTT Discharge Control
      11. 7.3.11 Current Protection for VDDQ
      12. 7.3.12 Current Protection for VTT
      13. 7.3.13 Overvoltage and Undervoltage Protection for VDDQ
      14. 7.3.14 Undervoltage Lockout (UVLO) Protection, V5IN (PWP), V5FILT (RGE)
      15. 7.3.15 Input Capacitor, V5IN (PWP), V5FILT (RGE)
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDDQ SMPS, Dual PWM Operation Modes
      2. 7.4.2 Current Mode Operation
      3. 7.4.3 D-CAP™ Mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 DDR3 Application With Current Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pin Connections
        2. 8.2.2.2 Choose the inductor
        3. 8.2.2.3 Choose rectifying (low-side) MOSFET
        4. 8.2.2.4 Choose output capacitance
        5. 8.2.2.5 Determine f0 and calculate RC
        6. 8.2.2.6 Calculate CC2
        7. 8.2.2.7 Calculate CC.
        8. 8.2.2.8 Determine the value of R1 and R2.
      3. 8.2.3 Application Curves
    3. 8.3 DDR3 Application With D−CAP™ Mode
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Pin Connections
        2. 8.3.2.2 Choose the Components
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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TPS51116 全套 DDR、DDR2、DDR3、DDR3L、LPDDR3 和 DDR4 电源解决方案同步降压控制器、3A LDO、缓冲基准

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 同步降压控制器 (VDDQ)
    • 宽输入电压范围: 3.0V 至 28V
    • 负载阶跃响应为 100ns 的 D−CAP™ 模式
    • 电流模式选项支持陶瓷输出电容器
    • 支持 S4/S5 状态内的软关闭
    • 利用RDS(on) 或电阻器进行电流检测
    • 2.5V (DDR)、1.8V (DDR2)，可调节至
      1.5V (DDR3)、1.35V (DDR3L)、1.2V（LPDDR3 和 DDR4）或
      输出范围 0.75V 至 3.0V
    • 配备有电源正常、过压保护和欠压保护
  • 3A LDO (VTT)，经缓冲基准 (VREF)
    • 拉电流和灌电流的能力达到 3A
    • 提供 LDO 输入以优化功率损耗
    • 只需 20μF 陶瓷输出电容器
    • 经缓冲的低噪声 10mA VREF 输出
    • 针对 VREF 和 VTT 的 ±20mV 精度
    • 在 S3 中支持高阻抗 (high-Z)，在 S4/S5 中支持软关闭
    • 热关断

2 应用

  • DDR/DDR2/DDR3/DDR3L/LPDDR3/DDR4 存储器电源
  • SSTL-2、SSTL-18、SSTL-15 和 HSTL 终端

3 说明

TPS51116 提供一个用于 DDR/SSTL-2、DDR2/SSTL-18、DDR3/SSTL-15、DDR3L、LPDDR3 和 DDR4 内存系统的完整电源。它集成了一个具有 3A 拉电流/灌电流跟踪线性稳压器和经缓冲的低噪声基准的同步降压控制器。该器件在空间受限的系统中提供最低的总解决方案成本。同步控制器运行具有自适应接通时间控制的定频 400kHz、伪恒定频率脉宽调制 (PWM)，此控制可在 D-CAP 中配置™易于使用和最快瞬态响应或者电流模式以支持陶瓷输出电容器。3A 拉电流/灌电流 LDO 只需 20μF (2 × 10μF) 陶瓷输出电容器即可保持快速瞬态响应。此外，LDO 电源输入是外部可用的，这样可大大减少总体功耗。该器件支持所有睡眠状态控制，此类控制在 S3（挂起到 RAM）中将 VTT 置于 high-Z 状态并且在 S4/S5（挂起到硬盘）中将 VDDQ、VTT 和 VTTREF（软关闭）放电。该器件还具有全部保护 特性， 包括热关断保护，并且提供 20 引脚 HTSSOP PowerPAD™封装和 24 引脚 4 × 4 QFN 封装。

Device Images

3.1 典型应用

TPS51116 simp_app_slus609.gif

4 修订历史记录

Changes from I Revision (March 2012) to J Revision

  • Added 引脚配置和功能部分、ESD 额定值表、特性 说明部分、器件功能模式、应用和实施部分、电源建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分Go
  • Added 整个数据表的 DDR4 工作模式说明和规格Go
  • Clarified graphs in Typical Characteristics sectionGo

Changes from H Revision (July 2009) to I Revision

  • Added 向 特性 部分添加了澄清说明Go
  • Added 将“SSTL-15”添加到了 应用 部分Go
  • Added “LPDDR3”添加到标题和说明部分Go
  • Added references to "LPDDR3 " to the Detailed Description sectionGo
  • Added clarity to Figure 34Go

5 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP
Top View
TPS51116 pinout_pwp20_slus609.gif
RGE Package
24-Pin QFN
Top View
TPS51116 pinout_rge24_slus609.gif

Pin Functions

NAME NO. I/O DESCRIPTION
PWP RGE
COMP 8 6 I/O Output of the transconductance amplifier for phase compensation. Connect to V5IN pin to disable gM amplifier and use D-CAP mode.
CS 15 16 I/O Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip voltage setting input for RDS(on) current sense scheme if connected to V5IN (PWP), V5FILT (RGE) through the voltage setting resistor.
DRVH 19 21 O Switching (high-side) MOSFET gate-drive output.
DRVL 17 19 O Rectifying (low-side) MOSFET gate-drive output.
GND 5 3 - Signal ground. Connect to negative terminal of the VTT LDO output capacitor.
CS_GND - 17 – Current sense comparator input (+) and ground for powergood circuit.
LL 18 20 I/O Switching (high-side) MOSFET gate driver return. Current sense comparator input (-) for RDS(on) current sense.
MODE 6 4 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section.
NC – 7 – No connect.
– 12 –
PGND 16 18 – Ground for rectifying (low-side) MOSFET gate driver (PWP, RGE). Also current sense comparator input(+) and ground for powergood circuit (PWP).
PGOOD 13 13 O Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the target range.
S3 11 10 I S3 signal input.
S5 12 11 I S5 signal input.
V5IN 14 15 I 5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).
V5FILT – 14 I Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to V5FILT.
VBST 20 22 I/O Switching (high-side) MOSFET driver bootstrap voltage input.
VDDQSET 10 9 I VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.
VDDQSNS 9 8 I/O VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to V5IN or GND.
VLDOIN 1 23 I Power supply for the VTT LDO.
VTT 2 24 O Power output for the VTT LDO.
VTTGND 3 1 - Power ground output for the VTT LDO.
VTTREF 7 5 O VTTREF buffered reference output.
VTTSNS 4 2 I Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Input voltage range VBST –0.3 36 V
VBST wrt LL –0.3 6
CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET, V5FILT –0.3 6
PGND, VTTGND, CS_GND –0.3 0.3
VOUT Output voltage range DRVH –1.0 36 V
LL –1.0 30
COMP, DRVL, PGOOD, VTT, VTTREF –0.3 6
TA Operating ambient temperature range –40 85 °C
Tstg Storage temperature –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, V5IN, V5FILT 4.75 5.25 V
Voltage range VBST, DRVH –0.1 34 V
LL –0.6 28
VLDOIN, VTT, VTTSNS, VDDQSNS –0.1 3.6
VTTREF –0.1 1.8
PGND, VTTGND, CS_GND –0.1 0.1
S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, DRVL –0.1 5.25
Operating free-air temperature, TA –40 85 °C

6.4 Dissipation Ratings

PACKAGE TA< 25°C POWER RATING
(W) 		DERATING FACTOR ABOVE
TA = 25°C
(mW/°C)		 TA = 85°C POWER RATING
(W)
20-pin PWP 2.53 25.3 1.01
24-pin RGE 2.20 22.0 0.88

6.5 Thermal Information

THERMAL METRIC(1) TPS51116 UNIT
PWP
HTSSOP		 RGE
QFN
20 24
RθJA Junction-to-ambient thermal resistance 41.2 35.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.4 41.1 °C/W
RθJB Junction-to-board thermal resistance 23.9 12.9 °C/W
ψJT Junction-to-top characterization parameter 1.1 07 °C/W
ψJB Junction-to-board characterization parameter 23.7 12.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 3.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IV5IN1 Supply current 1, V5IN(1) TA = 25°C, No load, VS3 = VS5 = 5 V,
COMP connected to capacitor		 0.8 2 mA
IV5IN2 Supply current 2, V5IN(1) TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
COMP connected to capacitor		 300 600 μA
IV5IN3 Supply current 3, V5IN(1) TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V 240 500
IV5INSDN Shutdown current, V5IN(1) TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0
IVLDOIN1 Supply current 1, VLDOIN TA = 25°C, No load, VS3 = VS5 = 5 V 1 10
IVLDOIN2 Supply current 2, VLDOIN TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V, 0.1 10
IVLDOINSDN Standby current, VLDOIN TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0
VTTREF OUTPUT
VVTTREF Output voltage, VTTREF VVDDQSNS/2 V
VVTTREFTOL Output voltage tolerance –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 2.5 V, Tolerance to VVDDQSNS/2		 –20 20 mV
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.8 V, Tolerance to VVDDQSNS/2		 –18 18
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.5 V, Tolerance to VVDDQSNS/2		 –15 15
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.2 V, Tolerance to VVDDQSNS/2		 –12 12
VVTTREFSRC Source current VVDDQSNS = 2.5 V, VVTTREF = 0 V –20 –40 –80 mA
VVTTREFSNK Sink current VVDDQSNS = 2.5 V, VVTTREF = 2.5 V 20 40 80
VDDQ OUTPUT
VVDDQ Output voltage, VDDQ TA = 25°C, VVDDQSET = 0 V, No load 2.465 2.500 2.535 V
0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load(2) 2.457 2.500 2.543
–40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2) 2.440 2.500 2.550
TA = 25°C, VVDDQSET = 5 V, No load (2) 1.776 1.800 1.824
0°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.769 1.800 1.831
–40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.764 1.800 1.836
–40°C ≤ TA ≤ 85°C, Adjustable mode, No load(2) 0.75 3.0
VVDDQSET VDDQSET regulation voltage TA = 25°C, Adjustable mode 742.5 750.0 757.5 mV
0°C ≤ TA ≤ 85°C, Adjustable mode 740.2 750.0 759.8
–40°C ≤ TA ≤ 85°C, Adjustable mode 738.0 750.0 762.0
RVDDQSNS Input impedance, VDDQSNS VVDDQSET = 0 V 215 kΩ
VVDDQSET = 5 V 180
Adjustable mode 460
IVDDQSET Input current, VDDQSET VVDDQSET = 0.78 V, COMP = Open –0.04 μA
VVDDQSET = 0.78 V, COMP = 5 V –0.06
IVDDQDisch Discharge current, VDDQ VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0 V		 10 40 mA
IVLDOINDisch Discharge current, VLDOIN VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0.5 V		 700 mA
VTT OUTPUT
VVTTSNS Output voltage, VTT VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V 1.25 V
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V 0.9
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V 0.75
VVTTTOL25 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A –30 30
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 3 A –40 40
VVTTTOL18 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 2 A –40 40
VVTTTOL15 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 2 A –40 40
VVTTTOL12 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A –40 40
IVTTOCLSRC Source current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI 3.0 3.8 6.0 A
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V 1.5 2.2 3.0
IVTTOCLSNK Sink current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI 3.0 3.6 6.0
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ 1.5 2.2 3.0
IVTTLK Leakage current, VTT VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 –10 10 μA
IVTTBIAS Input bias current, VTTSNS VS3 = 5 V, VVTTSNS = VVDDQSNS /2 –1 –0.1 1
IVTTSNSLK Leakage current, VTTSNS VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 –1 1
IVTTDisch Discharge current, VTT TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
VVTT = 0.5 V		 10 17 mA
TRANSCONDUCTANCE AMPLIFIER
gm Gain TA = 25°C 240 300 360 μS
ICOMPSNK COMP maximum sink current VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCOMP = 1.28 V 13 μA
ICOMPSRC COMP maximum source
current		 VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCOMP = 1.28 V –13
VCOMPHI COMP high clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V 1.31 1.34 1.37 V
VCOMPLO COMP low clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V 1.18 1.21 1.24
DUTY CONTROL
tON Operating on-time VIN = 12 V, VVDDQSET = 0 V 520 ns
tON0 Startup on-time VIN = 12 V, VVDDQSNS = 0 V 125
tON(min) Minimum on-time TA = 25°C(2) 100
tOFF(min) Minimum off-time TA = 25°C(2) 350
ZERO CURRENT COMPARATOR
VZC Zero current comparator offset –6 0 6 mV
OUTPUT DRIVERS
RDRVH DRVH resistance Source, IDRVH = –100 mA 3 6 Ω
Sink, IDRVH = 100 mA 0.9 3
RDRVL DRVL resistance Source, IDRVL = –100 mA 3 6
Sink, IDRVL = 100 mA 0.9 3
tD Dead time LL-low to DRVL-on(2) 10 ns
DRVL-off to DRVH-on(2) 20
INTERNAL BST DIODE
VFBST Forward voltage VV5IN-VBST , IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,
TA = 25°C		 0.1 1.0 μA
PROTECTIONS
VOCL Current limit threshold VPGND-CS , PGOOD = HI, VCS< 0.5 V 50 60 70 mV
VPGND-CS , PGOOD = LO, VCS< 0.5 V 20 30 40
ITRIP Current sense sink current TA = 25°C, VCS> 4.5 V, PGOOD = HI 9 10 11 μA
TA = 25°C, VCS> 4.5 V, PGOOD = LO 4 5 6
TCITRIP TRIP current temperature
coefficient		 RDS(on) sense scheme, On the basis
of TA = 25°C(2) 		4500 ppm/°C
VOCL(off) Overcurrent protection COMP offset (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
VCS> 4.5 V (2) 		–5 0 5 mV
VR(trip) Current limit threshold setting range VV5IN-CS(2)(1) 30 150
POWERGOOD COMPARATOR
VTVDDQPG VDDQ powergood threshold PG in from lower 92.5% 95.0% 97.5%
PG in from higher 102.5% 105.0% 107.5%
PG hysteresis 5%
IPG(max) PGOOD sink current VVTT = 0 V, VPGOOD = 0.5 V 2.5 7.5 mA
tPG(del) PGOOD delay time Delay for PG in 80 130 200 μs
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD
VUVV5IN V5IN UVLO threshold
voltage		 Wake up 3.7 4.0 4.3 V
Hysteresis 0.2 0.3 0.4
VTHMODE MODE threshold No discharge 4.7
Non-tracking discharge 0.1
VTHVDDQSET VDDQSET threshold voltage 2.5 V output 0.08 0.15 0.25
1.8 V output 3.5 4.0 4.5
VIH High-level input voltage S3, S5 2.2
VIL Low-level input voltage S3, S5 0.3
VIHYST Hysteresis voltage S3, S5 0.2
VINLEAK Logic input leakage current S3, S5, MODE –1 1 μA
VINVDDQSET Input leakage/ bias current VDDQSET –1 1
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP VDDQ OVP trip threshold voltage OVP detect 110% 115% 120%
Hysteresis 5%
tOVPDEL VDDQ OVP propagation
delay (2) 		1.5 μs
VUVP Output UVP trip threshold UVP detect 70%
Hysteresis 10%
tUVPDEL Output UVP propagation delay(2) 32 cycle
tUVPEN Output UVP enable delay(2) 1007
THERMAL SHUTDOWN
TSDN Thermal SDN threshold (2) Shutdown temperature 160 °C
Hysteresis 10
(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
(2) Specified by design. Not production tested.

6.7 Typical Characteristics

All data in the following graphs are measured from the PWP packaged device.
TPS51116 D024_SLUS609.gif
Figure 1. V5IN Supply Current vs Junction Temperature
TPS51116 D023_SLUS609.gif
DDR2 VVTT = 0.3 V
Figure 3. V5IN Supply Current vs VTT Current
TPS51116 icsvst_lus609.gif
Figure 5. CS Current vs Junction Temperature
TPS51116 idschavst_lus609.gif
Figure 7. VTT Discharge Current vs Junction Temperature
TPS51116 fswvsvin_slus609.gif
DCAP Mode IVDDQ = 7 A
Figure 9. Switching Frequency vs Input Voltage
TPS51116 vvddqvsivddq_slus609.gif
DDR VIN = 12 V
DCAP Mode
Figure 11. VDDQ Load Regulation
TPS51116 vvttvsivtta_slus609.gif
DDR
Figure 13. VTT Load Regulation
TPS51116 D012_SLUS609.gif
DDR3 VVLDOIN = 1. 5 V
Figure 15. VTT Load Regulation
TPS51116 D021_SLUS609.gif
DDR D021
Figure 17. VTTREF Load Regulation
TPS51116 D011_SLUS609.gif
DDR3
Figure 19. VTTREF Load Regulation
TPS51116 D026_SLUS609.gif
DDR VVDDQ = 2.5 V
fSW = 400 kHz
Figure 21. VDDQ Efficiency vs VDDQ Current
TPS51116 ripple_lus609.gif
Heavy Load
Figure 23. Ripple Waveforms
TPS51116 vttload_lus609.gif
Figure 25. VTT Load Transient Response
TPS51116 sswtrack_lus609.gif
Figure 27. Soft-Start Waveforms Tracking Discharge
TPS51116 vddqbode_lus609.gif
Current mode
Figure 29. VDDQ Bode Plot
TPS51116 bodesink_lus609.gif
DDR2 Sink
Figure 31. VTT Bode Plot
TPS51116 D025_SLUS609.gif
Figure 2. V5IN Shutdown Current vs Junction Temperature
TPS51116 D028_SLUS609.gif
Figure 4. VLDOIN Supply Current vs Junction Temperature
TPS51116 idschbvst_lus609.gif
Figure 6. VDDQ Discharge Current vs Junction Temperature
TPS51116 ouvptripvt_lus609.gif
Figure 8. Overvoltage and Undervoltage Threshold vs Junction Temperature
TPS51116 fswvsivddq_slus609.gif
DCAP Mode VIN =12 V
Figure 10. Switching Frequency vs IVDDQ Output Current
TPS51116 vvddqvsvin_slus609.gif
DDR2 DCAP Mode
Figure 12. VDDQ Line Regulation
TPS51116 vvttvsivttb_slus609.gif
DDR2
Figure 14. VTT Load Regulation
TPS51116 D002_SLUS609.gif
DDR4
Figure 16. VTTREF Output Voltage vs Output Current
TPS51116 D022_SLUS609.gif
DDR2
Figure 18. VTTREF Load Regulation
TPS51116 D003_SLUS609.gif
DDR4
Figure 20. VTTREF Load Regulation
TPS51116 D027_SLUS609.gif
DDR2 VVDDQ = 1.8 V
fSW = 400 kHz
Figure 22. VDDQ Efficiency vs VDDQ Current
TPS51116 transient_lus609.gif
Figure 24. VDDQ Load Transient Response
TPS51116 startup_lus609.gif
Figure 26. VDDQ, VTT, and VTTREF Start-Up Waveforms
TPS51116 sswotrack_lus609.gif
Figure 28. Soft-Stop Waveforms Non-Tracking Discharge
TPS51116 bodesource_lus609.gif
DDR2 Source
Figure 30. VTT Bode Plot

7 Detailed Description

7.1 Overview

 
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