本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。
ADS1013、ADS1014 和 ADS1015 (ADS101x) 是采用、无引线 X2QFN-10、SOT-10 和 VSSOP-10 封装,兼容 I2C 的 12 位低功耗精密模数转换器 (ADC)。ADS101x 采用了低漂移电压基准和振荡器。ADS1014 和 ADS1015 还包含一个可编程增益放大器 (PGA) 和一个数字比较器。除了这些特性,这些器件还具有宽工作电源电压范围,因而非常适用于功率受限型和空间受限型传感器测量应用。
ADS101x 可在数据速率高达 33008 个样本/秒 (SPS) 的情况下执行转换。PGA 可提供从 ±256mV 到 ±6.144V 的输入范围,从而实现精准的大小信号测量。ADS1015 具有一个输入多路复用器 (MUX),可实现双路差分输入或四路单端输入测量。在 ADS1014 和 ADS1015 中使用数字比较器可进行欠压和过压检测。
器件型号 | 封装(1) | 封装尺寸(2) |
---|---|---|
ADS101x | RUG(X2QFN,10) | 1.5mm × 2mm |
DYN(SOT,10) | 2.9mm × 2.8mm | |
DGS(VSSOP,10) | 3mm × 4.9mm |
器件型号 | 输入通道 | 特性(1) |
---|---|---|
ADS1013 | 1 个差分(1 个单端) | — |
ADS1014 | 1 个差分(1 个单端) | PGA、比较器 |
ADS1015 | 2 个差分(4 个单端) | PGA、比较器 |
DEVICE | RESOLUTION (Bits) |
MAXIMUM
SAMPLE RATE (SPS) |
INPUT
CHANNELS Differential (Single-Ended) |
PGA | INTERFACE | SPECIAL FEATURES |
---|---|---|---|---|---|---|
ADS1015 | 12 | 3300 | 2 (4) | Yes | I2C | Comparator |
ADS1014 | 12 | 3300 | 1 (1) | Yes | I2C | Comparator |
ADS1013 | 12 | 3300 | 1 (1) | No | I2C | None |
ADS1115 | 16 | 860 | 2 (4) | Yes | I2C | Comparator |
ADS1114 | 16 | 860 | 1 (1) | Yes | I2C | Comparator |
ADS1113 | 16 | 860 | 1(1) | No | I2C | None |
ADS1018 | 12 | 3300 | 2 (4) | Yes | SPI | Temperature sensor |
ADS1118 | 16 | 860 | 2 (4) | Yes | SPI | Temperature sensor |
PIN | TYPE | DESCRIPTION(1) | |||
---|---|---|---|---|---|
NAME | ADS1013 | ADS1014 | ADS1015 | ||
ADDR | 1 | 1 | 1 | Digital input | I2C target address select |
AIN0 | 4 | 4 | 4 | Analog input | Analog input 0 |
AIN1 | 5 | 5 | 5 | Analog input | Analog input 1 |
AIN2 | — | — | 6 | Analog input | Analog input 2 (ADS1015 only) |
AIN3 | — | — | 7 | Analog input | Analog input 3 (ADS1015 only) |
ALERT/RDY | — | 2 | 2 | Digital output | Comparator output or conversion ready (ADS1014 and ADS1015 only) Open-drain output. Connect to VDD using a pullup resistor. |
GND | 3 | 3 | 3 | Analog | Ground |
NC | 2, 6, 7 | 6, 7 | — | — | No connect. Leave pin floating or connect to GND. |
SCL | 10 | 10 | 10 | Digital input | Serial clock input. Connect to VDD using a pullup resistor. |
SDA | 9 | 9 | 9 | Digital I/O | Serial data input and output. Connect to VDD using a pullup resistor. |
VDD | 8 | 8 | 8 | Analog | Power supply. Connect a 0.1μF, power-supply decoupling capacitor to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | VDD to GND | –0.3 | 7 | V |
Analog input voltage | AIN0, AIN1, AIN2, AIN3 | GND – 0.3 | VDD + 0.3 | V |
Digital input voltage | SDA, SCL, ADDR, ALERT/RDY | GND – 0.3 | 5.5 | V |
Input current, continuous | Any pin except power supply pins | –10 | 10 | mA |
Temperature | Operating ambient, TA | –40 | 125 | °C |
Junction, TJ | –40 | 150 | ||
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Power supply (VDD to GND) | 2 | 5.5 | V | |||
ANALOG INPUTS(1) | ||||||
FSR | Full-scale input voltage range(2) (VIN = V(AINP) – V(AINN)) | ±0.256 | ±6.144 | V | ||
V(AINx) | Absolute input voltage | GND | VDD | V | ||
DIGITAL INPUTS | ||||||
VDIG | Digital input voltage | GND | 5.5 | V | ||
TEMPERATURE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | RUG (X2QFN) | DYN (SOT) | DGS (VSSOP) | UNIT | |
---|---|---|---|---|---|
10 PINS | 10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 245.2 | 147.1 | 182.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 69.3 | 59.3 | 67.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 172.0 | 71.3 | 103.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 8.2 | 2.8 | 10.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 170.8 | 70.4 | 102.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG INPUT | |||||||
Common-mode input impedance | FSR = ±6.144V(1) | 10 | MΩ | ||||
FSR = ±4.096V(1), FSR = ±2.048V | 6 | ||||||
FSR = ±1.024V | 3 | ||||||
FSR = ±0.512V, FSR = ±0.256V | 100 | ||||||
Differential input impedance | FSR = ±6.144V(1) | 22 | MΩ | ||||
FSR = ±4.096V(1) | 15 | ||||||
FSR = ±2.048V | 4.9 | ||||||
FSR = ±1.024V | 2.4 | ||||||
FSR = ±0.512V, ±0.256V | 710 | kΩ | |||||
SYSTEM PERFORMANCE | |||||||
Resolution (no missing codes) | 12 | Bits | |||||
DR | Data rate | 128, 250, 490, 920, 1600, 2400, 3300 | SPS | ||||
Data rate variation | All data rates | –10% | 10% | ||||
INL | Integral nonlinearity | DR = 128SPS, FSR = ±2.048V(2) | 0.5 | LSB | |||
Offset error | FSR = ±2.048V, differential inputs | -0.5 | 0 | 0.5 | LSB | ||
FSR = ±2.048V, single-ended inputs | ±0.25 | ||||||
Offset drift over temperature | FSR = ±2.048V | 0.005 | LSB/°C | ||||
Long-term offset drift | FSR = ±2.048V, TA = 125°C, 1000 hrs | ±1 | LSB | ||||
Offset channel match | Match between any two inputs | 0.25 | LSB | ||||
Gain error(3) | FSR = ±2.048V, TA = 25°C | 0.05% | 0.25% | ||||
Gain drift over temperature(3) | FSR = ±0.256V | 7 | ppm/°C | ||||
FSR = ±2.048V | 5 | 40 | |||||
FSR = ±6.144V(1) | 5 | ||||||
Long-term gain drift | FSR = ±2.048V, TA = 125°C, 1000 hrs | ±0.05 | % | ||||
Gain match(3) | Match between any two gains | 0.02% | 0.1% | ||||
Gain channel match | Match between any two inputs | 0.05% | 0.1% | ||||
DIGITAL INPUT/OUTPUT | |||||||
VIH | High-level input voltage | 0.7 VDD | 5.5 | V | |||
VIL | Low-level input voltage | GND | 0.3 VDD | V | |||
VOL | Low-level output voltage | IOL = 3mA | GND | 0.15 | 0.4 | V | |
Input leakage current | GND < VDIG < VDD | –10 | 10 | μA | |||
POWER-SUPPLY | |||||||
IVDD | Supply current | Power-down | TA = 25°C | 0.5 | 2 | μA | |
5 | |||||||
Operating | TA = 25°C | 150 | 200 | ||||
300 | |||||||
PD | Power dissipation | VDD = 5.0V | 0.9 | mW | |||
VDD = 3.3V | 0.5 | ||||||
VDD = 2.0V | 0.3 |
FAST MODE | HIGH-SPEED MODE | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
fSCL | SCL clock frequency | 0.01 | 0.4 | 0.01 | 3.4 | MHz |
tBUF | Bus free time between START and STOP condition | 600 | 160 | ns | ||
tHDSTA | Hold time
after repeated START condition. After this period, the first clock is generated. |
600 | 160 | ns | ||
tSUSTA | Setup time for a repeated START condition | 600 | 160 | ns | ||
tSUSTO | Setup time for STOP condition | 600 | 160 | ns | ||
tHDDAT | Data hold time | 0 | 0 | ns | ||
tSUDAT | Data setup time | 100 | 10 | ns | ||
tLOW | Low period of the SCL clock pin | 1300 | 160 | ns | ||
tHIGH | High period for the SCL clock pin | 600 | 60 | ns | ||
tF | Fall time for both SDA and SCL signals(1) | 300 | 160 | ns | ||
tR | Rise time for both SDA and SCL signals(1) | 300 | 160 | ns |