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  • TPS4030x 3V 至 20V 输入、电压模式、同步降压控制器

    • ZHCSHA3D NOVEMBER   2009  – March 2018 TPS40303 , TPS40304 , TPS40305

      PRODUCTION DATA.  

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  • TPS4030x 3V 至 20V 输入、电压模式、同步降压控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Reference
      2. 7.3.2 Enable Functionality, Start-Up Sequence and Timing
      3. 7.3.3 Soft-Start Time
      4. 7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Drivers
      7. 7.3.7 Prebias Start-Up
      8. 7.3.8 Power Good
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 UVLO
        2. 7.4.1.2 Disable
        3. 7.4.1.3 Calibration
        4. 7.4.1.4 Converting
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Inductor Selection (L1)
          4. 8.2.1.2.4  Output Capacitor Selection (C12)
          5. 8.2.1.2.5  Peak Current Rating of Inductor
          6. 8.2.1.2.6  Input Capacitor Selection (C8)
          7. 8.2.1.2.7  MOSFET Switch Selection (Q1 and Q2)
          8. 8.2.1.2.8  Bootstrap Capacitor (C6)
          9. 8.2.1.2.9  VDD Bypass Capacitor (C7)
          10. 8.2.1.2.10 BP Bypass Capacitor (C5)
          11. 8.2.1.2.11 Short-Circuit Protection (R11)
          12. 8.2.1.2.12 Feedback Divider (R4, R5)
          13. 8.2.1.2.13 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 A High-Current, Low-Voltage Design Using the TPS40304
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency
          2. 8.2.2.2.2  Inductor Selection (L1)
          3. 8.2.2.2.3  Output Capacitor Selection (C12)
          4. 8.2.2.2.4  Peak Current Rating of Inductor
          5. 8.2.2.2.5  Input Capacitor Selection (C8)
          6. 8.2.2.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.2.2.7  Bootstrap Capacitor (C6)
          8. 8.2.2.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.2.2.9  BP Bypass Capacitor (C5)
          10. 8.2.2.2.10 Short-Circuit Protection (R11)
          11. 8.2.2.2.11 Feedback Divider (R4, R5)
          12. 8.2.2.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.2.3 Application Curves
      3. 8.2.3 A Synchronous Buck Application Using the TPS40303
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1  Selecting the Switching Frequency
          2. 8.2.3.2.2  Inductor Selection (L1)
          3. 8.2.3.2.3  Output Capacitor Selection (C12)
          4. 8.2.3.2.4  Peak Current Rating of Inductor
          5. 8.2.3.2.5  Input Capacitor Selection (C8)
          6. 8.2.3.2.6  MOSFET Switch Selection (Q1 and Q2)
          7. 8.2.3.2.7  Bootstrap Capacitor (C6)
          8. 8.2.3.2.8  VDD Bypass Capacitor (C7)
          9. 8.2.3.2.9  BP Bypass Capacitor (C5)
          10. 8.2.3.2.10 Short-Circuit Protection (R11)
          11. 8.2.3.2.11 Feedback Divider (R4, R5)
          12. 8.2.3.2.12 Compensation: (C2, C3, C4, R3, R6)
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 使用 WEBENCH® 工具创建定制设计
    3. 11.3 文档支持
      1. 11.3.1 相关文档
    4. 11.4 相关链接
    5. 11.5 接收文档更新通知
    6. 11.6 社区资源
    7. 11.7 商标
    8. 11.8 静电放电警告
    9. 11.9 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS4030x 3V 至 20V 输入、电压模式、同步降压控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 输入电压范围为 3V 至 20V
  • 300kHz (TPS40303)、600kHz (TPS40304) 和 1.2MHz (TPS40305) 开关频率
  • 高侧和低侧 FET RDS(on) 电流检测
  • 可编程热补偿 OCP 电平
  • 可编程软启动
  • 600mV、1% 基准电压
  • 电压前馈补偿
  • 支持预偏置输出
  • 扩频频谱
  • 145°C 的热关断保护限制
  • 10 引脚 3mm × 3mm VSON 封装，散热垫具有接地连接
  • 使用 TPS4030x 并借助 WEBENCH® Power Designer 创建定制设计方案

2 应用

  • 负载点 (POL) 模块
  • 打印机
  • 数字电视
  • 电信
  • USB Type-C 墙壁插座

3 说明

TPS4030x 是成本优化的同步降压控制器系列产品，可在 3V 至 20V 输入电压下运行。此控制器实现了一种电压模式控制架构，具有输入电压前馈补偿功能，可对输入电压变化做出即时响应。固定开关频率为 300KHz、600KHz 或1.2MHz。

在开关频率部分添加了扩频频谱 (FSS) 特性，显著降低了峰值 EMI 噪声，使其更容易符合 EMI 标准。

TPS4030x 具有多种用户可编程功能，包括软启动、过流保护 (OCP) 电平以及环路补偿。

OCP 电平可以通过从 LDRV 引脚连接到电路接地的单个外部电阻器进行编程。在初始通电过程中，TPS4030x 将进入校准环节，测量 LDRV 引脚电压，并设置内部 OCP 电压电平。在工作期间，器件可在通电时通过将已编程 OCP 电压电平与低侧 FET 上的压降进行比较来确定是否发生过流情况。之后，TPS4030x 会进入关断和重启周期，直到故障消除为止。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS40303 VSON (10) 3.00mm × 3.00mm
TPS40304
TPS40305
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化应用示意图

TPS40303 TPS40304 TPS40305 v09158_lus964.gif

4 修订历史记录

Changes from C Revision (January 2018) to D Revision

  • Changed 更改了 SEO 的数据表标题Go
  • Added 将“USB Type-C 墙壁插座”添加到应用；添加了 WEBENCH 链接Go
  • Deleted redundant Dissipation Ratings table Go

Changes from B Revision (May 2015) to C Revision

  • Added 在 TPS40303 TI 设计中添加了顶部导航图标Go
  • Deleted 从器件和文档支持 中删除了相关器件表Go

Changes from A Revision (August 2012) to B Revision

  • Added 添加了引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from * Revision (November 2009) to A Revision

  • Changed minimum controllable pulse width max value from 100 to 70Go

5 Pin Configuration and Functions

DRC Package
10-Pins VSON
Top View
TPS40303 TPS40304 TPS40305 pinout_lus964.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 6 I Gate drive voltage for the high-side N-channel MOSFET. A 0.1-µF capacitor (typical) must be connected between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is recommended to maximize the gate drive voltage for the high-side.
BP 10 O Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from this pin to GND.
COMP 4 O Output of the error amplifier and connection node for loop feedback components.
EN/SS 2 I Logic level input which starts or stops the controller via an external user command. Letting this pin float turns the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-kΩ resistor from this pin to BP enables the FSS feature.
FB 5 I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage.
HDRV 7 O Bootstrapped gate drive output for the high-side N-channel MOSFET.
LDRV/OC 9 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the resistor during initial calibration and that sets up the voltage trip point used for OCP.
PGOOD 3 O Open-drain power good output.
SW 8 O Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-side FET driver.
VDD 1 I Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1-µF close to the device.
GND Thermal Pad — Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This connection serves a twofold purpose. The first is to provide an electrical ground connection for the device. The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.

6 Specifications

 
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