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  • LMK61E07 具有内部 EEPROM 的超低抖动可编程振荡器

    • ZHCSH74B december   2017  – august 2023 LMK61E07

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  • LMK61E07 具有内部 EEPROM 的超低抖动可编程振荡器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  Frequency Tolerance Characteristics
    10. 6.10 Frequency Margining Characteristics
    11. 6.11 Power-On Reset Characteristics (VDD)
    12. 6.12 I2C-Compatible Interface Characteristics (SDA, SCL)
    13. 6.13 PSRR Characteristics
    14. 6.14 Other Characteristics
    15. 6.15 PLL Clock Output Jitter Characteristics
    16. 6.16 Typical 156.25-MHz Output Phase Noise Characteristics
    17. 6.17 Typical 161.1328125 MHz Output Phase Noise Characteristics
    18. 6.18 Additional Reliability and Qualification
    19. 6.19 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Divider and Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Engine
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
      2. 8.4.2 DCXO Mode and Frequency Margining
        1. 8.4.2.1 DCXO Mode
        2. 8.4.2.2 Fine Frequency Margining
        3. 8.4.2.3 Coarse Frequency Margining
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  VNDRID_BY1 Register; R0
        2. 8.6.1.2  VNDRID_BY0 Register; R1
        3. 8.6.1.3  PRODID Register; R2
        4. 8.6.1.4  REVID Register; R3
        5. 8.6.1.5  TARGETADR Register; R8
        6. 8.6.1.6  EEREV Register; R9
        7. 8.6.1.7  DEV_CTL Register; R10
        8. 8.6.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.6.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.6.1.10 DIFFCTL Register; R21
        11. 8.6.1.11 OUTDIV_BY1 Register; R22
        12. 8.6.1.12 OUTDIV_BY0 Register; R23
        13. 8.6.1.13 RDIVCMOSCTL Register; R24
        14. 8.6.1.14 PLL_NDIV_BY1 Register; R25
        15. 8.6.1.15 PLL_NDIV_BY0 Register; R26
        16. 8.6.1.16 PLL_FRACNUM_BY2 Register; R27
        17. 8.6.1.17 PLL_FRACNUM_BY1 Register; R28
        18. 8.6.1.18 PLL_FRACNUM_BY0 Register; R29
        19. 8.6.1.19 PLL_FRACDEN_BY2 Register; R30
        20. 8.6.1.20 PLL_FRACDEN_BY1 Register; R31
        21. 8.6.1.21 PLL_FRACDEN_BY0 Register; R32
        22. 8.6.1.22 PLL_MASHCTRL Register; R33
        23. 8.6.1.23 PLL_CTRL0 Register; R34
        24. 8.6.1.24 PLL_CTRL1 Register; R35
        25. 8.6.1.25 PLL_LF_R2 Register; R36
        26. 8.6.1.26 PLL_LF_C1 Register; R37
        27. 8.6.1.27 PLL_LF_R3 Register; R38
        28. 8.6.1.28 PLL_LF_C3 Register; R39
        29. 8.6.1.29 PLL_CALCTRL Register; R42
        30. 8.6.1.30 NVMSCRC Register; R47
        31. 8.6.1.31 NVMCNT Register; R48
        32. 8.6.1.32 NVMCTL Register; R49
        33. 8.6.1.33 NVMLCRC Register; R50
        34. 8.6.1.34 MEMADR Register; R51
        35. 8.6.1.35 NVMDAT Register; R52
        36. 8.6.1.36 RAMDAT Register; R53
        37. 8.6.1.37 NVMUNLK Register; R56
        38. 8.6.1.38 INT_LIVE Register; R66
        39. 8.6.1.39 SWRST Register; R72
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PLL Loop Filter Design
        2. 9.2.2.2 Spur Mitigation Techniques
          1. 9.2.2.2.1 Phase Detection Spur
          2. 9.2.2.2.2 Integer Boundary Fractional Spur
          3. 9.2.2.2.3 Primary Fractional Spur
          4. 9.2.2.2.4 Sub-Fractional Spur
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Ensured Thermal Reliability
        2. 9.4.1.2 Best Practices for Signal Integrity
        3. 9.4.1.3 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
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Data Sheet

LMK61E07 具有内部 EEPROM 的超低抖动可编程振荡器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 超低噪声、高性能
    • 抖动：90fs RMS（LMK61E07 上 fOUT > 100MHz 时的典型值）
    • PSRR：-70dBc，LMK61E07 具有强大的抗电源噪声能力
  • LMK61E07 具有灵活的输出格式
    • LVPECL 高达 1 GHz
    • LVDS 高达 900 MHz
    • HSTL 高达 400 MHz
  • 总频率容差：±25 ppm
  • 系统级特性
    • 无毛刺频率裕量：与标称值相差高达 ±1000ppm
    • 内部 EEPROM：用户可配置的启动设置
  • 其他特性
    • 器件控制：快速模式 I2C 高达 1000kHz
    • 3.3V 工作电压
    • 工业温度范围（–40°C 至 +85°C）
    • 7mm × 5mm 6 引脚封装
  • 默认频率：
    • 70.656MHz

2 应用

  • 晶体振荡器、SAW 振荡器或芯片振荡器的高性能替代产品
  • 开关、路由器、网卡、基带装置 (BBU)、服务器、存储/SAN
  • 测试和测量
  • 医疗成像
  • FPGA，处理器连接
  • xDSL，广播视频

3 说明

LMK61E07 系列超低抖动 PLLatinum™ 可编程振荡器使用分数 N 频率合成器与集成 VCO 来生成常用的参考时钟。LMK61E07 的输出可配置为 LVPECL、LVDS 或 HCSL。该器件可从片上 EEPROM 自启动，以便生成出厂编程的默认输出频率，或者可通过 I2C 串行接口在系统中对器件寄存器和 EEPROM 设置进行完全编程。该器件通过 I2C 串行接口提供精细和粗糙的频率裕量控制，因此是一种数控振荡器 (DCXO)。

您可以更新 PLL 反馈分频器，从而使用 12.5MHz 的 PFD（R 分频器=4，禁用倍频器）以小于 1ppb 的步进值进行无峰值或毛刺的输出频率调节以符合 xDSL 要求，或使用 100MHz 的 PFD（R 分频器=1，启用倍频器）以小于 5.2ppb 的步进值进行此调节以符合广播视频要求。频率裕量特性还有利于进行系统设计验证测试 (DVT)，如标准合规性和系统时序裕量测试。

封装信息(1)
器件型号封装封装尺寸(2)
LMK61E07SIA（QFM，6）7.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
GUID-606C5234-2DF3-423B-B1CE-3645FEAE7068-low.gif引脚分布和简化框图

4 Revision History

Changes from Revision A (October 2018) to Revision B (August 2023)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将表从“器件信息”更改为“封装信息”Go
  • Changed the OUTDIV_BY0 default from: 0x20 to: 0x46Go
  • Changed the PLL_NDIV_BY0 default from: 0x64 to: 0x31Go
  • Changed the PLL_FRACNUM_ BY1 default from: 0x00 to: 0x01Go
  • Changed the PLL_FRACNUM_ BY0 default from: 0x00 to: 0x1FGo
  • Changed the PLL_FRACDEN_ BY1 default from: 0x00 to: 0x02Go
  • Changed the PLL_FRACDEN_ BY0 default from: 0x00 to: 0x71Go
  • Changed the PLL_CALCTRL default from: 0x00 to: 0x09Go
  • Changed ENCAL and AUTOSTRT register descriptionsGo
  • Changed XO_CAPCTRL [9:2] default from: 0x80 to: 0x00Go
  • Changed PLL_LF_R2[7:0] default from: 0x08 to: 0x28Go
  • Moved the Power Supply Recommendations and Layout sections to the Application and Implementation sectionGo

Changes from Revision * (December 2017) to Revision A (October 2018)

  • Changed the Loop Filter Structure of PLL graphic Go
  • Changed the LMK61E07 Interface and Control Block graphic Go

5 Pin Configuration and Functions

GUID-01BDD946-1C22-4968-AA32-B1C6396A9D51-low.gifFigure 5-1 SIA Package6-Pin QFMTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
POWER
GND 3 Ground Device Ground.
VDD 6 Power 3.3-V Power Supply.
OUTPUT BLOCK
OUTP 4 Output Differential Output Pair (LVPECL, LVDS, or HCSL).
OUTN 5
DIGITAL CONTROL / INTERFACES
SCL 2 LVCMOS I2C Serial Clock (open-drain). Requires an external pullup resistor to VDD.
SDA 1 LVCMOS I2C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VDDDevice supply voltage–0.33.6V
VINInput voltage for logic inputs–0.3VDD + 0.3V
VOUTOutput voltage for clock outputs–0.3VDD + 0.3V
TJJunction temperature150°C
TSTGStorage temperature–40125°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VDDDevice supply voltage3.1353.33.465V
TAAmbient temperature–402585°C
TJJunction temperature115°C
tRAMPVDD power-up ramp time0.1100ms

 
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