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  • TPS92830-Q1 3 通道大电流线性 LED 控制器

    • ZHCSGY7B October   2017  – January 2018 TPS92830-Q1

      PRODUCTION DATA.  

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  • TPS92830-Q1 3 通道大电流线性 LED 控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Bias
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Current Reference (IREF)
        3. 8.3.1.3 Low-Current Fault Mode
      2. 8.3.2 Charge Pump
        1. 8.3.2.1 Charge Pump Architecture
      3. 8.3.3 Constant-Current Driving
        1. 8.3.3.1 High-Side Current Sense
        2. 8.3.3.2 High-Side Current Driving
        3. 8.3.3.3 Gate Overdrive Voltage Protection
        4. 8.3.3.4 High-Precision Current Regulation
        5. 8.3.3.5 Parallel MOSFET Driving
      4. 8.3.4 PWM Dimming
        1. 8.3.4.1 Supply Dimming
        2. 8.3.4.2 PWM Dimming by Input
        3. 8.3.4.3 Internal Precision PWM Generator
        4. 8.3.4.4 Full Duty-Cycle Switch
      5. 8.3.5 Analog Dimming
        1. 8.3.5.1 Analog Dimming Topology
        2. 8.3.5.2 Internal High-Precision Pullup Current Source
      6. 8.3.6 Output Current Derating
        1. 8.3.6.1 Output-Current Derating Topology
      7. 8.3.7 Diagnostics and Fault
        1. 8.3.7.1 LED Short-to-GND Detection
        2. 8.3.7.2 LED Short-to-GND Auto Retry
        3. 8.3.7.3 LED Open-Circuit Detection
        4. 8.3.7.4 LED Open-Circuit Auto Retry
        5. 8.3.7.5 Dropout-Mode Diagnostics
        6. 8.3.7.6 Overtemperature Protection
        7. 8.3.7.7 FAULT Bus Output With One-Fails–All-Fail
        8. 8.3.7.8 Fault Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Undervoltage Lockout, V(IN) < V(UVLO)
      2. 8.4.2 Normal Operation (V(IN) ≥ 4.5 V, V(IN) > V(LED) + 0.5 V)
      3. 8.4.3 Low-Voltage Dropout
      4. 8.4.4 Fault Mode (Fault Is Detected)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Automotive Exterior Lighting With One-Fails–All-Fail
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High-Precision Dual-Brightness PWM Generation
        1. 9.2.2.1 Dual-Brightness Application
        2. 9.2.2.2 Design Requirements
        3. 9.2.2.3 Detailed Design Procedure
        4. 9.2.2.4 Application Curve
      3. 9.2.3 Driving High-Current LEDs With Parallel MOSFETs
        1. 9.2.3.1 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS92830-Q1 3 通道大电流线性 LED 控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合 AEC-Q100 标准
    • 器件温度等级 1：环境运行温度范围为 -40°C 至 125°C
    • 器件人体放电模型 (HBM) 静电防护 (ESD) 分类等级 H2
    • 器件组件充电模型 (CDM) ESD 分类等级 C4B
  • 4.5V 至 40V 的宽电压输入范围
  • 3 通道高侧电流驱动和检测
    • 通道独立的电流设置
    • 通道独立的 PWM 输入
    • 通过 PWM 输入和电源实现 PWM 调光
    • 针对 EMC 优化的压摆率
  • 高精度 LED 驱动
    • 采用外部 N 沟道 MOSFET 的精密电流调节（2.5% 容差）
    • 具有非板载 Bin 电阻支持的 20:1 模拟调光配置
    • 具有全占空比屏蔽的精密 PWM 发生器（2% 容差）
    • 用于同步的开漏 PWM 输出
  • 保护和诊断
    • 用于外部 MOSFET 热保护的可调节输出电流降额
    • 具有自动恢复功能的 LED 灯串开路或短路诊断
    • 针对低电压运行支持诊断并具有可调节阈值
    • 多达 15 个器件的故障总线，可配置为连带失效或仅失效的通道关闭
    • 故障模式下具有较低的静态电流（每个器件小于 0.75mA）
  • 工作结温范围：-40°C 至 150°C
  • TSSOP 28 封装 (PW)

2 应用

  • 后灯 – 尾灯和制动灯、后转向灯、雾灯、倒车灯
  • 前灯 – 位置灯、日间行车灯、前转向灯、近光灯

3 说明

在实现更佳的灯光均匀性的趋势下，高电流 LED 通常用于汽车前灯和后灯（配备灯光扩散器和导光板）。同时，为了满足严格的 EMC 和可靠性要求，线性 LED 驱动器广泛用于汽车 应用。不过，通过集成功率晶体管为线性 LED 驱动器提供高电流是一项挑战。TPS92830-Q1 器件是一款先进的汽车级高侧恒定电流线性 LED 控制器，通过使用外部 N 沟道 MOSFET 提供高电流。该器件具有一整套用于 汽车 应用的 功能， 并与各种 N 沟道 MOSFET 兼容。

TPS92830-Q1 器件的每个通道可以通过感应电阻器值独立设置通道电流。内部精密恒定电流调节环路通过感应电阻器上的电压感应通道电流，并相应地控制 N 沟道 MOSFET 的栅极电压。该器件还集成了一个两级电荷泵，用于低压降运行。电荷泵电压足够高，可以支持各种 N 沟道 iMOSFET。iPWM i调光i允许使用i多个

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS92830-Q1 TSSOP (28) 9.70mm x 4.40mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化原理图

TPS92830-Q1 page1_SLIS178.gif

4 修订历史记录

Changes from A Revision (October 2017) to B Revision

  • Changed timing specification for PWM duty cycleGo

Changes from * Revision (July 2017) to A Revision

  • 在特性 部分中更改了电流调节和 PWM 发生器的容差Go
  • Changed values for several parameters throughout the Electrical Characteristics tableGo
  • Changed parameter definitions for I(DRV_source) and I(DRV_sink) in the Electrical Chaaracteristics tableGo
  • Changed parameter symbols for analog dimming accuracy in the Electrical Characteristics tableGo
  • Changed parameter descriptions for V(OPEN_th_rising), V(OPEN_th_falling),Go
  • Changed parameter descriptions for t(SG_retry_OFF) and t(OPEN_retry_OFF) in the Timing Requirements tableGo
  • Added a condition for Typical CharacteristicFigure 6Go
  • Deleted a condition from Typical CharacteristicFigure 8Go
  • Deleted a Fast Power Down and Slow Power Up typical characteristic graphGo
  • Added a Fast Power Down and Slow Power Up typical characteristic graphGo
  • Added a condition for Typical CharacteristicFigure 17Go
  • Added a condition for Typical CharacteristicFigure 18Go
  • Changed heat dissipation to current distribution in Parallel MOSFET DrivingGo
  • Deleted a sentence from the PWM Dimming by Input sectionGo
  • Added resistor and capacitor reference designatorsGo
  • Deleted percentage values for V(ICTRL_LIN_BOT) and V(ICTRL_LIN_TOP) in the Analog Dimming Topology sectionGo
  • Changed V(SG_th_rising) and V(SG_th_falling) with each other in the LED Short-to-GND Detection sectionGo
  • Changed symbol of short-to-ground retry current to I(Retry_short)Go
  • Changed symbol of LED-open retry current to I(Retry_open) in the LED Open-Circuit Auto Retry sectionGo
  • Changed some FAULT TYPE names in Table 4Go
  • Updated application schematic. Go
  • Changed the value of R8 from 75 kΩ to 76 kΩ for the PWM threshold settingGo
  • Changed the equation for calculating K(RES_DiagEn)Go
  • Changed the values of R13 and R6 for Go
  • Changed the equation for calculating K(RES_DERATE)Go
  • Changed component values inthe PWM equations of the Detailed Design ProcedureGo
  • Added an application curveGo
  • Added text in the Layout Guidelines for keeping LED ground separate from device groundGo

5 说明 （续）

源以实现灵活性 - 内部 PWM 发生器、外部 PWM 输入或电源调光。各种专为汽车应用 设计的 诊断和保护可 帮助 提高系统稳健性和易用性。连带失效故障总线支持 TPS92830-Q1 与 TPS92630-Q1、TPS92638-Q1 和 TPS9261x-Q1 系列一同运行，以满足各种故障处理要求。

6 Pin Configuration and Functions

PW Package
28-Pin TSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CP1N 2 O Charge pump first-stage flying capacitor negative output, charge pump to provide gate-drive voltage for external MOSFET. Connect a 10-nF flying capacitor between CP1P and CP1N.
CP1P 1 O Charge pump first-stage flying capacitor positive output
CP2N 4 O Charge pump second-stage flying capacitor negative output. Connect a 10-nF flying capacitor between CP2P and CP2N.
CP2P 5 O Charge pump second-stage flying capacitor positive output
CPOUT 6 O Charge-pump output voltage. Connect a 150-nF storage capacitor between CPOUT and IN.
DERATE 9 I Voltage input for current derating. Connect to GND to disable the derate feature.
DIAGEN 8 I Input pin with comparator to enable diagnostics to avoid false open-fault diagnostics when the device works in low-dropout mode. Use a resistor divider to set a threshold according to the LED forward voltage.
FAULT 17 I/O Fault bus pin to support one-fails–all-fail feature. Float: one-fails–all-fail; strong pullup: only-fails-off
FD 13 I Full duty-cycle input, HIGH: 100% PWM; LOW: using external resistor-capacitor network to set PWM duty cycle
G1 26 O Channel 1 gate driver output, connect to CH 1 N-channel MOSFET gate
G2 23 O Channel 2 gate driver output, connect to CH 2 N-channel MOSFET gate
G3 20 O Channel 3 gate driver output, connect to CH 3 N-channel MOSFET gate
GND 3 — GND
ICTRL 14 I Analog dimming input, modulates the regulation voltage across the current-sense resistor. Apply a voltage source or connect a resistor between ICTRL and GND to set the analog dimming ratio.
IN 7 I Power supply for the device. LED current only flows from the external MOSFET to the LED.
ISN1 27 I Channel 1 current-sense negative input. Connect a current-sense resistor between ISP and ISN1 to set the CH 1 current.
ISN2 24 I Channel 2 current-sense negative input. Connect a current-sense resistor between ISP and ISN2 to set the CH 2 current.
ISN3 21 I Channel 3 current-sense negative input. Connect a current-sense resistor between ISP and ISN3 to set the CH 3 current.
IREF 15 O Internal current reference. Connect an 8-kΩ resistor between IREF and GND,
ISP 28 I Channel current-sense positive input. Kelvin-sense to LED sense-resistor positive node.
PWM1 10 I Channel 1 PWM input
PWM2 11 I Channel 2 PWM input
PWM3 12 I Channel 3 PWM input
PWMCHG 16 I/O On-chip PWM generator pin for external R-C. Connect a resistor and a capacitor between PWMCHG and GND to set the PWM duty cycle and frequency.
PWMOUT 18 O High-voltage PWM open-drain output. Connect a 10-kΩ resistor between IN and PWMOUT
SENSE1 25 I/O Channel 1 diagnostics pin. Connect to the CH 1 MOSFET source terminal
SENSE2 22 I/O Channel 2 diagnostics pin. Connect to the CH 2 MOSFET source terminal
SENSE3 19 I/O Channel 3 diagnostics pin. Connect to the CH 3 MOSFET source terminal

7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range TJ= –40°C to 150°C (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage IN(2) –0.3 45(3) V
Input voltage DERATE, DIAGEN, FD, ICTRL, ISN1, ISN2, ISN3, ISP, PWM1, PWM2, PWM3, PWMOUT, SENSE1, SENSE2, SENSE3(2) –0.3 V(IN) + 0.3 V
Output voltage CP1P, CP2P, CPOUT, G1, G2, G3(2) –0.3 V(IN) + 10 V
Current-sense voltage V(ISP) – V(ISNx) –0.3 1 V
Gate-source voltage V(Gx) – V(SENSEx) –1 12 V
I/O FAULT(2) –0.3 22 V
CP1N, CP2N, IREF, PWMCHG(2) –0.3 6 V
Storage temperature, Tstg –65 150 °C
Junction temperature, TJ -40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
(3) Absolute maximum voltage 45 V for 200 ms.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 Corner pins (CP1P, ICTRL, IREF, ISP) ±750
Other pins ±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating junction temperature range TJ= –40°C to 150°C (unless otherwise noted)
MIN MAX UNIT
Device supply voltage IN 4.5 40 V
Sense voltage ISP 0 V(IN) V
PWM inputs PWMx 0 V(IN) V
Diagnostics enable pin DIAGEN 0 V(IN) V
Current-sense voltage V(ISP) – V(ISNx) 0 1 V
Fault bus FAULT 0 20 V
PWM open-drain output PWMOUT 0 V(IN) V
Analog dimming input ICTRL 0 V(IN) V
Current derating input DERATE 0 V(IN) V
Full duty-cycle input FD 0 V(IN) V

7.4 Thermal Information

THERMAL METRIC(1) TPS92830-Q1 UNIT
PW (TSSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance 79.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.1 °C/W
RθJB Junction-to-board thermal resistance 37.4 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 36.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics

VIN = 5 V to 40 V, VICTRL = 3 V, VDERATE = 0 V, TJ= –40°C to 150°C,(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(POR_rising) Supply voltage POR, rising threshold 4.5 V
I(Quiescent) Device standby current PWMx = HIGH, FD = HIGH 3.5 mA
I(FAULT) Device current in fault mode PWMx = HIGH, FAULT = LOW 0.5 0.75 mA
I(IREF) Reference current R(IREF) = 8 kΩ 99 µA
C(IREF) IREF loading capacitance R(IREF) = 8 kΩ 0 4.3 nF
CHARGE PUMP
V(cp_drv) Charge-pump operating voltage 6.1 8.5 10 V
f(cp_sw) Charge-pump switching frequency 2.65 MHz
C(cp_flying) Charge-pump flying capacitor 10 nF
C(cp_storage) Charge-pump storage capacitor 150 nF
HIGH-PRECISION LOGIC INPUTS (DIAGEN, PWMx, FD)
VIL(DIAGEN) Input logic-low voltage, DIAGEN 1.105 1.145 1.185 V
VIH(DIAGEN) Input logic-high voltage, DIAGEN 1.193 1.224 1.255 V
VIL(PWMx) Input logic-low voltage, PWMx 1.094 1.128 1.161 V
VIH(PWMx) Input logic-high voltage, PWMx 1.176 1.212 1.248 V
VIL(FD) Input logic-low voltage, FD 1.105 1.133 1.161 V
VIH(FD) Input logic-high voltage, FD 1.186 1.216 1.246 V
CONSTANT-CURRENT EXTERNAL N-CHANNEL MOSFET DRIVER
V(CS_REG_FULL) Current-sense-resistor regulation voltage V(ICTRL) = 3 V, V(DERATE) = 0 V 295 mV
∆V(CS)(2)(3) Current-sense-resistor regulation-voltage accuracy V(ICTRL) = 3 V, V(DERATE) = 0 V, channel accuracy –1.5% 1.5%
V(ICTRL) = 3 V, V(DERATE) = 0 V, device accuracy –2.5% 2.5%
I(DRV_source) Gate-driver current-source capability at Gx 190 230 270 µA
I(DRV_sink) Gate-driver current-sink capability at Gx 190 230 270 µA
V(GS_clamp_neg) Gate-source negative clamp voltage –0.9 –0.7 –0.5 V
V(GS_clamp_pos) Gate-source positive clamp voltage 9.8 10.4 11.3 V
I(ISNx_leakage) Leakage current sink on ISNx pins 1.3 2.3 µA
INTERNAL PWM DIMMING
V(PWMCHG_th_rising) Internal PWM generator, rising threshold 1.45 1.48 1.51 V
V(PWMCHG_th_falling) Internal PWM generator, falling threshold 0.78 0.8 0.82 V
V(PWMCHG_th_hys) Internal PWM generator hysteresis 0.68 V
I(PWMCHG) PWM generator pullup current V(PWMCHG) = 0 V, FD = LOW 194 200 206 µA
VOL(PWMOUT) Open-drain PWMOUT pulldown voltage V(PWMCHG) = 3 V, I(PWMOUT) pullup current = 4 mA 0.4 V
rDS(on)(PWMOUT) Open-drain PWMOUT pulldown MOSFET rDS(on) 40 55 90 Ω
ANALOG DIMMING
V(ICTRL_FULL) Full-range ICTRL voltage 1.65 V
V(ICTRL_LIN_TOP) Upper boundary for linear ICTRL dimming 1.425 V
V(ICTRL_LIN_BOT) Lower boundary for linear ICTRL dimming 75 mV
∆V(CS_ ICTRL_H) Analog dimming accuracy V(ICTRL) = 1.35 V, V(DERATE) = 0 V, accuracy: 1 – (V(CS_REG_x) / 0.27), x = 1, 2, 3 –2.5% 2%
∆V(CS_ ICTRL_M) Analog dimming accuracy V(ICTRL) = 0.75 V, V(DERATE) = 0 V, accuracy: 1 – (V(CS_REG_x) / 0.15), x = 1, 2, 3 –4% 4%
∆V(CS_ ICTRL_L) Analog dimming accuracy V(ICTRL) = 0.15 V, V(DERATE) = 0 V, accuracy: 1 –V(CS_REG_x) / 0.03, x = 1, 2, 3 –18% 18%
I(ICTRL_pullup) ICTRL internal pullup current 0.95 0.985 1.02 mA
CURRENT DERATING
V(DERATE_FULL) Full-range DERATE voltage 1.83 V
V(DERATE_HALF) Half-range DERATE voltage 2.38 V
K(DERATE) Derate dimming ratio V(DERATE) = 1.966 V 81% 87% 95%
V(DERATE) = 2.316 V 51% 58% 65%
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold, device triggers open-circuit diagnostics V(SG_th_rising), and V(SG_th_falling) in the Electrical Characteristics table V(ISNx) – V(SENSEx), x = 1, 2, 3 100 145 190 mV
V(OPEN_th_falling) LED open falling threshold, device releases from open-circuit diagnostics V(ISNx) – V(SENSEx), x = 1, 2, 3 240 280 320 mV
V(OPEN_th_hyst) 135 mV
I(Retry_open) LED-open retry current 8 10 12 mA
V(SG_th_rising) Channel output VSENSEx short-to-ground rising threshold, device triggers short-to-ground diagnostics 0.885 0.92 0.95 V
V(SG_th_falling) Channel output VSENSEx short-to-ground falling threshold, device releases from short-to-ground diagnostics 1.17 1.215 1.26 V
V(SG_th_hyst) Channel output VSENSEx short-to-ground hysteresis 295 mV
I(Retry_short) Channel output VSENSEx short-to-ground retry current 0.75 1 1.25 mA
FAULT
VIL(FAULT) Logic-input low threshold 0.7 V
VIH(FAULT) Logic-input high threshold 2 V
VOL(FAULT) Logic-output low threshold With 500-µA external pullup 0.4 V
VOH(FAULT) Logic-output high threshold With 1-µA external pulldown 2.7 3.4 V
I(FAULT_pulldown) FAULT internal pulldown current 650 750 800 µA
I(FAULT_pullup) FAULT internal pullup current 6.5 7.6 9.5 µA
THERMAL PROTECTION
T(TSD) Thermal shutdown threshold 176 ºC
T(TSD_HYS) Thermal shutdown hysteresis 15 ºC
(1) External N-channel MOSFET Ciss = 200 pF, Coss = 70 pF, at VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz, Vth= 4 V, compensation capacitor Cgs = 4 nF
(2) TPS92830-Q1 Equation_08_SLIS178.gif
(3) TPS92830-Q1 Equation_09_SLIS178.gif

 
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