TPS7A39 双路、150mA、宽输入电压正负 LDO 稳压器

7.3.1.1 DC Regulation

An LDO functions as a buffered op-amp in which the input signal is the internal reference voltage (V_NR/SS), as shown in Figure 59, and in normal regulation V_FBP = V_NR/SS. Sharing a single reference ensures that both channels track each other during start-up.

V_NR/SS is designed to have a very low-bandwidth at the input to the error amplifier through the use of a low-pass filter. As such, the reference can be considered as a pure dc input signal.

As Figure 60 shows, the negative LDO on the device regulates with a V_FBN = 0 V and inverts the positive reference (V_BUF). This topology allows the negative regulator to regulate down to 0 V.

Figure 59. Simplified Positive Regulation Circuit

Figure 60. Simplified Negative Regulation Circuit

7.3.1.2 AC and Transient Response

Each LDO responds quickly to a transient on the input supply (line transient) or the output current (load transient). This LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noise-floor (V_n), the LDO approximates an ideal power supply in ac and large-signal conditions.

The performance and internal layout of the device minimizes the coupling of noise from one channel to the other channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.

The noise-reduction and soft-start capacitor (C_NR/SS) and feed-forward capacitor (C_FFx) easily reduce the device noise floor and improve PSRR; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.

7.3.4.1 Start-Up Tracking

Figure 63 shows how both regulators use a common reference, which enables start-up tracking. Using the same reference voltage for both the positive and negative regulators ensures that the regulators start-up together in a controlled fashion; see Figure 24 and Figure 25.

Ramps on V_INx with EN = V_INP that are slower than the soft-start time do not have start-up tracking. If ramps slower than the soft-start time are used then enable should be used to start the device to ensure start-up tracking. A small mismatch between the positive and negative internal enable thresholds means that one channel turns on at a slightly lower input voltage than the other channel. This mismatch is typically not a problem in most applications and is easily solved by controlling the start-up with enable. The external signal can come from the input power supply power-good indicator, a voltage supervisor output such as the TPS3701, or from another source.

Figure 63. Simplified Regulation Circuit

7.3.4.2 Sequencing

Figure 64 and Table 2 describe how the turn-on and turn-off times of both LDOs (respectively) is controlled by setting the enable circuit (EN) and undervoltage lockout circuit (UVLOP and UVLON).

Figure 64. Simplified Turn-On Control

Table 3. Device Functional Mode Comparison

Table 4. Recommended Feedback-Resistor Values for the Positive LDO

Table 5. Recommended Feedback-Resistor Values for the Negative LDO

8.1.8.1 Soft-Start Control (NR/SS)

Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems.

The output voltage (V_OUTx) rises proportionally to V_NR/SS during start-up. As such, the time required for V_NR/SS to reach its nominal value determines the rise time of V_OUTx (start-up time).

The soft-start ramp time depends on the soft-start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Equation 5 calculates the approximate soft-start ramp time (t_SS):

Values for the soft-start charging currents, R_NR/SS, and the device internal C_NR/SS are provided in the table.

8.1.8.1.1 In-Rush Current

In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, the in-rush current can be estimated by Equation 6:

Equation 6.

where

• V_OUTx(t) is the instantaneous output voltage of the turn-on ramp
• dV_OUTx(t) / dt is the slope of the V_OUTx ramp
• R_LOAD is the resistive load impedance

8.1.8.2 Undervoltage Lockout (UVLOx) Control

The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum operational voltage range, and ensures that the device properly shuts down when the input supply collapses.

Figure 66 and Table 6 explain the UVLOx circuit response to various input voltage events, assuming V_EN ≥ V_IH(EN).

The positive and negative UVLO circuits are internally ANDed together. As such, if either supply collapses, both outputs turn-off and V_NR/SS is pulled low internally.

Figure 66. Typical UVLOx Operation

Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time; however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum V_INx.

8.1.9.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control-loop rejects signals from V_INx to V_OUTx across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 7 gives the PSRR calculation as a function of frequency for the input signal [V_INx(f)] and output signal [V_OUTx(f)].

Equation 7.

Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.

Figure 67 shows a simplified diagram of PSRR versus frequency.

Figure 67. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components.

8.1.9.2 Channel-to-Channel Output Isolation and Crosstalk

Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting the other output. This attenuation appears in load transient tests on the other output; however, to numerically quantify the rejection, the output channel isolation is expressed in decibels (dB).

Output isolation performance is a strong function of the PCB layout. See the Layout Guidelines section on how to best optimize the isolation performance.

8.1.9.3 Output Voltage Noise

The TPS7A39 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A39 can be used in a phase-locked loop (PLL)-based clocking circuit that can be used for minimum phase noise, or in test and measurement systems where even small power-supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 68 shows a simplified output voltage noise density plot versus frequency.

Figure 68. Output Voltage Noise Diagram

For further details, see the How to Measure LDO Noise white paper.

8.1.9.4 Optimizing Noise and PSRR

Table 7 describes how the ultra-low noise floor and PSRR of the device can be improved in several ways.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 8. The effect of the C_NR/SS capacitor increases when V_OUTx(NOM) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, a 10-nF to 1-µF C_NR/SS is recommended.

The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.

A larger C_OUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high power dissipation across the die increases the output noise because of the increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and isolating V_OUTx at high frequencies.

8.1.9.5 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions illustrated in Figure 69 are broken down in this section and are described in Table 8. Regions A, E, and H are where the output voltage is in steady-state. Increasing the output capacitance improves the transient response (less dip); however, the transient takes longer to recover when using a large output capacitor.

Figure 69. Load Transient Waveform

8.1.10.1 Output Voltage Accuracy (V_OUTx)

The device features an output voltage accuracy that includes the errors introduced by the internal reference, load regulation, line regulation, process variation, and operating temperature as specified by the table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent (for very low output voltages this specification is in mV).

8.1.10.2 Dropout Voltage (V_DO)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (|V_DO| = |V_INx| – |V_OUTx|) that is required for regulation. When V_INx drops below the required V_DOx for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch.

8.1.12.1 Estimating Junction Temperature

The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB) are given in the Electrical Characteristics table and are used in accordance with Equation 11.

Equation 11.

where

• P_D is the power dissipated as explained in Equation 9
• T_T is the temperature at the center-top of the device package
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package edge

8.2.1.1 Design Requirements

8.2.1.2 Detailed Design Procedure

8.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer

To create the isolated supply, the SN6505B uses a center-tapped transformer. A full bridge rectifier and capacitors are required to regulate the signal before reaching the LDO because of the alternating nature of the input signal. TI recommends having a fast switching and low forward voltage diode to improve efficiency because of how fast the SN6505 switches; Schottky diodes work well. Figure 73 shows the switching nodes of the SN6505 D1 and D2 and also shows where the transformer connects to the full bridge rectifier TP1 and TP2. Figure 73 shows the switching waveforms across the rectifier diodes.

Figure 72. Bridge Rectifier With Center-Tapped Secondary Enables Bipolar Outputs

8.2.1.3 Application Curves

Figure 73. Switching Node of the SN6505B

Figure 75. System Startup

Figure 77. OUTN Noise

IOUT = IOUTP + |IOUTN|, IOUTP = |IOUTN|

Figure 74. Efficiency vs Output Current

Figure 76. OUTP Noise

8.2.2.1 Design Requirements

A common problem in analog-to-digital converters (ADCs) is that as the input signal approaches the edge of the range of the ADC, the signal begins to become distorted. Often times this is not because of a limitation of the ADC, but is a result of the analog front-end (AFE). In the AFE, the signal begins to approach the rails of the op amp and the signal begins to lose linearity and becomes distorted. This distortion is because when the rail-to-rail op amp begins to enter the nonlinear region of operation within 100 mV of the rail, the signal-to-noise ratio (SNR) starts to degrade and the total harmonic distortion (THD) of the ADC increases. To prevent the op amp from exiting the linear region of operation, the design must use a power supply that can generate rails 200 mV above and below the input range of the ADC.

8.2.2.2 Detailed Design Procedure

In this design, the ADS8900B is used as the ADC. This ADC features a differential input, so from a 5-V reference the ADC is able to encode values between ±5 V. In many applications, single-supply op amps are powered with rails from 0 V to 5 V, which causes the input signal to become distorted when the full range signal is applied. The FFT of a 10-V_PP (peak-to-peak) sine wave using a single 5-V rail to bias the amplifiers is illustrated in Figure 79. In this test the SNR was calculated to be 54.89 dB and the THD was calculated to be –40.68 dB.

There is a simple solution to improve the SNR and THD of the ADC: bias the amplifiers in the analog front end with a 5.2-V rail and a –0.2-V rail. Using these rails allows the amplifier to operate in the linear region in the 0-V to 5-V range needed by the ADC. The FFT of a 10-V_PP sine wave using a 5.2-V rail and a –0.2-V rail is illustrated in Figure 80. In this test the SNR was calculated to be 102.535 dB and the THD was calculated to be –121.66 dB. Using –0.2-V and 5.2-V rail voltages still allows for common 5-V (5.5 V max) op amps to be used in the design.

8.2.2.3 Detailed Design Description

8.2.2.4 Application Curves

fIN = 1 kHz, VPP = 10.0 V

Figure 79. FFT Using 5-V and 0-V Supply Rails

fIN = 1 kHz, VPP = 10.0 V

Figure 80. FFT Using 5.2-V and –0.2-V Supply Rails