LM5118 宽电压范围降压/升压控制器

7.3.1 UVLO

An undervoltage lockout pin is provided to disable the regulator when the input is below the desired operating range. If the UVLO pin is below 1.13 V, the regulator enters a standby mode with the outputs disabled, but with VCC regulator operating. If the UVLO input exceeds 1.23 V, the regulator will resume normal operation. A voltage divider from the input to ground can be used to set a VIN threshold to disable the regulator in brownout conditions or for low input faults.

If a current limit fault exists for more than 256 clock cycles, the regulator will enter a hiccup mode of current limiting and the UVLO pin will be pulled low by an internal switch. This switch turns off when the UVLO pin approaches ground potential allowing the UVLO pin to rise. A capacitor connected to the UVLO pin will delay the return to a normal operating level and thereby set the off-time of the hiccup mode fault protection. An internal 5-µA pullup current pulls the UVLO pin to a high state to ensure normal operation when the VIN UVLO function is not required and the pin is left floating.

7.3.2 Oscillator and Sync Capability

The LM5118 oscillator frequency is set by a single external resistor connected between the RT pin and the AGND pin. The R_T resistor should be located very close to the device and connected directly to the pins of the IC. To set a desired oscillator frequency (f), the necessary value for the R_T resistor can be calculated from Equation 1:

Equation 1.

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be of higher frequency than the free-running frequency set by the R_T resistor. A clock circuit with an open-drain output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should be greater than 15 ns.

Multiple LM5118 devices can be synchronized together simply by connecting the SYNC pins together as in Figure 11. In this configuration, all of the devices are synchronized to the highest frequency device. Figure 12 shows the SYNC input and output features of the LM5118. The internal oscillator circuit drives the SYNC pin with a strong pull down or weak pullup inverter. When the SYNC pin is pulled low, either by the internal oscillator or an external clock, the ramp cycle of the oscillator is terminated and forced 400 ns off-time is initiated before a new oscillator cycle begins. If the SYNC pins of several LM5118 IC’s are connected together, the IC with the highest internal clock frequency will pull all the connected SYNC pins low and terminate the oscillator ramp cycles of the other ICs. The LM5118 with the highest programmed clock frequency will serve as the master and control the switching frequency of all the devices with lower oscillator frequencies.

Figure 11. Sync From Multiple Devices

Figure 12. Simplified Oscillator and Block Diagram With Sync I/O Circuit

7.3.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference (1.23 V). The output of the error amplifier is connected to the COMP pin. Loop compensation components, typically a type II network shown in are connected between the COMP and FB pins. This network creates a low frequency pole, a zero, and a noise reducing high frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to the error amplifier output voltage at the COMP pin. The same error amplifier is used for operation in buck and buck-boost mode.

Figure 13. Composition of Emulated Current Signal

7.3.4 Ramp Generator

The ramp signal of a pulse-width modulator with current mode control is typically derived directly from the buck switch drain current. This switch current corresponds to the positive slope portion of the inductor current signal. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics. The leading edge spike must be filtered or blanked to avoid early termination of the PWM pulse. Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimal achievable pulse width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling a small pulse width is necessary for regulation. The LM5118 uses a unique ramp generator which does not actually measure the buck switch current but instead creates a signal representing or emulating the inductor current. The emulated ramp provides signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements, a sample-and-hold pedestal level and a ramp capacitor which is charged by a controlled current source. Refer to Figure 13 for details.

The sample-and-hold pedestal level is derived from a measurement of the recirculating current through a current sense resistor in series with the recirculating diode of the buck regulator stage. A small value current sensing resistor is required between the recirculating diode anode and ground. The CS and CSG pins should be Kelvin connected directly to the sense resistor. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the reconstructed current signal. The sample and hold of the recirculating diode current is valid for both buck and buck-boost modes. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to the AGND and an internal voltage controlled current source. In buck mode, the ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per Equation 2:

Equation 2.

In buck-boost mode, the ramp current source is a function of the input voltage VIN, per Equation 3:

Equation 3.

Proper selection of the RAMP capacitor (C_RAMP) depends upon the value of the output inductor (L) and the current sense resistor (R_S). For proper current emulation, the sample and hold pedestal value and the ramp amplitude must have the same relative relationship to the actual inductor current. That is:

Equation 4.

where

• g_m is the ramp generator transconductance (5 µA/V)
• A is the current sense amplifier gain (10V/V)

The ramp capacitor should be located very close to the device and connected directly to the RAMP and AGND pins.

The relationship between the average inductor current and the pedestal value of the sampled inductor current can cause instability in certain operating conditions. This instability is known as sub-harmonic oscillation, which occurs when the inductor ripple current does not return to its initial value by the start of the next switching cycle. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 50 µA of offset current provided from the emulated current source adds enough slope compensation to the ramp signal for output voltages less than or equal to 12 V. For higher output voltages, additional slope compensation may be required. In such applications, the ramp capacitor can be decreased from the nominal calculated value to increase the ramp slope compensation.

The pedestal current sample is obtained from the current sense resistor (Rs) connected to the CS and CSG pins. It is sometimes helpful to adjust the internal current sense amplifier gain (A) to a lower value in order to obtain the higher current limit threshold. Adding a pair of external resistors RG in a series with CS and CSG as in Figure 14 reduces the current sense amplifier gain A according to Equation 5:

Equation 5.

7.3.5 Current Limit

In the buck mode the average inductor current is equal to the output current (IOUT). In buck-boost mode the average inductor current is approximately equal to:

Equation 6.

Consequently, the inductor current in buck-boost mode is much larger especially when VOUT is large relative to VIN. The LM5118 provides a current monitoring scheme to protect the circuit from possible over-current conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a scale factor determined by the current sense resistor. The emulated ramp signal is applied to the current limit comparator. If the peak of the emulated ramp signal exceeds 1.25 V when operating in the buck mode, the PWM cycle is immediately terminated (cycle-by-cycle current limiting). In buck-boost mode the current limit threshold is increased to 2.50 V to allow higher peak inductor current. To further protect the external switches during prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter detects 256 consecutive current limited PWM cycles, the LM5118 enters a low power dissipation hiccup mode. In the hiccup mode, the output drivers are disabled, the UVLO pin is momentarily pulled low, and the soft-start capacitor is discharged. The regulator is restarted with a normal soft-start sequence once the UVLO pin charges back to 1.23 V. The hiccup mode off-time can be programmed by an external capacitor connected from UVLO pin to ground. This hiccup cycle will repeat until the output overload condition is removed.

In applications with low output inductance and high input voltage, the switch current may overshoot due to the propagation delay of the current limit comparator and control circuitry. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating diode current. If the sample-and-hold pedestal level exceeds the internal current limit threshold, the buck switch will be disabled and will skip PWM cycles until the inductor current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay before the buck switch is turned on again.

Figure 14. Current Limit and Ramp Circuit

7.3.6 Maximum Duty Cycle

Each conduction cycle of the buck switch is followed by a forced minimum off-time of 400 ns to allow sufficient time for the recirculating diode current to be sampled. This forced off-time limits the maximum duty cycle of the controller. The actual maximum duty cycle will vary with the operating frequency as follows:

Figure 15. Maximum Duty Cycle vs Frequency

Limiting the maximum duty cycle will limit the maximum boost ratio (VOUT/VIN) while operating in buck-boost mode. For example, from Figure 15, at an operating frequency of 500 kHz, D_MAX is 80%. Using the buck-boost transfer function.

Equation 8.

With D = 80%, solving for VOUT results in:

With a minimum input voltage of 5 V, the maximum possible output voltage is 20 V at f = 500 kHz. The buck-boost step-up ratio can be increased by reducing the operating frequency which increases the maximum duty cycle.

7.3.7 Soft Start

The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing start-up stresses and surges. The internal 10-µA soft-start current source gradually charges an external soft-start capacitor connected to the SS pin. The SS pin is connected to the positive input of the internal error amplifier. The error amplifier controls the pulse-width modulator such that the FB pin approximately equals the SS pin as the SS capacitor is charged. Once the SS pin voltage exceeds the internal 1.23-V reference voltage, the error amp is controlled by the reference instead of the SS pin. The SS pin voltage is clamped by an internal amplifier at a level of 150 mV above the FB pin voltage. This feature provides a soft-start controlled recovery in the event a severe overload pulls the output voltage (and FB pin) well below normal regulation but does not persist for 256 clock cycles.

Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the voltage level of the SS pin. The SS pin acts as a non-inverting input to the error amplifier anytime SS voltage is less than the 1.23-V reference. In the event a fault is detected (overtemperature, VCC undervoltage, hiccup current limit), the soft-start capacitor will be discharged. When the fault condition is no longer present, a new soft-start sequence will begin.

7.3.8 HO Output

The LM5118 contains a high-side, high-current gate driver and associated high voltage level shift. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1-µF ceramic capacitor, connected with short traces between the HB pin and HS pin is recommended for most circuit configurations. The size of the bootstrap capacitor depends on the gate charge of the external FET. During the off time of the buck switch, the HS pin voltage is approximately –0.5 V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be forced off each cycle for 400 ns to ensure that the bootstrap capacitor is recharged.

7.3.9 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state, disabling the output driver and the bias regulator. This protection is provided to prevent catastrophic failures from accidental device overheating.

7.4.1 Buck Mode Operation: VIN > VOUT

The LM5118 buck-boost regulator operates as a conventional buck regulator with emulated current mode control while VIN is greater than VOUT and the buck mode duty cycle is less than 75%. In buck mode, the LO gate drive output to the boost switch remains low.

7.4.2 Buck-Boost Mode Operation: VIN ≊ VOUT

When VIN decreases relative to VOUT, the duty cycle of the buck switch will increase to maintain regulation. Once the duty cycle reaches 75%, the boost switch starts to operate with a very small duty cycle. As VIN is further decreased, the boost switch duty cycle increases until it is the same as the buck switch. As VIN is further decreased below VOUT, the buck and boost switch operate together with the same duty cycle and the regulator is in full buck-boost mode. This feature allows the regulator to transition smoothly from buck to buck-boost mode. Note that the regulator can be designed to operate with VIN less than 4 V, but VIN must be at least 5 V Figure 16 presents a timing illustration of the gradual transition from buck to buck-boost mode when the input voltage ramps downward over a few switching cycles.

Figure 16. Buck (HO) and Boost (LO) Switch Duty Cycle vs. Time,
Illustrating Gradual Mode Change With Decreasing Input Voltage

7.4.3 High Voltage Start-Up Regulator

The LM5118 contains a dual-mode, high voltage linear regulator that provides the VCC bias supply for the PWM controller and the MOSFET gate driver. The VIN input pin can be connected directly to input voltages as high as 75 V. For input voltages below 10 V, an internal low dropout switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltages greater than 10 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. A wide operating range of 4 V to 75 V (with a start-up requirement of at least 5 V) is achieved through the use of this dual mode regulator.

The output of the VCC regulator is current limited to 35 mA, typical. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC undervoltage threshold of 3.7 V and the UVLO input pin voltage is greater than 1.23 V, the gate driver outputs are enabled and a soft-start sequence begins. The gate driver outputs remain enabled until VCC falls below 3.5 V or the voltage at the UVLO pin falls below 1.13 V.

In many applications, the regulated output voltage or an auxiliary supply voltage can be applied to the VCCX pin to reduce the IC power dissipation. For output voltages between 4 V and 15 V, VOUT can be connected directly to VCCX. When the voltage at the VCCX pin is greater than 3.85 V, the internal VCC regulator is disabled and an internal switch connects VCCX to VCC, reducing the internal power dissipation.

In high voltage applications, take extrac care to ensure the VIN pin voltage does not exceed the absolute maximum voltage rating of 76 V. During line or load transients, voltage ringing on the VIN line that exceeds the absolute maximum rating can damage the IC. Both careful PCB layout and the use of quality bypass capacitors located close to the VIN and GND pins are essential.

Figure 17. VIN and VCC Sequencing

7.4.4 Enable

The LM5118 contains an enable function which provides a very low input current shutdown mode. If the EN pin is pulled below 0.5 V, the regulator enters shutdown mode, drawing less than 10 µA from the VIN pin. Raising the EN input above 3 V returns the regulator to normal operation. The EN pin can be tied directly to the VIN pin if this function is not needed. It must not be left floating. A 1-MΩ pullup resistor to VIN can be used to interface with an open-collector or open-drain control signal.

8.2.1 Design Requirements

The procedure for calculating the external components is illustrated with the following design example. The designations used in the design example correlate to the Figure 19. The design specifications are:

• VOUT = 12 V
• VIN = 5 V to 42 V
• f = 300 kHz
• Minimum load current (CCM operation) = 600 mA
• Maximum load current = 3 A

8.2.2 Detailed Design Procedure

8.2.2.2 R7 = R_T

RT sets the oscillator switching frequency. Generally speaking, higher operating frequency applications will use smaller components, but have higher switching losses. An operating frequency of 300 kHz was selected for this example as a reasonable compromise for both component size and efficiency. The value of R_T can be calculated as follows:

Equation 10.

therefore, R7 = 18.3 kΩ

Figure 20. Inductor Current Waveform

8.2.2.3 Inductor Selection, L1

The inductor value is determined based upon the operating frequency, load current, ripple current and the input and output voltages. Refer to Figure 20 for details.

To keep the circuit in continuous conduction mode (CCM), the maximum ripple current I_RIPPLE should be less than twice the minimum load current. For the specified minimum load of 0.6 A, The maximum ripple current is 1.2 Ap-p. Also, the minimum value of L must be calculated both for a buck and buck-boost configurations. The final value of inductance will generally be a compromise between the two modes. It is desirable to have a larger value inductor for buck mode, but the saturation current rating for the inductor must be large for buck-boost mode, resulting in a physically large inductor. Additionally, large value inductors present buck-boost mode loop compensation challenges which will be discussed in the Error Amplifier Configuration section. For the design example, the inductor values in both modes are calculated as:

Equation 11.

Equation 12.

where

• V_OUT is the output voltage
• V_IN(MAX) is the maximum input voltage
• f is the switching frequency
• I_RIPPLE is the selected inductor peak to peak ripple current (1.2 A selected for this example)
• V_IN(MIN) is the minimum input voltage

The resulting inductor values are:

• L1 = 28 µH, Buck Mode
• L1 = 9.8 µH Buck-Boost mode

A 10-µH inductor was selected which is a compromise between these values, while favoring the buck-boost mode. As illustrated in the compensation section below, the inductor value should be as low as possible to move the buck-boost right-half-plane zero to a higher frequency. The ripple current is then rechecked with the selected inductor value using Equation 11 and Equation 12,

Equation 13. I_RIPPLE(BUCK) = 3.36 A

Equation 14. I_{RIPPLE(BUCK-BOOST)} = 1.17 A

Because the inductor selected is lower than calculated for the Buck mode, the minimum load current for CCM in buck mode is 1.68 A at maximum VIN.

With a 10-µH inductor, the worst case peak inductor currents can be estimated for each case, assuming a 20% inductor value tolerance and assuming 80% efficiency of the converter.

Equation 15.

Equation 16.

where

• η is efficiency
• L_TOL is the inductor tolerance

For this example, Equation 15 and Equation 16 yield:

Equation 17. I_1(PEAK) = 5.62 A

Equation 18. I_2(PEAK) = 13.4 A

An acceptable current limit setting would be 6.7 A for buck mode because the LM5118 automatically doubles the current limit threshold in buck-boost mode. The selected inductor must have a saturation current rating at least as high as the buck-boost mode cycle-by-cycle current limit threshold, in this case at least 13.5 A. A 10-µH, 15-A inductor was chosen for this application.

8.2.2.4 R13 = R_SENSE

To select the current sense resistor, begin by calculating the minimum K values for each mode using Equation 19 and Equation 20. K represents the slope compensation of the controller and is different for each mode, K_BUCK and K_BUCK-BOOST.

Equation 19.

Equation 20.

• K_BUCK = 1.16
• K_BUCK-BOOST = 3

Use Equation 21 and Equation 22 to calculate RSENSE for each mode of operation. A design margin, M, should be selected between 10%-30% to allow for component tolerances. For this design M was selected to be 10%.

Equation 21.

Equation 22.

• R13_(BUCK) = 19.75 mΩ
• R13_(BUCK-BOOST) = 15.5 mΩ

An R_SENSE value of no more than 15.5 mΩ must be used to ensure the required maximum output current in the buck-boost mode. A standard value of 15 mΩ was selected for this design.

8.2.2.5 C15 = C_RAMP

With the inductor value selected, the value of C3 necessary for the emulation ramp circuit is:

Equation 23.

With the inductance value (L1) selected as 10 µH, the calculated value for C_RAMP is 333 pF. A standard value of 330 pF was selected.

8.2.2.6 Inductor Current Limit Calculation

The current limit for each mode can be calculated using Equation 24 and Equation 26. If the peak current limit is less than the calculated inductor peak current the R13 and C15 need to be recalculated. This can be done by increasing the previous K values or M and reiterating the calculations.

Equation 24.

Equation 25. I_LIMIT(BUCK) = 7.795 A

Equation 26.

Equation 27. I_{LIMIT(BUCK-BOOST)} = 14.29 A

8.2.2.7 C9 - C12 = Output Capacitors

In buck-boost mode, the output capacitors C9 - C12 must supply the entire output current during the switch on-time. For this reason, the output capacitors are chosen for operation in buck-boost mode, the demands being much less in buck operation. Both bulk capacitance and ESR must be considered to ensure a given output ripple voltage. Buck-boost mode capacitance can be estimated from:

Equation 28.

ESR requirements can be estimated from:

Equation 29.

For this example, with a ΔVOUT (output ripple) of 50 mV:

Equation 30. C_MIN = 141 µF

Equation 31. ESR_MAX = 4.6 mΩ

If hold-up times are a consideration, the values of the input and output capacitors must be increased appropriately. Note that it is usually advantageous to use multiple capacitors in parallel to achieve the ESR value required. Also, it is good practice to put a .1-µF to .47-µF ceramic capacitor directly on the output pins of the supply to reduce high-frequency noise. Ceramic capacitors have good ESR characteristics, and are a good choice for input and output capacitors. It should be noted that the effective capacitance of ceramic capacitors decreases with dc bias. For larger bulk values of capacitance, a low ESR electrolytic is usually used. However, electrolytic capacitors have poor tolerance, especially over temperature, and the selected value should be selected larger than the calculated value to allow for temperature variation. Allowing for component tolerances, the following values of COUT were chosen for this design example:

Two 180-µF Oscon electrolytic capacitors for bulk capacitance

Two 47-µF ceramic capacitors to reduce ESR

Two 0.47-µF ceramic capacitors to reduce spikes at the output.

8.2.2.10 C1 - C5 = Input Capacitor

A typical regulator supply voltage has a large source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the buck switch on-time. When the buck switch turns on, the current into the buck switch steps from zero to the lower peak of the inductor current waveform, then ramps up to the peak value, and then drops to the zero at turnoff. The RMS current rating of the input capacitors depends on which mode of operation is most critical.

Equation 32.

This value is a maximum at 50% duty cycle which corresponds to VIN = 24 V.

Equation 33.

Checking both modes of operation we find:

• I_RMS(BUCK) = 1.5 A
• I_{RMS(BUCK-BOOST)} = 4.7 A

Therefore C1-C5 should be sized to handle 4.7 A of ripple current. Quality ceramic capacitors with a low ESR should be selected. To allow for capacitor tolerances, five 2.2-µF, 100-V ceramic capacitors will be used. If step input voltage transients are expected near the maximum rating of the LM5118, a careful evaluation of the ringing and possible spikes at the device VIN pin should be completed. An additional damping network or input voltage clamp may be required in these cases.

8.2.2.13 C16 = C_SS

The capacitor at the SS pin determines the soft-start time, that is, the time for the reference voltage and the output voltage, to reach the final regulated value. The time is determined from:

Equation 35.

and assumes a current limit > Iload + ICout

For this application, a C16 value of 0.1 µF was chosen which corresponds to a soft-start time of about 12 ms.

8.2.2.14 R8, R9

R8 and R9 set the output voltage level, the ratio of these resistors is calculated from:

Equation 36.

For a 12-V output, the R8/R9 ratio calculates to 8.76. The resistors should be chosen from standard value resistors and a good starting point is to select resistors within power ratings appropriate for the output voltage. Values of 309 Ω for R9 and 2.67 kΩ for R8 were selected.

8.2.2.15 R1, R3, C21

A voltage divider can be connected to the UVLO pin to set a minimum operating voltage VIN_(UVLO) for the regulator. If this feature is required, the easiest approach to select the divider resistor values is to choose a value for R1 between 10 kΩ and 100 kΩ, while observing the minimum value of R1 necessary to allow the UVLO switch to pull the UVLO pin low. This value is:

R1 ≥ 1000 × V_IN(MAX)

R1 ≥ 75 k in our example

R3 is then calculated from:

Equation 37.

Because VIN_(MIN) for our example is 5 V, set VIN_(UVLO) to 4.0 V for some margin in component tolerances and input ripple.

R1 = 75 k is chosen since it is a standard value.

R3 = 29.332 k is calculated from Equation 37. The 29.4 k value was used since it is a standard value.

Capacitor C21 provides filtering for the divider and the off-time of the hiccup duty cycle during current limit. The voltage at the UVLO pin should never exceed 15 V when using an external set-point divider. It may be necessary to clamp the UVLO pin at high input voltages.

Knowing the desired off time during hiccup current limit, the value of C21 is given by:

Equation 38.

Notice that t_OFF varies with V_IN

In this example, C21 was chosen to be 0.1 µF. This will set the t_OFF time to 723 µs with VIN = 12 V.

8.2.2.18 Error Amplifier Configuration

8.2.2.18.1 R4, C18, C17

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only three feedback components, R4, C18 and C17. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM5118 is as follows:

Equation 39.

The dominant, low frequency pole of the modulator is determined by the load resistance (R_LOAD) and output capacitance (C_OUT). The corner frequency of this pole is:

Equation 40.

For this example, R_LOAD = 4 Ω, D_MAX = 0.705, and C_OUT = 454 µF, therefore:

Equation 41. f_P(MOD) = 149 Hz

Equation 42. DC Gain_(MOD) = 4.598 = 13.25 dB

Additionally, there is a right-half plane (RHP) zero associated with the modulator. The frequency of the RHP zero is:

Equation 43.

Equation 44. f_RHPzero = 7.8 kHz

The output capacitor ESR produces a zero given by:

Equation 45.

Equation 46. ESR_ZERO = 76 kHz

The RHP zero complicates compensation. The best design approach is to reduce the loop gain to cross zero at about 25% of the calculated RHP zero frequency. The Type ll error amplifier compensation provided by R4, C18, and C17 places one pole at the origin for high DC gain. The 2nd pole should be located close to the RHP zero. The error amplifier zero (Equation 47) should be placed near the dominate modulator pole. This is a good starting point for compensation. Refer to the on-line LM5118 Quick-Start calculator for ready to use equations and more details.

Components R4 and C18 configure the error amplifier as a type II configuration which has a DC pole and a zero at:

Equation 47.

C17 introduces an additional pole used to cancel high-frequency switching noise. The error amplifier zero cancels the modulator pole leaving a single pose response at the crossover frequency of the loop gain if the crossover frequency is much lower than the right half plane zero frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 2.0 kHz was selected (about 25% of the right-half-plane zero frequency). The error amplifier zero (fz) should be selected at a frequency near that of the modulator pole and much less than the target crossover frequency. This constrains the product of R4 and C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4, while proportionally decreasing C18 increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C18 decreases the error amp gain. For the design example C18 was selected for 100 nF and R4 was selected to be 10 kΩ. These values set the compensation network zero at 159 Hz. The overall loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimal overshoot with a damped response.

8.2.3 Application Curves

The plots in Figure 21 through Figure 26 show the gain and phase diagrams of the design example. The overall bandwidth is lower in a buck-boost application due the compensation challenges associated with the right-half-plane zero. For a pure buck application, the bandwidth could be much higher. The LM5116 data sheet is a good reference for compensation design of a pure buck mode regulator.

Figure 21. Modulator Gain and Phase - Buck Mode

Figure 23. Error Amplifier Gain and Phase - Buck Mode

Figure 25. Overall Loop Gain and Phase - Buck Mode

Figure 22. Modulator Gain and Phase - Buck-Boost Mode

Figure 24. Error Amplifier Gain and Phase - Buck-Boost Mode

Figure 26. Overall Loop Gain and Phase - Buck Boost Mode

11.1.1 开发支持