SN65DSI85-Q1 汽车类双通道 MIPIDSI 转双链路 LVDS 桥接器
- ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
  
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SN65DSI85-Q1 汽车类双通道 MIPIDSI 转双链路 LVDS 桥接器

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1 特性

符合汽车类应用的要求
具有符合 AEC-Q100 标准的下列特性：
- 器件温度等级 2：-40°C 至 105°C 的环境运行温度范围
- 器件 HBM ESD 分类等级 3A
- 器件 CDM ESD 分类等级 C6
实现了 MIPI D-PHY 版本 1.00.00 物理层前端和显示屏串行接口 (DSI) 版本 1.02.00
双通道 DSI 接收器在每个通道上可针对 1 条，2 条，3 条或 4 条 D-PHY 数据信道进行配置，每信道的运行速率高达 1Gbps
支持 RGB666 和 RGB888 格式的 18bpp 与 24bpp DSI 视频流
适合 60fps WQXGA 2560 × 1600 分辨率（18bpp 和 24bpp 颜色），以及 60fps（120fps 等效）WUXGA 1920 × 1200 分辨率和 3D 图形显示（24bpp 颜色）
MIPI 前端可配置为单通道或双通道 DSI 配置
针对单链路或双链路 LVDS 的输出配置
支持双通道 DSI ODD/EVEN 和 LEFT/RIGHT 操作模式
支持两个单通道 DSI 转两条单链路 LVDS 的操作模式
双链路或单链路模式下 LVDS 输出时钟范围为 25MHz 到 154MHz
LVDS 像素时钟可采用自由运行持续 D-PHY 时钟或外部基准时钟 (REFCLK)
1.8V 主 V_CC 电源
低功耗特性包括关断模式、低 LVDS 输出电压摆幅、共模以及 MIPI 超低功耗状态 (ULPS) 支持
针对简化印刷电路板 (PCB) 走线的 LVDS 通道交换 (SWAP)，LVDS 引脚顺序反向特性
采用 64 引脚 10mm × 10mm HTQFP (PAP) 封装 PowerPAD™IC 封装

2 应用

集成显示屏的信息娱乐系统主机
具有远程显示屏的信息娱乐系统主机
后座信息娱乐系统
混合动力汽车仪表板
便携式导航设备
导航
工业人机界面 (HMI) 和显示屏

3 说明

SN65DSI85-Q1 DSI 转 LVDS 桥接器具有一个双通道 MIPI D-PHY 接收器前端
配置，此配置中在每个通道上具有 4 条信道，每条信道的运行速率为 1Gbps，最大输入带宽为 8Gbps。该桥接器可解码 MIPI DSI 18bpp RGB666 和 24bpp RGB888 视频流，并将格式化视频数据流转换为 LVDS 输出（像素时钟范围为 25MHz 至 154MHz），从而提供一个双链路 LVDS、单链路 LVDS 或两个单链路 LVDS 接口（每个链路具有 4 个数据信道）。

SN65DSI85-Q1 器件非常适用于 60fps 的 WQXGA (2560 × 1600)，以及等效 120fps（高达 24 bpp）的 WUXGA 3D 图形和全高清 (1920x1080) 分辨率。该器件实现了部分线路缓冲以适应 DSI 与 LVDS 接口间的数据流不匹配的情况。

SN65DSI85-Q1 器件采用小外形 10mm × 10mm HTQFP
（0.5mm 间距）封装，工作温度范围为 –40ºC 至 +105ºC。

器件信息⁽¹⁾

器件编号	封装	封装尺寸（标称值）
SN65DSI85-Q1	HTQFP (64)	10.00mm x 10.00mm

如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

典型应用

4 修订历史记录

Changes from A Revision (December 2016) to B Revision

Deleted figure RESET and Initialization Timing Definition While V_CC is HighGo
Changed the paragraph following Figure 8Go
Changed Table 1Go

Changes from * Revision (July 2016) to A Revision

已将器件状态更改为量产数据Go

5 Pin Configuration and Functions

PAP Package

64-Pin HTQFP With PowerPAD™

Top View

See the Layout section for layout information.

Pin Functions

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
ADDR	64	I/O	Local I²C interface target address select. See Table 6. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI85-Q1 VCC 1.8-V power rail is connected.
A_Y0P	46	O	LVDS channel A, LVDS data output 0
A_Y0N	47	O	LVDS channel A, LVDS data output 0
A_Y1P	44	O	LVDS channel A, LVDS data output 1
A_Y1N	45	O	LVDS channel A, LVDS data output 1
A_Y2P	41	O	LVDS channel A, LVDS data output 2
A_Y2N	42	O	LVDS channel A, LVDS data output 2
A_Y3P	36	O	LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels.
A_Y3N	37	O
A_CLKP	38	O	LVDS channel A, LVDS clock output
A_CLKN	39	O	LVDS channel A, LVDS clock output
B_Y0P	61	O	LVDS channel B, LVDS data output 0
B_Y0N	62	O	LVDS channel B, LVDS data output 0
B_Y1P	59	O	LVDS channel B, LVDS data output 1
B_Y1N	60	O	LVDS channel B, LVDS data output 1
B_Y2P	56	O	LVDS channel B, LVDS data output 2
B_Y2N	57	O	LVDS channel B, LVDS data output 2
B_Y3P	50	O	LVDS channel B, LVDS data output 3. B_Y3P and B_Y3N must be left NC for 18-bpp panels.
B_Y3N	51	O
B_CLKP	53	O	LVDS channel B, LVDS clock output
B_CLKN	54	O	LVDS channel B, LVDS clock output
DA0P	19	I	MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps.
DA0N	20	I	MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps.
DA1P	21	I	MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
DA1N	22	I	MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
DA2P	27	I	MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps.
DA2N	28	I	MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps.
DA3P	29	I	MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps.
DA3N	30	I	MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps.
DACP	24	I	MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps.
DACN	25	I	MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps.
DB0P	4	I	MIPI D-PHY channel B, data lane 0; data rate up to 1 Gbps.
DB0N	5	I	MIPI D-PHY channel B, data lane 0; data rate up to 1 Gbps.
DB1P	6	I	MIPI D-PHY channel B, data lane 1; data rate up to 1 Gbps.
DB1N	7	I	MIPI D-PHY channel B, data lane 1; data rate up to 1 Gbps.
DB2P	10	I	MIPI D-PHY channel B, data lane 2; data rate up to 1 Gbps.
DB2N	11	I	MIPI D-PHY channel B, data lane 2; data rate up to 1 Gbps.
DB3P	12	I	MIPI D-PHY channel B, data lane 3; data rate up to 1 Gbps.
DB3N	13	I	MIPI D-PHY channel B, data lane 3; data rate up to 1 Gbps.
DBCP	8	I	MIPI D-PHY channel B, clock lane; operates up to 1 Gbps.
DBCN	9	I	MIPI D-PHY channel B, clock lane; operates up to 1 Gbps.
EN	2	I	Chip enable and reset. The device is reset (shutdown) when the EN pin is low.
GND	23	G	Reference ground
	26	G
	52	G
IRQ	33	O	Interrupt signal
REFCLK	17	I	This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI.
RSVD1	34	I/O	Reserved. This pin must be left unconnected for normal operation.
RSVD2	1	I	Reserved. This pin must be left unconnected for normal operation.
SCL	15	I	Local I²C interface clock.
SDA	16	I/O	Local I²C interface data
V_CC	3	—	1.8-V power supply
	14	—
	18	—
	32	—
	35	—
	40	—
	43	—
	48	—
	49	—
	55	—
	58	—
	63	—
VCORE	31	P	1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground.
PowerPAD		—	Reference ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.3	2.175	V
	Input voltage	CMOS input pins	–0.5	2.175	V
	Input voltage	DSI input pins (DAxP, DAxN, DBxP, and DBxN)	–0.4	1.4	V
T_A	Operating free-air temperature		–40	105	°C
T_J	Junction temperature		–40	115	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	V_CC power supply	1.65	1.8	1.95	V
V_PSN	Supply noise on any V_CC pin	ƒ_(noise) > 1 MHz		0.05	V
V_(DSI)	DSI input pin voltage	–50		1350	mV
ƒ_(I2C)	Local I²C input frequency			400	kHz
ƒ_HS(CLK)	DSI high-speed (HS) clock input frequency	40		500	MHz
t_su	DSI HS data to clock setup time; see Figure 1	0.15			UI⁽¹⁾
t_h	DSI HS data to clock hold time; see Figure 1	0.15			UI⁽¹⁾
Z_OD(LVDS)	LVDS output differential impedance	90		132	Ω
T_C	Case temperature			92.2	°C

(1) The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN65DSI85-Q1	UNIT
		PAP (HTQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	36.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.2	°C/W
R_θJB	Junction-to-board thermal resistance	20.6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.8	°C/W
ψ_JB	Junction-to-board characterization parameter	20.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
V_IL	Low-level control signal input voltage				0.3 × V_CC	V
V_IH	High-level control signal input voltage		0.7 × V_CC			V
V_OH	High-level output voltage	I_OH = –4 mA	1.25			V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
I_LKG	Input failsafe leakage current	V_CC= 0; V_CC(PIN) = 1.8 V			±30	μA
I_IH	High level input current	Any input terminal			±30	μA
I_IL	Low level input current	Any input terminal			±30	μA
I_OZ	High-impedance output current	CMOS output terminals			±10	μA
I_OS	Short-circuit output current	Any output driving GND short			±50	mA
I_CC	Device active current	See ⁽²⁾		127	232	mA
I_ULPS	Device standby current	All data and clock lanes are in ultra-low power state (ULPS)		7.7	14	mA
I_RST	Shutdown current	EN = 0		0.04	130	µA
R_EN	EN control input resistor			200		kΩ
MIPI DSI INTERFACE
V_IH-LP	LP receiver input high threshold	See Figure 2	880			mV
V_IL-LP	LP receiver input low threshold	See Figure 2			550	mV
\|V_ID\|	HS differential input voltage		100		270	mV
\|V_IDT\|	HS differential input voltage threshold				50	mV
V_IL-ULPS	LP receiver input low threshold; ultra-low power state (ULPS)				300	mV
V_CM-HS	HS common mode voltage; steady-state		70		330	mV
ΔV_CM-HS	HS common mode peak-to-peak variation including symbol delta and interference				100	mV
V_IH-HS	HS single-ended input high voltage	See Figure 2			460	mV
V_IL-HS	HS single-ended input low voltage	See Figure 2	–40			mV
V_TERM-EN	HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable)	Termination is switched simultaneous for Dn and Dp			450	mV
R_DIFF-HS	HS mode differential input impedance		80		125	Ω
LVDS OUTPUT
\|V_OD\|	Steady-state differential output voltage for A_Yx P/N and B_Yx P/N	CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 Ω near end termination	180	245	330	mV
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 Ω near end termination	215	293	392
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 Ω near end termination	250	341	455
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 Ω near end termination	290	389	515
		CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 Ω near end termination	150	204	275
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 Ω near end termination	200	271	365
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 Ω near end termination	250	337	450
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 Ω near end termination	300	402	535
\|V_OD\|	Steady-state differential output voltage for A_CLKP/N and B_CLKP/N	CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 Ω near end termination	140	191	262	mV
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 Ω near end termination	168	229	315
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 Ω near end termination	195	266	365
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 Ω near end termination	226	303	415
		CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 Ω near end termination	117	159	220
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 Ω near end termination	156	211	295
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 Ω near end termination	195	263	362
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 Ω near end termination	234	314	435
Δ\|V_OD\|	Change in steady-state differential output voltage between opposite binary states	RL = 100 Ω			35	mV
V_OC(SS)	Steady state common-mode output voltage⁽³⁾	CSR 0x19.6 = 1 and CSR 0x1B.6 = 1; and, or CSR 0x19.4 = 1 and CSR 0x1B.4 = 1; see Figure 3	0.75	0.9	1.13	V
V_OC(SS)	Steady state common-mode output voltage⁽³⁾	CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0; see Figure 3	1	1.25	1.5	V
V_OC(PP)	Peak-to-peak common-mode output voltage	see Figure 3			35	mV
R_{LVDS_DIS}	Pulldown resistance for disabled LVDS outputs			1		kΩ

(1) All typical values are at V_CC = 1.8V and T_A = 25°C

(2) SN65DSI85-Q1: DUAL Channel DSI to DUAL Channel LVDS, 1920 x 1200

number of LVDS lanes = 2 × (3 data lanes + 1 CLK lane)
number of DSI lanes = 2 × (4 data lanes + 1 CLK lane
LVDS CLK OUT = 81.6 M
DSI CLK = 490 M
RGB888, LVDS18bpp

Maximum values are at V_CC = 1.95 V and T_A = 105°C

(3) Tested at V_CC = 1.8V , T_A = –40°C for MIN, T_A = 25°C for TYP, T_A = 105°C for MAX.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
DSI
t_GS	DSI LP glitch suppression pulse width				300	ps
LVDS
t_c	Output clock period		6.49		40	ns
t_w	High-level output clock (CLK) pulse duration			4/7 t_c		ns
t₀	Delay time, CLK↑ to 1st serial bit position	t_c = 6.49 ns; Input clock jitter < 25 ps (REFCLK) See Figure 4	–0.15		0.15	ns
t₁	Delay time, CLK↑ to 2nd serial bit position		1/7 t_c – 0.15		1/7 t_c + 0.15	ns
t₂	Delay time, CLK↑ to 3rd serial bit position		2/7 t_c – 0.15		2/7 t_c + 0.15	ns
t₃	Delay time, CLK↑ to 4th serial bit position		3/7 t_c – 0.15		3/7 t_c + 0.15	ns
t₄	Delay time, CLK↑ to 5th serial bit position		4/7 t_c – 0.15		4/7 t_c + 0.15	ns
t₅	Delay time, CLK↑ to 6th serial bit position		5/7 t_c – 0.15		5/7 t_c + 0.15	ns
t₆	Delay time, CLK↑ to 7th serial bit position		6/7 t_c – 0.15		6/7 t_c + 0.15	ns
t_r	Differential output rise-time	See Figure 4	180		500	ps
t_f	Differential output fall-time	See Figure 4	180		500	ps
	LVDS CLK A to CLK B skew		–10		10	ps
EN, ULPS, RESET
t_en	Enable time from EN or ULPS; see	t_c(o) = 12.9 ns			1	ms
t_dis	Disable time to standby	t_c(o) = 12.9 ns			0.1	ms
t_reset	Reset Time		10			ms
REFCLK
F_REFCLK	REFCLK Freqeuncy. Supported frequencies: 25 MHz - 15 4MHz		25		154	MHz
t_r, t_f	REFCLK rise and fall time		100ps		1ns	s
t_pj	REFCLK Peak-to-Peak Phase Jitter				50	ps
Duty	REFCLK Duty Cycle		40%	50%	60%
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC_CLKIN	SSC enabled Input CLK center spread depth⁽²⁾		0.5%	1%	2%
SSC_CLKIN	Modulation Frequency Range		30		60	kHz

(1) All typical values are at V_CC = 1.8 V and T_A = 25°C

(2) For EMI reduction purpose, SN65DSI85-Q1 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N.

7 Parameter Measurement Information

Figure 1. DSI HS Mode Receiver Timing Definitions

SN65DSI85-Q1 DSI_Rec_Voltage_Definitions_sllsej4.gif

Figure 2. DSI Receiver Voltage Definitions

SN65DSI85-Q1 fig15_test_load_sllsej4.gif

Figure 3. Test Load and Voltage Definitions for LVDS Outputs

SN65DSI85-Q1 fig16_flatlink_timing_sllsej4.gif

Figure 4. SN65DSI85-Q1 LVDS Timing Definitions

1. See the ULPS section of the data sheet for the ULPS entry and exit sequence.

2. ULPS entry and exit protocol and timing requirements must be met according to the MIPI DPHY specification.

Figure 5. ULPS Timing Definition

8 Detailed Description

8.1 Overview

The SN65DSI85-Q1 device is an AEC-Q100 qualified, 2-channel MIPI DSI to dual-link LVDS transmitter. The device features a dual-channel MIPI D-PHY receiver front-end configurable for 1 to 4 data lanes per channel operating at 1 Gbps/lane for a maximum input bandwidth of 8 Gbps. This device decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 data stream and converts it to an LVDS output operating at pixel-clock frequencies of 25 MHz to 154 MHz. The LVDS output can be configured as a dual-link LVDS, two single-link LVDS, or a single-link LVDS output interface with four data lanes per link.