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  • SN65DSI83-Q1 汽车类单通道 MIPI® DSI 转单链路 LVDS 桥接器

    • ZHCSFS0A December   2016  – June 2018 SN65DSI83-Q1

      PRODUCTION DATA.  

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  • SN65DSI83-Q1 汽车类单通道 MIPI® DSI 转单链路 LVDS 桥接器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     SN65DSI83-Q1 原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Configurations and Multipliers
      2. 8.3.2 ULPS
      3. 8.3.3 LVDS Pattern Generation
      4. 8.3.4 Reset Implementation
      5. 8.3.5 Initialization Sequence
      6. 8.3.6 LVDS Output Formats
      7. 8.3.7 DSI Lane Merging
      8. 8.3.8 DSI Pixel Stream Packets
      9. 8.3.9 DSI Video Transmission Specifications
    4. 8.4 Programming
      1. 8.4.1 Local I2C Interface Overview
    5. 8.5 Register Maps
      1. 8.5.1 Control and Status Registers Overview
        1. 8.5.1.1 CSR Bit Field Definitions – ID Registers
          1. 8.5.1.1.1 Registers 0x00 – 0x08
            1. Table 4. Registers 0x00 – 0x08 Field Descriptions
        2. 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers
          1. 8.5.1.2.1 Register 0x09
            1. Table 5. Register 0x09 Field Descriptions
          2. 8.5.1.2.2 Register 0x0A
            1. Table 6. Register 0x0A Field Descriptions
          3. 8.5.1.2.3 Register 0x0B
            1. Table 7. Register 0x0B Field Descriptions
          4. 8.5.1.2.4 Register 0x0D
            1. Table 8. Register 0x0D Field Descriptions
        3. 8.5.1.3 CSR Bit Field Definitions – DSI Registers
          1. 8.5.1.3.1 Register 0x10
            1. Table 9. Register 0x10 Field Descriptions
          2. 8.5.1.3.2 Register 0x11
            1. Table 10. Register 0x11 Field Descriptions
          3. 8.5.1.3.3 Register 0x12
            1. Table 11. Register 0x12 Field Descriptions
        4. 8.5.1.4 CSR Bit Field Definitions – LVDS Registers
          1. 8.5.1.4.1 Register 0x18
            1. Table 12. Register 0x18 Field Descriptions
          2. 8.5.1.4.2 Register 0x19
            1. Table 13. Register 0x19 Field Descriptions
          3. 8.5.1.4.3 Register 0x1A
            1. Table 14. Register 0x1A Field Descriptions
          4. 8.5.1.4.4 Register 0x1B
            1. Table 15. Register 0x1B Field Descriptions
        5. 8.5.1.5 CSR Bit Field Definitions – Video Registers
          1. 8.5.1.5.1  Register 0x20
            1. Table 16. Register 0x20 Field Descriptions
          2. 8.5.1.5.2  Register 0x21
            1. Table 17. Register 0x21 Field Descriptions
          3. 8.5.1.5.3  Register 0x24
            1. Table 18. Register 0x24 Field Descriptions
          4. 8.5.1.5.4  Register 0x25
            1. Table 19. Register 0x25 Field Descriptions
          5. 8.5.1.5.5  Register 0x28
            1. Table 20. Register 0x28 Field Descriptions
          6. 8.5.1.5.6  Register 0x29
            1. Table 21. Register 0x29 Field Descriptions
          7. 8.5.1.5.7  Register 0x2C
            1. Table 22. Register 0x2C Field Descriptions
          8. 8.5.1.5.8  Register 0x2D
            1. Table 23. Register 0x2D Field Descriptions
          9. 8.5.1.5.9  Register 0x30
            1. Table 24. Register 0x30 Field Descriptions
          10. 8.5.1.5.10 Register 0x31
            1. Table 25. Register 0x31 Field Descriptions
          11. 8.5.1.5.11 Register 0x34
            1. Table 26. Register 0x34 Field Descriptions
          12. 8.5.1.5.12 Register 0x36
            1. Table 27. Register 0x36 Field Descriptions
          13. 8.5.1.5.13 Register 0x38
            1. Table 28. Register 0x38 Field Descriptions
          14. 8.5.1.5.14 Register 0x3A
            1. Table 29. Register 0x3A Field Descriptions
          15. 8.5.1.5.15 Register 0x3C
            1. Table 30. Register 0x3C Field Descriptions
        6. 8.5.1.6 CSR Bit Field Definitions – IRQ Registers
          1. 8.5.1.6.1 Register 0xE0
            1. Table 31. Register 0xE0 Field Descriptions
          2. 8.5.1.6.2 Register 0xE1
            1. Table 32. Register 0xE1 Field Descriptions
          3. 8.5.1.6.3 Register 0xE5
            1. Table 33. Register 0xE5 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Video STOP and Restart Sequence
      2. 9.1.2 Reverse LVDS Pin Order Option
      3. 9.1.3 IRQ Usage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Example Script
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCORE Power Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Package Specific
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

SN65DSI83-Q1 汽车类单通道 MIPI® DSI 转单链路 LVDS 桥接器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合汽车类应用的 要求
  • 具有符合 AEC-Q100 标准的下列特性：
    • 器件温度等级 2：环境工作温度范围为 –40°C 至 +105°C
    • 器件 HBM ESD 分类等级 3A
    • 器件 CDM ESD 分类等级 C6
  • 实现 MIPI®D-PHY 1.00.00 版本的物理层前端和 1.02.00 版本的显示串行接口 (DSI)
  • 单通道 DSI 接收器每通道可配置 1、2、3 或 4 条 D-PHY 数据信道，每条信道的运行速率高达 1Gbps
  • 支持 RGB666 和 RGB888 格式的 18bpp 与 24bpp DSI 视频流
  • 最大分辨率高达 60fps WUXGA 1920 × 1200（18bpp 和 24bpp 颜色，采用简化消隐）。适合 60fps 1366 × 768/1280 × 800（18bpp 和 24bpp）
  • 针对单链路 LVDS 的输出
  • 支持单通道 DSI 至单链路 LVDS 运行模式
  • LVDS 输出时钟范围为 25MHz 至 154MHz
  • LVDS 像素时钟可采用自由运行持续 D-PHY 时钟或外部基准时钟 (REFCLK)
  • 1.8V 主 VCC 电源
  • 低功耗 特性 包括关断模式、低 LVDS 输出电压摆幅、共模以及 MIPI 超低功耗状态 (ULPS) 支持
  • 针对简化印刷电路板 (PCB) 走线的 LVDS 通道交换 (SWAP)，LVDS 引脚顺序反向特性
  • 采用 64 引脚 10mm × 10mm HTQFP (PAP) 封装 PowerPAD™IC 封装

2 应用

  • 集成显示屏的信息娱乐系统主机
  • 具有远程显示屏的信息娱乐系统主机
  • 后座信息娱乐系统
  • 混合动力汽车仪表板
  • 便携式导航设备
  • 导航
  • 工业人机界面 (HMI) 和显示屏

3 说明

SN65DSI83-Q1 DSI 转 LVDS 桥接器 具有 一个单通道 MIPI D-PHY 接收器前端
配置，此配置中在每个通道上具有 4 条信道，每条信道的运行速率为 1Gbps，最大输入带宽为 4Gbps。该桥接器可解码 MIPI DSI 18bpp RGB666 和 24bpp RGB888 视频流，并将格式化视频数据流转换为 LVDS 输出（像素时钟范围为 25MHz 至 154MHz），从而提供单链路 LVDS（每个链路具有 4 个数据信道）。

SN65DSI83-Q1 器件可支持高达 WUXGA 1920 × 1200（每秒 60 帧，24bpp，采用简化消隐）的分辨率。SN65DSI83-Q1 器件还适用于 使用 60fps 1366 × 768/1280 × 800（18bpp 和 24bpp）的应用。该器件实现了部分线路缓冲以适应 DSI 与 LVDS 接口间的数据流不匹配的情况。

SN65DSI83-Q1 器件采用小外形 10mm × 10mm HTQFP
（0.5mm 间距）封装，工作温度范围为 –40ºC 至 +105ºC。

器件信息(1)

器件编号 封装 封装尺寸（标称值）
SN65DSI83-Q1 HTQFP (64) 10.00mm x 10.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

SN65DSI83-Q1 原理图

SN65DSI83-Q1 alt_sllsew7.gif

4 修订历史记录

Changes from * Revision (December 2016) to A Revision

  • Deleted figure RESET and Initialization Timing Definition While VCC is HighGo
  • Changed the paragraph following Figure 8Go
  • Changed Recommended Initialization Sequence To: Initialization SequenceGo
  • Changed Table 2Go
  • Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. Go

5 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD™
Top View
See the Layout section for layout information.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADDR 64 I/O Local I2C interface target address select. See Table 3. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI83-Q1 VCC 1.8-V power rail is connected
A_CLKP 38 O LVDS channel A, LVDS clock output
A_CLKN 39
A_Y0P 46 O LVDS channel A, LVDS data output 0
A_Y0N 47
A_Y1P 44 O LVDS channel A, LVDS data output 1
A_Y1N 45
A_Y2P 41 O LVDS channel A, LVDS data output 2
A_Y2N 42
A_Y3P 36 O LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels
A_Y3N 37
DA0P 19 I MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps
DA0N 20
DA1P 21 I MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
DA1N 22
DA2P 27 I MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps
DA2N 28
DA3P 29 I MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps
DA3N 30
DACP 24 I MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps
DACN 25
EN 2 I Chip enable and reset. The device is reset (shutdown) when the EN pin is low
GND 23, 26, 52 G Reference ground
IRQ 33 O Interrupt signal
REFCLK 17 I This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI
RSVD 4 RSVD Reserved and leave them unconnected
5
6
7
8
9
10
11
12
13
50
51
53
54
56
57
59
60
61
62
RSVD1 34 I/O Reserved. This pin must be left unconnected for normal operation
RSVD2 1 I Reserved. This pin must be left unconnected for normal operation
SCL 15 I Local I2C interface clock
SDA 16 I/O Local I2C interface data
VCC 3 — 1.8-V power supply
14
18
32
35
40
43
48
49
55
58
63
VCORE 31 P 1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground
PowerPAD — — Reference ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.3 2.175 V
Input voltage CMOS input pins –0.5 2.175 V
DSI input pins (DAxP, DAxN) –0.4 1.4 V
TA Operating free-air temperature –40 105 °C
TJ Junction temperature –40 115 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC VCC power supply 1.65 1.8 1.95 V
VPSN Supply noise on any VCC pin ƒ(noise) > 1 MHz 0.05 V
V(DSI) DSI input pin voltage –50 1350 mV
ƒ(I2C) Local I2C input frequency 400 kHz
ƒHS(CLK) DSI high-speed (HS) clock input frequency 40 500 MHz
tsu DSI HS data to clock setup time; see Figure 1 0.15 UI(1)
th DSI HS data to clock hold time; see Figure 1 0.15 UI(1)
ZOD(LVDS) LVDS output differential impedance 90 132 Ω
TC Case temperature 92.2 °C
(1) The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps.

6.4 Thermal Information

THERMAL METRIC(1) SN65DSI83-Q1 UNIT
PAP (HTQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 36.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W
RθJB Junction-to-board thermal resistance 20.6 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 20.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

 
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