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  • TPS65981 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器

    • ZHCSFF4C February   2016  – August 2021 TPS65981

      PRODUCTION DATA  

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  • TPS65981 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Requirements
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input-Output (I/O) Requirements and Characteristics
    20. 7.20 I2C Slave Requirements and Characteristics
    21. 7.21 SPI Controller Characteristics
    22. 7.22 BUSPOWERZ Configuration Requirements
    23. 7.23 Single-Wire Debugger (SWD) Timing Requirements
    24. 7.24 Thermal Shutdown Characteristics
    25. 7.25 HPD Timing Requirements and Characteristics
    26. 7.26 Oscillator Requirements and Characteristics
    27. 7.27 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5-V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink With RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink Without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C® Port Data Multiplexer
        1. 9.3.4.1 USB Top and Bottom Ports
        2. 9.3.4.2 Multiplexer Connection Orientation
        3. 9.3.4.3 SBU Crossbar Multiplexer
        4. 9.3.4.4 Signal Monitoring and Pull-up and Pull-down
        5. 9.3.4.5 Port Multiplexer Clamp
        6. 9.3.4.6 USB2.0 Low-Speed Endpoint
        7. 9.3.4.7 Battery Charger (BC1.2) Detection Block
        8. 9.3.4.8 BC1.2 Data Contact Detect
        9. 9.3.4.9 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 I2C Slave
      13. 9.3.13 SPI Controller
      14. 9.3.14 Single-Wire Debugger Interface
      15. 9.3.15 DisplayPort HPD Timers
      16. 9.3.16 ADC
        1. 9.3.16.1 ADC Divider Ratios
        2. 9.3.16.2 ADC Operating Modes
        3. 9.3.16.3 Single Channel Readout
        4. 9.3.16.4 Round-Robin Automatic Readout
        5. 9.3.16.5 One Time Automatic Readout
      17. 9.3.17 I/O Buffers
        1. 9.3.17.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.17.2 IOBUF_OD
        3. 9.3.17.3 IOBUF_PORT
        4. 9.3.17.4 IOBUF_I2C
        5. 9.3.17.5 IOBUF_GPIOHSPI
        6. 9.3.17.6 IOBUF_GPIOHSSWD
      18. 9.3.18 Thermal Shutdown
      19. 9.3.19 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
    5. 9.5 Programming
      1. 9.5.1 SPI Controller Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C® and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65981 External Flash
          2. 10.2.1.2.2 Debug Control (DEBUG_CTL) and I2C (I2C) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 USB Type-C® and PD Dock or Monitor Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 AC-DC Power Supply (Barrel Jack) Detection Circuitry
          4. 10.2.2.2.4 TPS65981 Control of Variable Buck Regulator Output Voltage (PP_HV)
          5. 10.2.2.2.5 TPS65981 and System Controller Interaction
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3 V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65981 Recommended Footprint
      2. 12.1.2  Top TPS65981 Placement and Bottom Component Placement and Layout
      3. 12.1.3  Component Placement
      4. 12.1.4  Designs Rules and Guidance
      5. 12.1.5  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      6. 12.1.6  Routing Top and Bottom Passive Components
      7. 12.1.7  Thermal Pad Via Placement
      8. 12.1.8  Top Layer Routing
      9. 12.1.9  Inner Signal Layer Routing
      10. 12.1.10 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information
  15. 重要声明
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DATA SHEET

TPS65981 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 该器件由 USB-IF 进行了 PD2.0 认证
    • 截至 2020 年 6 月，PD2.0 认证对于新设计不再适用
    • 所有需要认证的新设计应使用符合 PD3.0 的器件
    • 有关 PD2.0 与 PD3.0 的文章
  • 完全可配置的 USB PD 控制器
    • 通过 GPIO 控制外部直流/直流电源
      • 例如：TPS65981EVM
    • 端口数据多路复用器
      • USB 2.0 HS 数据和低速端点
      • 用于交替模式的边带使用数据
    • 用于为各种应用轻松配置 TPS65981 的 GUI 工具
    • 支持 DisplayPort 交替模式
    • 支持工业温度范围
    • 有关更详尽的选择指南和入门信息，请参阅 www.ti.com/usb-c 和 E2E 指南
  • 完全管理的集成电源路径：
    • 集成 5V、3A、55mΩ 电源开关
    • 集成 5V-20V、3A、95mΩ 双向负载开关
    • 适用于外部 5V-20V、5A 双向开关（背靠背 NFET）的栅极控制和电流检测
    • UL2367 认证编号：E169910-20150728
  • 集成强大的电源路径保护
    • 集成式反向电流保护、欠压保护、过压保护和压摆率可控制高压双向电源路径
    • 集成了欠压和过压保护以及限流功能，可为 5V/3A 拉电流电源路径提供浪涌电流保护
  • USB Type-C® 功率传输 (PD) 控制器
    • 8 个可配置 GPIO
    • 支持 BC1.2 充电
    • 符合 USB PD 2.0 标准
    • 符合 USB Type-C 规范
    • 线缆连接和方向检测
    • 集成式 VCONN 开关
    • 物理层和策略引擎
    • 3.3V LDO 输出，在电池电量耗尽时提供支持
    • 通过 3.3V 或 VBUS 源供电
    • 1 个 I2C 主要端口
    • 1 个 I2C 次级端口

2 应用

  • 汽车信息娱乐系统售后
  • 其他个人电子产品和工业应用
  • 医疗设备
  • 耐用 PC 和笔记本电脑
  • 集线站
  • 平板监视器

3 说明

TPS65981 是一款高度集成的独立式 USB Type-C 和电力传输 (PD) 控制器，针对笔记本电脑应用进行了优化。TPS65981 集成了全面管理的电源路径与强大的保护功能，可提供完整的 USB-C PD 解决方案。TPS65981 集成了一个高速多路复用器，该多路复用器取决于 CC 引脚提供的 USB Type-C 电缆方向。多路复用器会传递用于交替模式的边带使用数据。TPS65981 具有用于可靠制造的 QFN 封装（具有 0.5mm 间距并与 2 层 PCB 兼容），并具有扩展的（工业）温度范围。TPS65981 通过了 USB PD 2.0 认证，不可再通过 USB IF 进行认证。

器件信息(1)
器件型号 封装 封装尺寸（标称值）
TPS65981 VQFN (56) 8.00mm x 8.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-53BB2390-5C90-47FE-A157-1E90BAA69530-low.gif 简化版图表

4 Revision History

Changes from Revision B (August 2016) to Revision C (August 2021)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 更新了特性 列表Go
  • 将提到 SPI 的旧术语实例全局更改为控制器和外设Go
  • 更新了应用 列表Go
  • 更新了描述 部分Go

Changes from Revision A (April 2016) to Revision B (August 2016)

  • 将器件状态从产品预发布 更改为量产数据 Go

5 说明（续）

端口电源开关在 5V 电压下可为传统 USB 电源和 Type-C USB 电源提供高达 3A 的下行电流。当 USB PD 电源用作供电器件（主机）、受电器件（设备）或供电-受电器件时，附加的双向开关路径可在最高 20V 的电压下为其提供高达 3A 的电流。

此外，TPS65981 器件也可用作上行数据端口 (UFP)、下行数据端口 (DFP) 或者双角色数据端口。端口数据多路复用器可实现端口与顶部或底部 D+/D– 信号对之间的 USB 2.0 HS 数据传输，并且具有一个 USB 2.0 低速端点。此外，还可以将边带使用 (SBU) 信号对用于辅助或交替模式的通信（例如 DisplayPort）。

电源管理电路使用系统内部的 3.3V 电压供电，同时使用 VBUS 启动并针对电池电量耗尽或无电池情况进行供电协商。

6 Pin Configuration and Functions

GUID-9928CD19-C7C8-4F68-9C44-F325212F67A4-low.gifFigure 6-1 RTQ Package 56-Pin VQFN With Exposed Thermal PadTop View
Table 6-1 Pin Functions
PIN CATEGORY I/O TYPE POR STATE DESCRIPTION
NAME NO.
AUX_N 55 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
AUX_P 54 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
BUSPOWERZ 22 Digital Core I/O and Control Analog Input Input (Hi-Z) General-purpose digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details.
C_CC1 13 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.
C_CC2 15 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.
C_SBU1 10 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_SBU2 11 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_USB_BN 9 Type-C Port Analog I/O Hi-Z Port-side bottom USB D– connection to the port multiplexer.
C_USB_BP 8 Type-C Port Analog I/O Hi-Z Port-side bottom USB D+ connection to the port multiplexer.
C_USB_TN 7 Type-C Port Analog I/O Hi-Z Port-side top USB D– connection to the port multiplexer.
C_USB_TP 6 Type-C Port Analog I/O Hi-Z Port-side top USB D+ connection to the port multiplexer.
DEBUG_CTL1 45 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address.
DEBUG_CTL2 44 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address.
DEBUG1 2 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 15. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO0 41 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO2 25 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO3 19 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO4 26 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 4. Configured as a hot-plug detect (HPD) transistor, HPD receiver, or both when DisplayPort mode is supported. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO5 23 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 5. Can be configured as a HPD receiver when DisplayPort mode is supported. Must be tied high or low through a 1-kΩ pull-up or pull-down resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO6 20 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO7 38 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO8 1 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
HV_GATE1 31 External HV FET Control and Sense Analog Output Short to SENSEP External NFET gate control for high voltage power path. Float pin when unused.
HV_GATE2 32 External HV FET Control and Sense Analog Output Short to VBUS External NFET gate control for high voltage power path. Float pin when unused.
I2C_IRQZ 43 Digital Core I/O and Control Digital Output Hi-Z I2C port interrupt. Active low. Implement externally as an open-drain with a pull-up resistance. Float pin when unused.
I2C_SCL 47 Digital Core I/O and Control Digital I/O Digital Input I2C port serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused.
I2C_SDA 46 Digital Core I/O and Control Digital I/O Digital Input I2C port serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused.
LDO_1V8A 56 Low Current Power N/A Output of the 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
LDO_1V8D 40 Low Current Power N/A Output of the 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
LDO_3V3 51 Low Current Power N/A Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND.
LDO_BMC 48 Low Current Power N/A Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND.
MRESET 24 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1-MΩ resistor when unused in the application.
PP_5V0 27 High Current Power N/A 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused
28
PP_CABLE 14 High Current Power N/A 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
PP_HV 33 High Current Power N/A HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused
34
R_OSC 52 Digital Core I/O and Control Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
RESETZ 21 Digital Core I/O and Control Digital I/O Push-Pull Output (Low) General-purpose digital I/O 9. Active low reset output when VIN_3V3 is low (driven low on start-up). Float pin when unused.
RPD_G1 12 Type-C Port Analog I/O Hi-Z Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
RPD_G2 16 Type-C Port Analog I/O Hi-Z Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
SENSEN 29 External HV FET Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SENSEP 30 External HV FET Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SPI_CLK 37 Digital Core I/O and Control Digital Output Digital Input SPI serial clock. Connect pin directly to SPI Flash IC. Refer to the Boot Code section for more details on the SPI Flash.
SPI_POCI 35 Digital Core I/O and Control Digital Input Digital Input SPI serial controller input from peripheral. Tie pin to LDO_3V3 through a 3.3-kΩ resistor.
SPI_PICO 36 Digital Core I/O and Control Digital Output Digital Input SPI serial controller output to peripheral. Connect pin directly to SPI flash IC.
SPI_CSZ 39 Digital Core I/O and Control Digital Output Digital Input SPI chip select. Tie pin to LDO_3V3 through a 3.3-kΩ resistor.
SS 3 External HV FET Control and Sense Analog Output Driven Low Soft Start. Tie pin to capacitance CSS to ground.
SWD_CLK 50 Port Multiplexer Digital Input Resistive Pull High SWD serial clock. Float pin when unused.
SWD_DATA 49 Port Multiplexer Digital I/O Resistive Pull High SWD serial data. Float pin when unused.
USB_RP_N 5 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
USB_RP_P 4 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
VBUS 17 High Current Power N/A 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
18
VDDIO 42 Low Current Power N/A VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
VIN_3V3 53 Low Current Power N/A Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
GND (Thermal Pad) Ground Ground Hi-Z Ground. Connect directly to ground plane in accordance with the guidelines listed in the Layout Guidelines section to achieve the measured values in the Thermal Information table.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VIInput voltage(2)PP_CABLE, PP_5V0–0.36V
VIN_3V3–0.33.6
SENSEP, SENSEN(3)–0.324
VDDIO–0.3LDO_3V3 + 0.3
VIOOutput voltage(2)LDO_1V8A, LDO_1V8D, LDO_BMC, SS–0.32V
LDO_3V3–0.33.45
RESETZ, I2C _IRQ1Z, SPI_PICO, SPI_CLK, SPI_CSZ, SWD_CLK–0.3LDO_3V3 + 0.3
HV_GATE1, HV_GATE2–0.330
HV_GATE1 (relative to SENSEP)–0.36
HV_GATE2 (relative to VBUS)–0.36
VIOI/O voltage(2)PP_HV, VBUS (2)–0.324V
I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_POCI, USB_RP_P, USB_RP_N, AUX_N, AUX_P, DEBUG1, DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ, GPIO0-8–0.3LDO_3V3 + 0.3
R_OSC–0.32
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Open)–26
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Closed)–0.36
C_CC1, C_CC2, RPD_G1, RPD_G2–0.36
TJOperating junction temperature–40125°C
TstgStorage temperature–55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(3) The 24 V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (<100 ns) can occur up to 30 V.

7.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VIInput voltage(1)VIN_3V32.853.45V
PP_5V04.755.5
PP_CABLE2.955.5
PP_HV4.522
VDDIO1.73.45
VIOI/O voltage(1)VBUS422V
C_USB_PT, C_USB_NT, C_USB_PB, C_USB_NB, C_SBU1, C_SBU2–25.5
C_CC1, C_CC205.5
TAAmbient operating temperature –40105°C
TBOperating board temperature–40120°C
TJOperating junction temperature–40125°C
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

7.4 Thermal Information

THERMAL METRIC(1)TPS65981UNIT
RTQ (VQFN)
56 PINS
RθJAJunction-to-ambient thermal resistance25.2°C/W
RθJC(top)Junction-to-case (top) thermal resistance9.3°C/W
RθJBJunction-to-board thermal resistance3.6°C/W
ψJTJunction-to-top characterization parameter0.2°C/W
ψJBJunction-to-board characterization parameter3.5°C/W
RθJC(bottom)Junction-to-case (bottom) thermal resistance0.5°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Supply Requirements and Characteristics

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL
VIN_3V3Input 3.3-V supply2.853.33.45V
PP_CABLEInput voltage to power C_CC pins. This input is also available to power core circuitry2.9555.5V
VBUSBidirection DC bus voltage. Output from the TPS65981 or input to the TPS659814522V
PP_5V05-V supply input to power VBUS. This supply does not power the TPS659814.7555.5V
VDDIO(1)Optional supply for I/O cells1.73.45V
INTERNAL
VLDO_3V3DC 3.3 V generated internally by either a switch from VIN_3V3, an LDO from PP_CABLE, or an LDO from VBUS2.73.33.45V
VDO_LDO3V3Dropout voltage of LDO_3V3 from PP_CABLEILOAD = 50 mA250mV
Dropout voltage of LDO_3V3 from VBUS250500750mV
VLDO_1V8DDC 1.8 V generated for internal digital circuitry1.71.81.9V
VLDO_1V8ADC 1.8 V generated for internal analog circuitry1.71.81.9V
VLDO_BMCDC voltage generated on LDO_BMC. Setting for USB-PD1.051.1251.2V
ILDO_3V3DC current supplied by the 3.3-V LDOs. This includes internal core power and external load on LDO_3V370mA
ILDO_3V3EXExternal DC current supplied by LDO_3V330mA
ILDO_1V8DDC current supplied by LDO_1V8D. This is intended for internal loads only but small external loads may be added.50mA
ILDO_1V8DEXExternal DC current supplied by LDO_1V8D.5mA
ILDO_1V8ADC current supplied by LDO_1V8A. This is intended for internal loads only but small external loads may be added.20mA
ILDO_1V8AEXExternal DC current supplied by LDO_1V8A.5mA
ILDO_BMCDC current supplied by LDO_BMC. This is intended for internal loads only5mA
ILDO_BMCEXExternal DC current supplied by LDO_BMC0mA
VFWD_DROPForward voltage drop across VIN_3V3 to LDO_3V3 switchILOAD = 50 mA256090mV
RIN_3V3Input switch resistance from VIN_3V3 to LDO_3V3VVIN_3V3 – VLDO_3V3 > 50 mV0.51.11.75Ω
(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.

7.6 Power Supervisor Characteristics

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
UV_LDO3V3Undervoltage threshold for LDO_3V3. Locks out 1.8-V LDOsLDO_3V3 rising2.22.3252.45V
UVH_LDO3V3Undervoltage hysteresis for LDO_3V3LDO_3V3 falling2080150mV
UV_VBUS_LDOUndervoltage threshold for VBUS to enable LDOVBUS rising3.353.753.95V
UVH_VBUS_LDOUndervoltage hysteresis for VBUS to enable LDOVBUS falling2080150mV
UV_PCBLUndervoltage threshold for PP_CABLEPP_CABLE rising2.52.6252.75V
UVH_PCBLUndervoltage hysteresis for PP_PCABLEPP_CABLE falling205080mV
UV_5V0Undervoltage threshold for PP_5V0PP_5V0 rising3.53.7253.95V
UVH_5V0Undervoltage hysteresis for PP_P5V0PP_5V0 falling2080150mV
OV_VBUSOvervoltage threshold for VBUS. This value is a 6-bit programmable thresholdVBUS rising524V
OVLSB_VBUSOvervoltage threshold step for VBUS. This value is the LSB of the programmable thresholdVBUS rising328mV
OVH_VBUSOvervoltage hysteresis for VBUSVBUS falling, % of OV_VBUS0.9%1.3%1.7%
UV_VBUSUndervoltage threshold for VBUS. This value is a 6-bit programmable thresholdVBUS falling2.518.21V
UVLSB_VBUSUndervoltage threshold step for VBUS. This value is the LSB of the programmable thresholdVBUS falling249mV
UVH_VBUSUndervoltage hysteresis for VBUSVBUS rising, % of UV_VBUS0.9%1.3%1.7%
UVR_RST3V3Configurable under-voltage threshold for VRSTZ_3V3 rising. De-asserts RESETZVIN_3V3 and VRSTZ_3V3 rising (default setting)2.6132.752.888V
UVRH_RST3V3Under-voltage hysteresis for VRST_3V3 falling. Asserts RESETZVIN_3V3 and VRSTZ_3V3 falling3050mV
TUVRASSERTDelay from falling or MRESET assertion to RESETZ asserting low75μs
TUVRDELAYConfigurable delay from to RESETZ de-assertion0161.3ms

7.7 Power Consumption Characteristics

Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted(4)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IVIN_3V3Sleep(1)VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz oscillator running62µA
Idle (2)VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE = 0; 100-kHz oscillator running,
48-MHz oscillator running		2.5mA
Active(3)VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz oscillator running,
48-MHz oscillator running		6.0mA
(1) Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.
(2) Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and the digital core is clocked at 4 MHz.
(3) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all core functionality active, and the digital core is clocked at 12 MHz.
(4) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).

7.8 Cable Detection Characteristics

Recommended operating conditions; TA = -40 to 105°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IH_CC_USBSource current through each C_CC pin when in a disconnected state and configured as a DFP advertising Default USB current to a peripheral device73.68086.4μA
IH_CC_1P5Source current through each C_CC pin when in a disconnected state when configured as a DFP advertising 1.5 A to a UFP169180191μA
IH_CC_3P0Source current through each C_CC pin when in a disconnected state and configured as a DFP advertising 3 A to a UFP.VIN_3V3 ≥ 3.135 V303330356μA
VD_CCH_USBVoltage threshold for detecting a DFP attach when configured as a UFP and the DFP is advertising Default USB current source capability0.150.20.25V
VD_CCH_1P5Voltage threshold for detecting a DFP advertising 1.5-A source capability when configured as a UFP0.610.660.7V
VD_CCH_3P0Voltage threshold for detecting a DFP advertising 3 A source capability when configured as a UFP1.1691.231.29V
VH_CCD_USBVoltage threshold for detecting a UFP attach when configured as a DFP and advertising default USB current source capability.IH_CC = IH_CC_USB1.4731.551.627V
VH_CCD_1P5Voltage threshold for detecting a UFP attach when configured as a DFP and advertising 1.5-A source capabilityIH_CC = IH_CC_1P51.4731.551.627V
VH_CCD_3P0Voltage threshold for detecting a UFP attach when configured as a DFP and advertising 3-A source capability.IH_CC = IH_CC_3P0
VIN_3V3 ≥ 3.135 V		2.4232.552.67V
VH_CCA_USBVoltage threshold for detecting an active cable attach when configured as a DFP and advertising default USB current capability.0.150.20.25V
VH_CCA_1P5Voltage threshold for detecting active cables attach when configured as a DFP and advertising 1.5-A capability.0.350.40.45V
VH_CCA_3P0Voltage threshold for detecting active cables attach when configured as a DFP and advertising 3-A capability.0.760.80.84V
RD_CCPull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered.V = 1 V, 1.5 V4.855.15.35kΩ
RD_CC_OPENPull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered.V = 0 V to LDO_3V3500kΩ
RD_DBPull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when configured for dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpoweredV = 1.5 V, 2 V
RPD_Gn tied to C_CCn		4.085.16.12kΩ
RD_DB_OPENPull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when not configured for dead battery (RPD_Gn tied to GND). LDO_3V3 unpoweredV = 1.5 V, 2 V
RPD_Gn tied to GND		500kΩ
VTH_DBThreshold voltage of the pull-down FET in series with RD during dead batteryI_CC = 80 μA0.50.91.2V
R_RPDResistance between RPD_Gn and the gate of the pull-down FET255085MΩ

7.9 USB-PD Baseband Signal Requirements and Characteristics

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
COMMON
PD_BITRATEPD data-bit rate270300330Kbps
UI(1)Unit interval (1/PD_BITRATE)3.033.33 3.7μs
CCBLPLUG(2)Capacitance for a cable plug (each plug on a cable can have up to this value)25pF
ZCABLECable characteristic impedance3265Ω
CRECEIVER(3)Receiver capacitance. Capacitance looking into C_CCn pin when in receiver mode. 70120pF
TRANSMITTER
ZDRIVERTX output impedance. Source output impedance at the Nyquist frequency of USB2.0 low speed (750 kHz) while the source is driving the C_CCn line.3375Ω
TRISERise time. 10% to 90% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask.300ns
TFALLFall time. 90% to 10% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask.300ns
RECEIVER
VRXTRRx receive rising input threshold605630655mV
VRXTFRx receive falling input threshold450 470490mV
NCOUNT(4)Number of transitions for signal detection (number to count to detect non-idle bus).3
TTRANWIN(4)Time window for detecting non-idle bus.1220μs
ZBMCRXReceiver input impedanceDoes not include pull-up or pull-down resistance from cable detect. Transmitter is Hi-Z.10MΩ
TRXFILTER(5)Rx bandwidth limiting filter. Time constant of a single pole filter to limit broadband noise ingression100ns
(1) UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the transition at the start of the cell.
(2) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends to add capacitance to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle.
(5) Broadband noise ingression is because of coupling in the cable interconnect.

7.10 USB-PD TX Driver Voltage Adjustment Parameter

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted(1)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
VTXP0TX transmit peak voltage1.6151.71.785V
VTXP11.521.61.68V
VTXP21.4251.51.575V
VTXP31.331.41.47V
VTXP41.2351.31.365V
VTXP51.1881.251.312V
VTXP61.141.21.26V
VTXP71.1161.1751.233V
VTXP81.0921.151.208V
VTXP91.0681.1251.181V
VTXP101.0451.11.155V
VTXP111.0211.0751.128V
VTXP120.9981.051.102V
VTXP130.9741.0251.076V
VTXP140.9511.05V
VTXP150.9030.950.997V
(1) VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to the USB-PD Specifications.

7.11 Port Power Switch Characteristics

Recommended operating conditions; TA = –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS, when configured as a source, must not exceed 12 µF.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
RPPCCPP_CABLE to C_CCn power switch resistance312mΩ
RPP5VPP_5V0 to VBUS power switch resistance5575mΩ
RPPHVPP_HV to VBUS power switch resistance95135mΩ
IHVACTActive quiescent current from PP_HV pinEN_HV = 11mA
IHVSDShutdown quiescent current from PP_HV pinEN_HV = 0100μA
IHVEXTACTActive quiescent current from SENSEP pin,Configured as source; EN_HV = 11mA
Active quiescent current from VBUS pinConfigured as sink; EN_HV = 13.5mA
IHVEXTSDShutdown quiescent current from SENSEP pinEN_HV = 040μA
IPP5VACTActive quiescent current from PP_5V01mA
IPP5VSDShutdown quiescent current from PP_5V0100μA
ILIMHV(4)PP_HV current limit, setting 01.0071.1181.330A
PP_HV current limit, setting 11.2581.3981.638A
PP_HV current limit, setting 21.511.6781.945A
PP_HV current limit, setting 31.7611.9572.153A
PP_HV current limit, setting 52.0132.2372.46A
PP_HV current limit, setting 62.2652.5162.768A
PP_HV current limit, setting 72.5162.7963.076A
PP_HV current limit, setting 82.7683.0763.383A
PP_HV current limit, setting 93.023.3553.691A
PP_HV current limit, setting 103.2713.6353.998A
PP_HV current limit, setting 113.5233.9144.306A
PP_HV current limit, setting 123.7754.1944.613A
PP_HV current limit, setting 134.0264.4744.921A
PP_HV current limit, setting 144.2784.7535.228A
PP_HV current limit, setting 154.5295.0335.536A
PP_HV current limit, setting 165.0335.5926.151A
ILIMHVEXT(3)(4)PP_EXT current limit, setting 00.9861.121.254A
PP_EXT current limit, setting 11.2311.3991.567A
PP_EXT current limit, setting 21.4771.6781.879A
PP_EXT current limit, setting 31.7611.9572.153A
PP_EXT current limit, setting 42.0122.2362.46A
PP_EXT current limit, setting 52.2632.5152.767A
PP_EXT current limit, setting 62.5142.7943.074A
PP_EXT current limit, setting 72.7653.0733.381A
PP_EXT current limit, setting 83.0163.3523.688A
PP_EXT current limit, setting 93.2673.6313.995A
PP_EXT current limit, setting 103.5193.914.301A
PP_EXT current limit, setting 113.774.1894.608A
PP_EXT current limit, setting 124.0214.4684.915A
PP_EXT current limit, setting 134.2724.7475.222A
PP_EXT current limit, setting 144.5235.0265.529A
PP_EXT current limit, setting 155.0255.5846.143A
ILIMPP5V(4)PP_5V0 current limit, setting 01.0061.1181.330A
PP_5V0 current limit, setting 11.1321.2581.484A
PP_5V0 current limit, setting 21.2581.3981.638A
PP_5V0 current limit, setting 31.3841.5381.691A
PP_5V0 current limit, setting 41.511.6771.845A
PP_5V0 current limit, setting 51.6361.8171.999A
PP_5V0 current limit, setting 61.7611.9572.153A
PP_5V0 current limit, setting 71.8872.0972.307A
PP_5V0 current limit, setting 82.0132.2372.46A
PP_5V0 current limit, setting 92.1392.3762.614A
PP_5V0 current limit, setting 102.2652.5162.768A
PP_5V0 current limit, setting 112.392.6562.922A
PP_5V0 current limit, setting 122.5162.7963.075A
PP_5V0 current limit, setting 132.6422.9363.229A
PP_5V0 current limit, setting 142.7683.0753.383A
PP_5V0 current limit, setting 153.0193.3553.69A
ILIMPPCCPP_CABLE current limit (highest setting)0.60.750.9A
PP_CABLE current limit (lowest setting)0.350.450.55A
IHV_ACC(1)PP_HV current sense accuracy I = 100 mA, Reverse current blocking disabled3.2556.75A/V
 I = 200 mA456A/V
 I = 500 mA4.455.6A/V
 I ≥ 1 A4.555.5A/V
IHVEXT_ACCPP_EXT current sense accuracy (excluding RSENSE accuracy) I = 100 mA, RSENSE = 10 mΩ, Reverse current blocking disabled3.556.5A/V
 I = 200 mA, RSENSE = 10 mΩ456A/V
 I = 500 mA, RSENSE = 10 mΩ4.455.6A/V
 I ≥ 1 A, RSENSE = 10 mΩ4.555.5A/V
IPP5V_ACC(1)PP_5V0 current sense accuracy I = 100 mA, Reverse current blocking disabled1.9534.05A/V
 I = 200 mA2.433.6A/V
 I = 500 mA2.6433.36A/V
 I ≥ 1 A2.733.3A/V
IPPCBL_ACCPP_CABLE current sense accuracy I = 100 mA1A/V
 I = 200 mA1A/V
 I = 500 mA1A/V
IGATEEXT(2)External gate-drive current on HV_GATE1 and HV_GATE2456μA
VGSEXTVGS voltage driving external FETs4.57.5V
TON_HVPP_HV path turn on time from enable to VBUS = 95% of PP_HV voltageConfigured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 μF, ILOAD = 100 mA8ms
TON_5VPP_5V0 path turn on time from enable to VBUS = 95% of PP_5V0 voltageConfigured as a source or as a sink with soft start disabled. PP_5V0 = 5 V, CVBUS = 10 μF, ILOAD = 100 mA2.5ms
TON_CCPP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltagePP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA2ms
ISSSoft-start charging current5.578.5μA
RSS_DISSoft-start discharge resistance0.611.4kΩ
VTHSSSoft-start complete threshold1.351.51.65V
TSSDONESoft-start complete timeCSS = 220 nF31.946.260.5ms
VREVPHVReverse current blocking voltage threshold for PP_HV switch2610mV
VREVPEXTReverse current blocking voltage Threshold for PP_EXT external switches2610mV
VREV5V0Reverse current blocking voltage threshold for PP_5V0 switches2610mV
VHVDISPDVoltage threshold above VIN at which the pull-down RHVDISPD on VBUS will disable during a transition from PHV to 5V045200250mV
VSAFE0VVoltage that is a safe 0 V per USB-PD Specifications00.8V
TSAFE0VVoltage transition time to VSAFE0V650ms
VSO_HVVoltage on PP_HV or PP_HVEXT above which the PP_HV or PP_EXT to PP_5V0 transition on VBUS will meet transition requirements9.9V
SRPOSMaximum slew rate for positive voltage transitions0.03V/μs
SRNEGMaximum slew rate for negative voltage transitions–0.03V/μs
TSTABLEEN to stable time for both positive and negative voltage transitions275ms
VSRCVALIDSupply output tolerance beyond VSRCNEW during time TSTABLE–0.50.5V
VSRCNEWSupply output tolerance–55%
(1) The current sense in the ADC does not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
(2) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit events.
(3) Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. The values scale with a different RSENSE resistance and application code setting.
(4) The settings are selected automatically by application code for the current limit required in the application.

 
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