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  • DS90UB964-Q1 12 位、100MHz FPD-Link III 四路解串器集线器

    • ZHCSFB4A July   2016  – January 2024 DS90UB964-Q1

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  • DS90UB964-Q1 12 位、100MHz FPD-Link III 四路解串器集线器
  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 支持资源
    4. 7.4 Trademarks
    5. 7.5 静电放电警告
    6. 7.6 术语表
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information
  12. 重要声明
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Data Sheet

DS90UB964-Q1 12 位、100MHz FPD-Link III 四路解串器集线器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合面向汽车应用的 AEC-Q100 标准：
    • 器件温度等级 2：-40℃ 至 +105℃ 环境工作温度范围
    • 器件 HBM ESD 分类等级 ±4kV
    • 器件 CDM ESD 分类等级 C6
  • 可通过 FPD-Link III 接口聚合来自多达 4 个传感器的数据
  • 支持 100 万像素传感器，可在 30Hz 或 60Hz 帧速率下支持高清 720p/800p/960p 分辨率
  • 多摄像头同步
  • 符合 MIPI D-PHY 版本 1.2/CSI-2 版本 1.3 标准
    • 2 个 MIPI CSI-2 输出端口
    • 每个 CSI-2 端口支持 1、2、3、4 个数据通道
    • CSI-2 数据速率可扩展为每个数据通道 400Mbps/800Mbps/1.5Gbps/1.6Gbps
    • 可编程数据类型
    • 四个虚拟通道
    • ECC 和 CRC 生成
  • 支持单端同轴（包括电缆供电 (PoC)）或屏蔽双绞线 (STP) 电缆
  • 自适应接收均衡
  • 具有快速+ 模式（高达 1Mbps）的 I2C
  • 用于传感器同步和诊断的灵活 GPIO
  • 与 DS90UB933-Q1/DS90UB913A-Q1 串行器兼容
  • 内部数据路径上的 CRC 保护
  • 符合 ISO 10605 和 IEC 61000-4-2 ESD 标准

2 应用

  • 汽车 ADAS
    • 环视系统 (SVS)
    • 摄像头监控系统 (CMS)
    • 卫星雷达、飞行时间 (ToF)、激光雷达传感器模块和传感器融合
  • 安全和监控

3 说明

DS90UB964-Q1 是一款多功能传感器集线器，可通过 FPD-Link III 接口收集从 4 个独立视频数据流接收到的串行传感器数据。与 DS90UB913A-Q1/933-Q1 串行器搭配使用时，DS90UB964-Q1 可接收来自一百万像素图像传感器（可在 30Hz 或 60Hz 帧速率下支持 720p/800p/960p 分辨率）的数据。数据接收并汇总至符合 MIPI CSI-2 标准并与下游处理器互连的输出端。该器件还配有第二个 MIPI CSI-2 输出端口，可提供额外带宽或提供第二个复制输出，以便进行数据记录和并行处理。

DS90UB964-Q1 包括 4 个 FPD-Link III 解串器，每个均支持通过具有成本效益的 50Ω 单端同轴或 100Ω 差分 STP 电缆进行连接。接收均衡器会自动适应以补偿电缆损耗特性，包括随时间推移而出现的劣化。

每个 FPD-Link III 接口还包括一个单独的低延迟双向控制通道，该通道可连续传送 I2C、GPIO 和其他控制信息。通用 I/O 信号，如摄像头同步和诊断特性所需的，也可利用该双向控制通道。

DS90UB964-Q1 符合面向汽车应用的 AEC-Q100 标准，采用具有成本效益且节省空间的 64 引脚 VQFN 封装。

器件信息
器件型号封装 (1)封装尺寸（标称值）
DS90UB964-Q1VQFN (64)9.00mm x 9.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-20231106-SS0I-LHD8-LRCZ-3HLSWZX524QF-low.svg典型应用原理图

Pin Configuration and Functions

GUID-20231023-SS0I-GMXM-B9VV-MTJV6N9KGTZJ-low.svg Figure 4-1 RGC Package
64 Pin VQFN
(Top View)
Table 4-1 Pin Functions
PIN I/O
TYPE		 DESCRIPTION
NAME NO.
MIPI CSI-2 TX INTERFACE
CSI0_CLKN 22 O CSI-2 TX Port 0 differential clock output pins.
Leave unused pins as No Connect.
CSI0_CLKP 23
CSI0_D0N 24 CSI-2 TX Port 0 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI0_D0P 25
CSI0_D1N 26
CSI0_D1P 27
CSI0_D2N 28
CSI0_D2P 29
CSI0_D3N 30
CSI0_D3P 31
CSI1_CLKN 34 O CSI-2 TX Port 1 differential clock output pins.
Leave unused pins as No Connect.
CSI1_CLKP 35
CSI1_D0N 36 CSI-2 TX Port 1 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI1_D0P 37
CSI1_D1N 38
CSI1_D1P 39
CSI1_D2N 40
CSI1_D2P 41
CSI1_D3N 42
CSI1_D3P 43
FPD-LINK III RX INTERFACE
RIN0+ 50 I/O FPD-Link III RX Port 0 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 0 to 0 to disable RX Port 0 and leave the pins as No Connect.
RIN0- 51
RIN1+ 53 FPD-Link III RX Port 1 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 1 to 0 to disable RX Port 1 and leave the pins as No Connect.
RIN1- 54
RIN2+ 59 FPD-Link III RX Port 2 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 2 to 0 to disable RX Port 2 and leave the pins as No Connect.
RIN2- 60
RIN3+ 62 FPD-Link III RX Port 3 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 3 to 0 to disable RX Port 3 and leave the pins as No Connect.
RIN3- 63
GENERAL-PURPOSE I/O
GPIO0 9 I/O, PD General-Purpose Input/Output pins. The pins can be used to control and respond to various commands. The pins can be configured to be input signals for the corresponding GPIOs on the serializer, or the pins can be configured to be outputs to follow local register settings. At power up, the GPIO pins are disabled and by default include a pulldown resistor (25kΩ typical).
See Section 5.4.9. for programmability. If unused, leave the pin as No Connect.
GPIO1 10
GPIO2 14
GPIO3 15
GPIO4 17
GPIO5 18
GPIO6 19
GPIO7 20
SERIAL CONTROL BUS (I2C)
I2C_SCL 12 I/O, OD Primary I2C Clock Input / Output interface pin. See Section 5.5.1.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SDA 11 I/O, OD Primary I2C Data Input / Output interface pin. See Section 5.5.1.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SCL2 8 I/O, OD Secondary I2C Clock Input / Output interface pin. See Section 5.5.2.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SDA2 7 I/O, OD Secondary I2C Data Input / Output interface pin. See Section 5.5.2.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
CONFIGURATION AND CONTROL
IDX 46 S I2C Serial Control Bus Device ID Address Select configuration pin.
Connect to an external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 5-13.
MODE 45 S Mode Select configuration pin.
Connect to external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 5-2.
PDB 3 I, PD Inverted Power-Down input pin. Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low powers down the device and consumes minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an internal 50kΩ internal pulldown enabled. PDB must remain low until after power supplies are applied and reach minimum required levels. See Section 6.4.1.
INPUT IS 3.3V TOLERANT
PDB = 1.8V or 3.3V, device is enabled (normal operation)
PDB = 0V, device is powered down.
POWER AND GROUND
VDDIO 16 P 1.8V (±5%) OR 3.3V (±10%) LVCMOS I/O Power
Recommend 1μF, 0.1F, and 0.1μF or 0.01μF capacitors to GND (see Section 6.2)
VDD_CSI0
VDD_CSI1		 21
33		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 1μF decoupling is recommended for the pin group (see Section 6.2)
VDDL1
VDDL2		 13
44		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD_FPD1
VDD_FPD2		 52
61		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18_P2
VDD18_P3
VDD18_P1
VDD18_P0		 2
1
47
48		 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18A 32 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF, and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18_FPD0
VDD18_FPD1
VDD18_FPD2
VDD18_FPD3		 49
55
58
64		 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF, 1μF, and 10uF decoupling is recommended for the pin group (see Section 6.2)
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
OTHERS
INTB 6 O, OD Interrupt Output pin.
INTB is an active-low open drain and controlled by the status registers. See Section 5.5.9.
Recommend a 4.7kΩ Pullup to 1.8V or 3.3V. If unused, leave the pin as No Connect.
REFCLK 5 I Reference clock oscillator input.
Typically connected to a 23MHz to 25MHz LVCMOS-level oscillator (100 ppm).
For 400Mbps, 800Mbps or 1.6Gbps CSI-2 data rates, use 25MHz frequency. For <1.5Gbps operation use 23MHz (1.47Gbps)
For the oscillator requirements, see Section 5.4.3. For other common CSI-2 data rates, see Section 5.4.18.
RES 4 - This pin must be tied to GND for normal operation.
CMLOUTP 56 O Channel Monitor Loop-through Driver differential output.
Route to a test point or a pad with 100Ω termination resistor between pins for channel monitoring (recommended). See Section 5.4.7.
CMLOUTN 57
The definitions below define the functionality of the I/O cells for each pin. TYPE:
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Strap Input
  • PD = Internal Pulldown
  • OD = Open Drain
  • P = Power Supply
  • G = Ground

4 Specifications

4.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage VDD11 –0.3 1.8 V
VDD18 –0.3 2.5 V
VDDIO –0.3 4 V
LVCMOS IO voltage –0.3 VDDIO + 0.3 V
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office or Distributors for availability and specifications.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings – JEDEC

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) RIN[3:0]+, RIN[3:0]- ±8000 V
Other pins ±4000
Charged device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4.3 ESD Ratings – IEC and ISO

VALUE UNIT
V(ESD) Electrostatic discharge ESD Rating (IEC 61000-4-2)
RD= 330 Ω, CS = 150 pF		 Contact Discharge
(RIN[3:0]+, RIN[3:0]-)		 ±8000 V
Air Discharge
(RIN[3:0]+, RIN[3:0]-)		 ±18000
ESD Rating (ISO 10605)
RD= 330 Ω, CS = 150 pF and 330 pF
RD= 2 kΩ, CS = 150 pF and 330 pF		 Contact Discharge
(RIN[3:0]+, RIN[3:0]-)		 ±8000 V
Air Discharge
(RIN[3:0]+, RIN[3:0]-)		 ±18000

4.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage VDD11 1.045 1.1 1.155 V
VDD18 1.71 1.8 1.89 V
LVCMOS supply voltage VDDIO 1.8V Option 1.71 1.8 1.89 V
3.3V Option 3.0 3.3 3.6 V
Operating free-air temperature, TA –40 25 105 °C
MIPI data rate (per CSI-2 lane) 400 800 1600 Mbps
MIPI CSI-2 HS clock frequency 200 400 800 MHz
Local I2C frequency, fI2C 1 MHz
Supply Noise(1) VDD11 25 mVP-P
VDD18 50 mVP-P
VDDIO 1.8V Option 50 mVP-P
3.3V Option 100 mVP-P
(1) Supply noise testing was performed with minimum capacitors (as shown in the Typical Application Diagram). A sinusoidal signal is AC coupled from DC to 10 MHz to the VDD11, VDD18, and VDDIO (1.8V / 3.3V) supply pins with amplitude of 25 mVp-p, 50 mVp-p, and 50 mVp-p / 100 mVp-p respectively measured at the device VDD pins.

4.5 Thermal Information

THERMAL METRIC(1) DS90UB964-Q1 UNIT
RGC (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 25.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.8 °C/W
RθJB Junction-to-board thermal resistance 4.8 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.6 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT
1.8 V LVCMOS I/O
(VDDIO = 1.8 V ± 5%)
VIH High Level Input Voltage GPIO[7:0], PDB, REFCLK 0.65 ×
VDDIO		 VDDIO V
VIL Low Level Input Voltage GND 0.35 ×
VDDIO		 V
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Enabled GPIO[7:0](1), PDB –20 150 μA
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Disabled GPIO[7:0](1) –20 20 μA
IIL Input Low Current VIN = 0 V or VDDIO GPIO[7:0](1), PDB
–20

 20 μA
VOH High Level Output Voltage IOH = –2 mA GPIO[7:0] VDDIO – 0.45 VDDIO V
VOL Low Level Output Voltage IOL = 2 mA GPIO[7:0], INTB GND 0.45 V
IOS Output Short Circuit Current VOUT = 0 V GPIO[7:0] –35 mA
IOZ TRI-STATE Output Current VOUT = 0 V or VDDIO, PDB = LOW GPIO[7:0] –20 20 μA
3.3 V LVCMOS I/O
(VDDIO = 3.3 V ± 10%)
VIH High Level Input Voltage GPIO[7:0] 2 VDDIO V
VIH REFCLK, PDB 1.17 VDDIO
VIL Low Level Input Voltage GPIO[7:0] GND 0.8 V
VIL REFCLK, PDB GND 0.63
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Enabled GPIO[7:0](1), PDB –20 200 μA
IIH Input High current VIN = 0 V or VDDIO Internal Pulldown Disabled GPIO[7:0](1) –20 20 μA
IIL Input Low current  VIN = 0 V or VDDIO GPIO[7:0](1), PDB –20 20 μA
VOH High Level Output Voltage IOH = –4 mA GPIO[7:0] 2.4 VDDIO V
VOL Low Level Output Voltage IOL = 4 mA GPIO[7:0], INTB GND 0.4 V
IOS Output Short Circuit Current VOUT = 0 V GPIO[7:0] –50 mA
IOZ TRI-STATE Output Current VOUT = 0 V or VDDIO, PDB = LOW GPIO[7:0] –20 20 μA
I2C SERIAL CONTROL BUS (VDDIO = 1.8 V ± 5%
OR 3.3 V ± 10%)
VIH Input High Level I2C_SDA, I2C_SCL
I2C_SDA2, I2C_SCL2		 0.7 × VDDIO VDDIO V
VIL Input Low Level GND 0.3 × VDDIO V
VHY Input Hysteresis >50 mV
VOL Output Low Level IOL = 4 mA Standard-mode
Fast-mode		 0 0.4 V
IOL = 15 mA Fast-mode Plus 0 0.4 V
IIN Input Current VIN = 0 V or VDDIO –10 10 µA
FPD-LINK III
RECEIVER INPUT
VIN Single-ended Input Voltage  (Figure 5-2) RIN0±, RIN1±,
RIN2±, RIN3±		 60 mV
VID Differential Input Voltage (Figure 5-2) RIN0±, RIN1±,
RIN2±, RIN3±		 115 mV
VCM Common Mode Voltage 1.0 V
IIZ Power-down input current PDB = LOW –10 –10 μA
RT Internal Termination Resistance Single-ended RIN+ or RIN- 40 50 60 Ω
Differential across RIN+ and RIN- 80 100 120 Ω
FPD-LINK III
BI-DIRECTIONAL CONTROL CHANNEL
VOUT-BC Back Channel Single-Ended Output Voltage RL = 50 Ω
Coaxial configuration
Forward channel disabled		 RIN0+, RIN1+
RIN2+, RIN3+		 +190 +220 +260 mV
RIN0-, RIN1-
RIN2-, RIN3-		 –190 –220 –260
VOD-BC Back Channel Differential Output Voltage (RIN+) - (RIN-) RL = 100 Ω
STP configuration
Forward channel disabled		 RIN0±,
RIN1±,
RIN2±,
RIN3±		 380 440 520 mV
HSTX DRIVER
VCMTX HS transmit static common-mode voltage CSI0_D[3:0]P/N,
CSI0_CLKP/N,
CSI1_D[3:0]P/N,
CSI1_CLKP/N		 150 200 250 mV
|ΔVCMTX(1,0)| VCMTX mismatch when output is 1 or 0 5 mVP-P
|VOD| HS transmit differential voltage 140 200 270 mV
|ΔVOD| VOD mismatch when output is 1 or 0 14 mV
VOHHS HS output high voltage 360 mV
ZOS Single-ended output impedance 40 50 62.5 Ω
ΔZOS Mismatch in single-ended output impedance 10 %
LPTX DRIVER
VOH High Level Output Voltage IOH = –4 mA CSI0_D[3:0]P/N,
CSI0_CLKP/N,
CSI1_D[3:0]P/N,
CSI1_CLKP/N		 1.1 1.2 1.3 V
VOL Low Level Output Voltage IOL = 4 mA –50 50 mV
ZOLP Output impedance 110 Ω
POWER CONSUMPTION
PT Total Power Consumption in Operation Mode CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Non-Replicate>
Default registers		 1100 mW
SUPPLY CURRENT
IDDT1 DPHY TX Supply Current (includes load current) CSI-2 data rate = 800 Mbps
4 × FPD-Link III RX inputs
CSI-2 TX = 1 data lanes + 1 CLK lane
<Non-Replicate>
Default registers		 VDD11 90 275 mA
VDD18 177 240
VDDIO 10 50
CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 1 data lanes + 1 CLK lane
<Non-Replicate>
Default registers		 VDD11 100 280 mA
VDD18 177 240
VDDIO 10 50
IDDT2 DPHY TX Supply Current (includes load current) CSI-2 data rate = 800 Mbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Replicate Mode>
Default registers		 VDD11 105 285 mA
VDD18 180 240
VDDIO 10 50
CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Replicate Mode>
Default registers		 VDD11 120 380 mA
VDD18 180 240
VDDIO 10 50
IDDZ Standby Current PDB = LOW VDD11 100 mA
VDD18 1
VDDIO 3
(1) GPIO[7:0] Register 0xBE = 0xFF

4.7 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT
LVCMOS I/O
tCLH LVCMOS Low-to-High Transition Time VDDIO: 1.71 V to 1.89 V
OR
VDDIO: 3.0 V to 3.6 V
CL = 8 pF (lumped load)
Default Registers (Figure 5-1)		 GPIO[7:0] 2.5 ns
tCHL LVCMOS High-to-Low Transition Time GPIO[7:0] 2.5 ns
FPD-LINK III RECEIVER INPUT
tDDLT Deserializer Data Lock Time With Adaptive Equalization (Figure 5-3) RIN0±, RIN1±,
RIN2±, RIN3±		 15 22 ms
tIJIT Input Jitter Jitter Frequency > FPD3_PCLK(1) / 15 0.4 UI
(1) FPD3_PCLK is equivalent to PCLK frequency based on the operating MODE:
10-bit mode: PCLK_Freq. /2
12-bit HF mode: PCLK_Freq. x 2/3
12-bit LF mode: PCLK_Freq.

4.8 Recommended Timing for the Serial Control Bus

Over I2C supply and temperature ranges unless otherwise specified.
PARAMETER STANDARD-MODE FAST-MODE FAST-MODE PLUS UNIT
MIN MAX MIN MAX MIN MAX
I2C SERIAL CONTROL BUS (Figure 5-4)
fSCL SCL Clock Frequency >0 100 >0 400 >0 1000 kHz
tLOW SCL Low Period 4.7 1.3 0.5 µs
tHIGH SCL High Period 4.0 0.6 0.26 µs
tHD;STA Hold time for a start or a repeated start condition 4.0 0.6 0.26 µs
tSU;STA Set Up time for a start or a repeated start condition 4.7 0.6 0.26 µs
tHD;DAT Data Hold Time 0 0 0 µs
tSU;DAT Data Set Up Time 250 100 50 ns
tSU;STO Set Up Time for STOP Condition 4.0 0.6 0.26 µs
tBUF Bus Free Time Between STOP and START 4.7 1.3 0.5 µs
tr SCL & SDA Rise Time 1000 300 120 ns
tf SCL & SDA Fall Time 300 300 120 ns
Cb Capacitive Load for Each Bus Line 400 400 550 pF
tSP Input Filter - 50 50 ns

4.9 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
HSTX DRIVER
HSTXDBRData rateCSI0_D[3:0]P/N
CSI1_D[3:0]P/N		4008001600Mbps
fCLKDDR Clock frequencyCSI0_CLKP/N
CSI1_CLKP/N		200400800MHz
ΔVCMTX(HF)Common mode voltage variations HFAbove 450MHzCSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI0_CLKP/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI1_CLKP/N		15mVRMS
ΔVCMTX(LF)Common mode voltage variations LFBetween 50 and 450MHz25mVRMS
tRHS
tFHS		20% to 80% Rise and Fall HSHS data rates ≤ 1Gbps (UI ≥ 1ns)0.3UI
HS data rates > 1Gbps (UI ≤ 1ns) but less than 1.5Gbps (UI ≥ 0.667ns)0.35UI
Applicable when supporting maximum HS data rates ≤ 1.5Gbps.100ps
Applicable for all HS data rates when supporting > 1.5Gbps.0.4UI
Applicable for all HS data rates when supporting > 1.5Gbps.50ps
SDDTXTX differential return lossfLPMAXHS data rates <1.5Gbps-18dB
fH-9dB
fMAX-3dB
fLPMAXHS data rates >1.5Gbps-18dB
fH-4.5dB
fMAX-2.5dB
LPTX DRIVER
tRLPRise Time LP(1)15% to 85% rise timeCSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		25ns
tFLPFall Time LP (1)15% to 85% fall time25ns
tREOTRise Time Post-EoT(1)30%-85% rise time35ns
tLP-PULSE-TXPulse width of the LP exclusive-OR clock(1)First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state40ns
All other pulses20ns
tLP-PER-TXPeriod of the LP exclusive-OR clock90ns
DV/DtSRSlew rate (1)CLOAD = 0 pF500mV/ns
CLOAD = 5 pF300mV/ns
CLOAD = 20 pF250mV/ns
CLOAD = 70 pF150mV/ns
CLOAD = 0 to 70 pF (Falling Edge Only)30mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only)30mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only) (2)(3)30 - 0.075×(VO,INST - 700)mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only) (4)(5)25 - 0.0625×(VO,INST - 500)mV/ns
CLOADLoad capacitance(1)070pF
CSI-2 TIMING SPECIFICATIONS — DATA-CLOCK TIMING (Figure 4-6, Figure 4-7)
UIINSTUI instantaneousIn 1, 2, 3, or 4 Lane Configuration
HS Data rate = 400 Mbps		CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		2.5ns
In 1, 2, 3, or 4 Lane Configuration
HS Data rate = 800 Mbps		1.25ns
In 1, 2, 3, or 4 Lane Configuration
HS Data rate = 1.6Gbps		0.625ns
ΔUIUI variationUI ≥ 1ns (Figure 4-5)-10%10%UI
UI < 1ns (Figure 4-5)-5%5%UI
tSKEW(TX)Data to Clock Skew (measured at transmitter)
Skew between clock and data from ideal center		HS Data rate ≤ 1Gbps (Figure 4-5)-0.150.15UIINST
1Gbps ≤ HS Data rate ≤ 1.5Gbps (Figure 4-5)-0.20.2UIINST
tSKEW(TX) staticStatic Data to Clock SkewHS Data rate > 1.5Gbps-0.20.2UIINST
tSKEW(TX) dynamicDynamic Data to Clock SkewHS Data rate > 1.5Gbps-0.150.15UIINST
CSI-2 TIMING SPECIFICATIONS - GLOBAL OPERATION (Figure 4-6, Figure 4-7)
tCLK-POSTHS exit CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		60 + 52×UIINSTns
tCLK-PRETime HS clock shall be driver prior to any associated Data Lane beginning the transition from LP to HS mode8UIINST
tCLK-PREPAREClock Lane HS Entry3895ns
tCLK-SETTLETime interval during which the HS receiver shall ignore any Clock Lane HS transitions95300ns
tCLK-TERM-ENTime-out at Clock Lane Display Module to enable HS TerminationTime for Dn to reach VTERM-EN38ns
tCLK-TRAILTime that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst 60ns
tCLK-PREPARE + tCLK-ZEROTCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock 300ns
tD-TERM-ENTime for the Data Lane receiver to enable the HS line termination Time for Dn to reach V-TERM-EN35 + 4×UIINSTns
tEOTTransmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst 105 + 12×UIINSTns
tHS-EXITTime that the transmitter drives LP=11 following a HS burst 100ns
tHS-PREPAREData Lane HS Entry 40 + 4×UIINST85 + 6×UIINSTns
tHS-PREPARE + tHS-ZEROtHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence 145 + 10×UIINSTns
tHS-SETTLETime interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of tHS-SETTLE 85 + 6×UIINST145 + 10×UIINSTns
tHS-SKIPTime interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 4055 + 4×UIINSTns
tHS-TRAILData Lane HS Exit 60 + 4×UIINSTns
tLPXTransmitted length of LP state 50ns
tWAKEUPRecovery Time from Ultra Low Power State (ULPS) 1ms
(1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
(2) When the output voltage is between 700 mV and 930 mV
(3) Applicable when the supported data rate ≤ 1.5Gbps
(4) When the output voltage is between 550 mV and 790 mV
(5) Applicable when the supported data rate > 1.5Gbps.
GUID-FC176185-C4B6-4097-AB19-63D3C865A5BB-low.gifFigure 4-1 LVCMOS Transition Times
GUID-FC0738FF-C4C1-4EE1-831A-882466AD26EE-low.gifFigure 4-2 FPD-Link III Receiver VID, VIN, VCM
GUID-A14DEEEE-7B4B-49D6-979D-D27F0B1FD2CA-low.gifFigure 4-3 Deserializer Data Lock Time
GUID-13334ADD-FE8D-445B-800E-A18408BC8ABF-low.gifFigure 4-4 I2C Serial Control Bus Timing
GUID-6CD216E9-A92A-4A09-8BD3-854DD228A8BB-low.gifFigure 4-5 Clock and Data Timing in HS Transmission
GUID-726C8505-78BC-47F8-AB88-AD132CE03549-low.gifFigure 4-6 Switching the Clock Lane Between Clock Transmission and Low-Power Mode
GUID-E3C97C66-56D8-4074-A27C-290B0C57EA7E-low.gifFigure 4-7 High-Speed Data Transmission Burst
GUID-486CDEF9-48AA-49A5-A693-DA5D36074645-low.gifFigure 4-8 Long Line Packets and Short Frame Sync Packets
GUID-07B689DF-98EB-470E-B22D-F1F1B55058FC-low.svgFigure 4-9 CSI-2 General Frame Format (Single Rx / VC)
GUID-29433953-5FB4-46B2-97F8-BFB464AF67CC-low.pngFigure 4-10 4 MIPI Data Lane Configuration

4.10 Typical Characteristics

GUID-66AB024C-04A3-4906-8AB8-D4839F7F6BEF-low.gifFigure 4-11 CSI-2 Start of Transmission (SoT)
GUID-0D6706E7-8C53-43EA-A5E0-0E6FB306ED8C-low.gifFigure 4-12 CSI-2 End of Transmission (EoT)

 
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