DATA SHEET
SN65DP141 DisplayPort 线性转接驱动器
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1 特性
- 支持 VESA DisplayPort 1.4a、
2.0 和 eDP 1.4 - 四通道线性转接驱动器，支持高达 12Gbps 的数据速率，包括 DisplayPort RBR、HBR、HBR2、HBR3 和 UHBR10
- 与协议无关
- 透明呈现 DP 链路训练
- 与在链路上的位置无关，适用于源端、接收端和电缆应用
- 6GHz 时模拟均衡为 15dB
- 输出线性动态范围：1200mV
- 带宽：>20 GHz
- 6GHz 时的回波损耗优于 16dB
- 2.5V 或 3.3V ±5% 单电源选项
- 低功耗，2.5V VCC 时每通道 80mW
- GPIO 或 I2C 控制
3 说明
SN65DP141 是一款与协议无关的异步、低延迟、四通道线性均衡器，该器件经过优化适用于高达 12Gbps 的数据速率并且可对电路板走线和电缆所产生的损耗进行补偿。
该器件透明呈现 DisplayPort (DP) 链路训练，这使得 DP 发送设备和接收设备能够执行有效的链路训练，克服了传统 aux snooping 转接驱动器的缺点。此外，该器件与位置无关。它可置于源设备、电缆或接收设备内，从而为总体链路预算有效提供负损耗 分量。SN65DP141 内的线性均衡在与接收器搭配使用时还可提高链路裕度，从而实现判决反馈均衡 (DFE)。
SN65DP141 支持采用 I2C 和 GPIO 配置对均衡、增益、动态范围进行独立通道控制。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| SN65DP141 | WQFN (38) | 7.00mm × 5.00mm |
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化版原理图4 Revision History
Changes from Revision B (September 2021) to Revision C (December 2021)
- Changed the I2C_EN pin Type from internal pull-up to internal pull-down Go
Changes from Revision A (October 2016) to Revision B (September 2021)
- 更新了整个文档中的表格、图和交叉参考的编号格式Go
- 将特性从：“支持 VESA DisplayPort 1.3 和 eDP 1.4”更新为：“支持 VESA DisplayPort 1.4a、2.0 和 eDP 1.4”Go
- 将特性从“包括 DisplayPort RBR、HBR、HBR2 和 HBR3”更新为“包括 DisplayPort RBR、HBR、HBR2、HBR3 和 UHBR10”Go
- Updated the DP bit rates from: RBR to HBR3 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps ... to: RBR to UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps and 10.0 Gbps … in the Overview sectionGo
- Updated Operating data rate from HBR3 (8.1 Gbps) to UHBR10 (10 Gbps)Go
Changes from Revision * (February 2016) to Revision A (October 2016)
- Replaced Figure 9-2 Go
5 Pin Configuration and Functions
It is required for the thermal
pad to be soldered to ground for better thermal performance.
Figure 5-1 RLJ Package38 Pins (WQFN)Top ViewTable 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | ||||||
|---|---|---|---|---|---|---|---|---|
| NAME | NO. | |||||||
| DIFFERENTIAL HIGH-SPEED I/O | ||||||||
| IN0_P | 1 | I | Differential input, lane 0 (with 50 Ω termination to input common mode) | |||||
| IN0_N | 2 | I | ||||||
| IN1_P | 4 | I | Differential input, lane 1 (with 50 Ω termination to input common mode) | |||||
| IN1_N | 5 | I | ||||||
| IN2_P | 8 | I | Differential input, lane 2 (with 50 Ω termination to input common mode) | |||||
| IN2_N | 9 | I | ||||||
| IN3_P | 11 | I | Differential input, lane 3 (with 50 Ω termination to input common mode) | |||||
| IN3_N | 12 | I | ||||||
| OUT0_P | 31 | O | Differential output, lane 0 | |||||
| OUT0_N | 30 | O | ||||||
| OUT1_P | 28 | O | Differential output, lane 1 | |||||
| OUT1_N | 27 | O | ||||||
| OUT2_P | 24 | O | Differential output, lane 2 | |||||
| OUT2_N | 23 | O | ||||||
| OUT3_P | 21 | O | Differential output, lane 3 | |||||
| OUT3_N | 20 | O | ||||||
| CONTROL SIGNALS | ||||||||
| DRV_PK#/SCL | 15 | I (with 200-kΩ internal pull-up) |
GPIO mode: HIGH: disable Driver peaking LOW: enables Driver 6-dB AC peaking |
I2C mode: I2C CLK. Connect a 10-kΩ pull-up resistor externally. |
||||
| EQ_MODE/ ADD2 | 35 | I (with 200-kΩ Internal pull-down, 2.5 V/3.3 V CMOS ) |
GPIO mode: HIGH: Trace mode LOW: Cable mode |
I2C mode: ADD2 along with pins ADD1 and ADD0 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX |
||||
| EQ0/ADD0 | 33 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with RX_GAIN and EQ1 to determine the receiver DC and AC gain. |
I2C mode: ADD0 along with pins ADD1 and ADD2 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX |
||||
| EQ1/ADD1 | 34 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with RX_GAIN and EQ0 to determine the receiver DC and AC gain. |
I2C mode: ADD1 along with pins ADD0 and ADD2 comprise the three bits of I2C slave address ADD2:ADD1:ADD0:XXX |
||||
| I2C_EN | 16 | I (with 200-kΩ internal pull-down) |
Configures the device operation for I2C
or GPIO mode: HIGH: enables I2C mode LOW: enables GPIO mode |
|||||
| PWD# | 37 | I (with 200-kΩ Internal pull-up, 2.5 V/3.3 V CMOS) |
HIGH: Normal Operation LOW: Power downs the device, inputs off and outputs disabled, resets I2C |
|||||
| REXT | 18 | I (analog) | External Bias Resistor: 1,200 Ω to GND | |||||
| RX_GAIN | 36 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with EQ0 and EQ1 to determine the receiver DC and AC gain. |
I2C mode: No action needed |
||||
| SDA | 14 | I/O (open drain) | GPIO mode: No action needed. |
I2C mode: I2C data. Connect a 10-kΩ pull-up resistor externally. |
||||
| TX_DC_GAIN/CS | 17 | I (with 200-kΩ Internal pull-down, 2.5 V/3.3 V CMOS) |
GPIO mode: HIGH: 6 dB DC gain for transmitter LOW: 0 dB DC gain for transmitter |
I2C mode: HIGH: acts as Chip Select LOW: disables I2C interface |
||||
| POWER SUPPLY | ||||||||
| GND Center Pad | Ground | The ground center pad is the metal contact at the bottom of the package. This pad must be connected to the GND plane. At least 15 PCB vias are recommended to minimize inductance and provide a solid ground. Refer to the package drawing (RLJ-package) for the via placement. | ||||||
| VCC | 3, 6, 7, 10, 13, 19, 22, 25, 26, 29, 32, 38 | Power | Power supply 2.5 V ±5%, 3.3 V ±5% | |||||
(1) I = input, O = output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage range | VCC | –0.3 | 4 | V |
| Differential voltage between INx_P and INx_N | VIN, DIFF | –2.5 | 2.5 | V |
| Voltage at INx_P and INx_N, | VIN+, IN– | –0.5 | VCC + 0.5 | V |
| Voltage on control IO pins,VIO | –0.5 | VCC + 0.5 | V | |
| Continuous current at high speed differential data inputs(differential) | IN+, IN– | –25 | 25 | mA |
| Continuous current at high speed differential data outputs | IOUT+, IOUT– | –25 | 25 | mA |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| DR | Operating data rate | 12 | Gbps | ||
| VCC | Supply voltage | 2.375 | 2.5/3.3 | 3.465 | V |
| TC | Junction temperature | –10 | 125 | °C | |
| TA | Operating free-air temperature | –40 | 85 | °C | |
| CMOS DC SPECIFICATIONS | |||||
| VIH | Input high voltage | 0.8 x VCC | V | ||
| V(MID) | Input middle voltage | VCC x 0.4 | VCC x 0.6 | V | |
| VIL | Input low voltage | –0.5 | 0.2 x VCC | V | |
6.4 Thermal Information
| THERMAL METRIC(1) | SN65DP141 | UNIT | |
|---|---|---|---|
| RLJ (WQFN) | |||
| 38 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 36.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 22.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 10.7 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
| ψJB | Junction-to-board characterization parameter | 10.6 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.9 | °C/W |
(1) For more information about traditional and new thermal
metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER CONSUMPTION | ||||||
| PDL | Device Power dissipation | VOD = Low, VCC = 3.3 V and all 4 channels active | 450 | 625 | mW | |
| VOD = Low, VCC = 2.5 V and all 4 channels active | 317 | 475 | mW | |||
| PDH | Device Power dissipation | VOD = High, VCC = 3.3 V and all 4 channels active | 697 | 925 | mW | |
| VOD = High, VCC = 2.5 V and all 4 channels active | 485 | 675 | mW | |||
| PDOFF | Device power with all 4 channels switched off | Refer to I2C section for device configuration | 10 | mW | ||
| CMOS DC SPECIFICATIONS | ||||||
| IIH | High level input current | VIN = 0.9 × VCC | -40 | 17 | 40 | µA |
| IIL | Low level input current | VIN = 0.1 × VCC | -40 | 17 | 40 | µA |
| CML INPUTS (IN[3:0]_P, IN[3:0]_N) | ||||||
| RIN | Differential input resistance | INx_P to INx_N | 100 | Ω | ||
| VIN | Input linear dynamic range | Gain = 0.5 | 1200 | mVpp | ||
| VICM | Input common mode voltage | Internally biased | VCC – 0.8 | V | ||
| SCD11 | Input differential to common mode conversion | 100 MHz to 6 GHz | -20 | dB | ||
| SDD11 | Differential input return loss | 100 MHz to 6 GHz | -15 | dB | ||
| CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N) | ||||||
| VOD | Output linear dynamic range | RL = 100 Ω, VOD = HIGH | 1200 | mVpp | ||
| RL = 100 Ω, VOD = LOW | 600 | mVpp | ||||
| VOS | Output offset voltage | RL = 100 Ω, 0 V applied at inputs | 10 | mVpp | ||
| VOCM | Output common mode voltage | VCC – 0.4 | V | |||
| VCM(RIP) | Common mode output ripple | K28.5 pattern at 12 Gbps on all 4 channels, No interconnect loss, VOD = HIGH | 10 | 20 | mVRMS | |
| VOD(RIP) | Differential path output ripple | K28.5 pattern at 12 Gbps on all channels, No interconnect loss, VIN = 1200 mVpp. | 20 | mVpp | ||
| VOC(SS) | Change in steady-state common mode output voltage between logic states | ±10 | mV | |||
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N) | ||||||
| tR | Rise time (1) | Input signal with 30 ps rise time, 20% to 80%, See Figure 7-3 | 31 | ps | ||
| tF | Fall time (1) | Input signal with 30 ps fall time, 20% to 80%, See Figure 7-3 | 32 | ps | ||
| SDD22 | Differential output return loss | 6 GHz (12 Gbps) | -14 | dB | ||
| 4.05 GHz (HBR3, 8.1 Gbps) | –9.33 | dB | ||||
| 4.05 GHz (HBR3, 8.1 Gbps) | –6.35 | dB | ||||
| 1.35 GHz (HBR, 2.7Gbps) | –3.5 | dB | ||||
| tPLH | Low-to-high propagation delay | See Figure 7-2 | 65 | ps | ||
| tPHL | High-to-low propagation delay | 65 | ps | |||
| tSK(O) | Inter-Pair (lane to lane) output skew (2) | All outputs terminated with 100 Ω, See Figure 7-4 | 8 | ps | ||
| tSK(PP) | Part-to-part skew (3) | All outputs terminated with 100 Ω | 50 | ps | ||
| rOT | Single ended output resistance | Single ended on-chip termination to VCC, Outputs are AC coupled | 50 | Ω | ||
| rOM | Output termination mismatch at 1 MHz |  | 5% | |||
| Channel-to-channel isolation | Frequency at 6 GHz | 35 | 45 | dB | ||
| Output referred noise(4) | 10 MHz to 6 GHz, No other noise source present, VOD = LOW | 400 | µVRMS | |||
| 10 MHz to 6 GHz, No other noise source present, VOD = HIGH | 500 | µVRMS | ||||
| EQUALIZATION | ||||||
| G | At 6 GHz input signal | Equalization Gain, EQ = MAX | 15 | dB | ||
| V(pre) | Output pre-cursor pre-emphasis | Input signal with 3.75 pre-cursor and measure it on the output signal, See Figure 7-5 | 3.75 | dB | ||
| V(pst) | Output post-cursor pre-emphasis | Input signal with 12 dB post-cursor and measure it on the output signal, See Figure 7-5 | 12 | dB | ||
(1) Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 7-1 and Figure 7-3.
(2) tSK(O) is the magnitude of the time difference between the channels.
(3) tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same
(4) All noise sources added.
6.7 Switching Characteristics, I2C Interface
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| fSCL | SCL clock frequency | 400 | KHz | |||
| tBUF | Bus free time between START and STOP conditions | 1.3 | µs | |||
| tHDSTA | "Hold time after repeated START
condition. After this period, the first clock pulse is generated |
0.6 | µs | |||
| tLOW | Low period of the SCL clock | 1.3 | µs | |||
| tHIGH | High period of the SCL clock | 0.6 | µs | |||
| tSUSTA | Setup time for a repeated START condition | 0.6 | µs | |||
| tHDDAT | Data HOLD time | 0 | µs | |||
| tSUDAT | Data setup time | 100 | µs | |||
| tR | Rise time of both SDA and SCL signals | 300 | µs | |||
| tF | Fall time of both SDA and SCL signals | 300 | µs | |||
| tSUSTO | Setup time for STOP condition | 0.6 | µs | |||
6.8 Typical Characteristics
Figure 6-1 Differential Input Return Loss
Figure 6-3 Differential Output Return Loss
Figure 6-2 Differential to Common Mode Conversion
Figure 6-4 Common Mode Output Return Loss7 Parameter Measurement Information
Figure 7-1 Common
Mode Output Voltage Test Circuit
Figure 7-2 Propagation Delay Input to Output
Figure 7-3 Output
Rise and Fall Times
Figure 7-4 Output
Inter-Pair Skew
Figure 7-5 V(pre) and V(post) (test pattern is 1111111100000000
(8-1s, 8-0s))
Figure 7-6 Receive
Side Performance Test Circuit
Figure 7-7 Transmit
Side Performance Test Circuit
Figure 7-8 Equivalent Input Circuit
Figure 7-9 3-Level
Input Biasing Network
Figure 7-10 Two –
Wire Serial Interface Data Transfer
Figure 7-11 Two –
Wire Serial Interface Timing Diagram8 Detailed Description
8.1 Overview
The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps. The characteristics of this device make it transparent to DisplayPort (DP) link training. It supports all the available DP bit rates from RBR to UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps, and 10.0 Gbps respectively). Additionally, the SN65DP141 is configurable to a trace or cable mode, and hence improves its performance depending on the type of channel it is being used. Its transparency to the DP link training makes the SN65DP141 a position independent device, suitable for source/sink or cable applications, effectively providing a negative loss component to the overall link budget, in order to compensate the signal degradation over the channel.
The SN65DP141 is configurable by means of I2C and GPIOs, allowing independent channel control for activation, equalization, gain, and dynamic range.
8.2 Functional Block Diagram
