• 输出频率范围为 20 至 5500MHz
• 相位噪声性能行业领先
  • VCO 相位噪声：在输出为 1.8GHz 且偏移为 1MHz 时为 –144.5dBc/Hz
  • 归一化 PLL 本底噪声：-231dBc/Hz
  • 归一化 PLL 闪烁噪声：-126dBc/Hz
  • 47fs RMS 抖动（12kHz 至 20MHz）（对于 1.8GHz 输出）
• 输入时钟频率高达 1400MHz
• 相位检测器频率高达 200MHz，
  且在整数 N 模式中高达 400MHz
• 支持分数 N 和整数 N 模式
• 双差分输出
• 减少毛刺的创新型解决方案
• 可编程相位调整
• 可编程电荷泵电流
• 可编程输出功率水平
• 串行外设接口 (SPI) 或 uWire（4 线制串行接口）
• 单电源运行：3.3V

• 测试和测量设备
• 蜂窝基站
• 微波回程
• 高速数据转换器的高性能时钟源
• 由软件定义的无线电

LMX2582 是一款集成了 VCO 的低噪声宽带射频 PLL，支持的频率范围为 20MHz 至 5.5GHz。该器件支持分数 N 和整数 N 模式，具有一个 32 位分数分频器，支持选择合适的频率。其积分噪声为 47fs（对于 1.8GHz 输出），是理想的低噪声源。该器件融入了一流的 PLL 和 VCO 积分噪声与集成的低压线性稳压器 (LDO)，从而无需高性能系统中的多个分立器件。

该器件可接受高达 1.4GHz 的输入频率，与分频器及可编程低噪声乘法器相结合，可灵活设置频率。附加的可编程低噪声乘法器可帮助用户减轻整数边界杂散的影响。在分数 N 模式下，该器件可将输出相位调整 32 位分辨率。对于需要快速频率变化的应用，该器件支持耗时小于 25µs 的快速校准选项。

使用一个 3.3V 电源即可能实现此性能。该器件支持 2 个差分输出，这两个输出也可灵活配置为单端输出。用户可选择将其中一个编程为从 VCO 输出，另一个从通道分配器输出。若不想使用，可分别禁用每个输出。

Figure 6-1 Serial Data Input Timing Diagram

There are several considerations for programming:

• A slew rate of at least 30 V/µs is recommended for the CLK, DATA, LE
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the last CLK signal, the data is sent from the shift registers to a register bank
• The LE pin may be held high after programming and clock pulses are ignored
• When CLK and DATA lines are shared between devices, TI recommends diving down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity
• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming

T_A = 25°C (unless otherwise noted)

Figure 6-2 900-MHz Output - Closed-Loop Phase Noise

Figure 6-4 1.8-GHz Output - Closed-Loop Phase Noise

Figure 6-6 5.5-GHz Output - Closed-Loop Phase Noise

Figure 6-8 Integrated Jitter (47 fs) - 1.8-GHz Output

Figure 6-10 Variation of Phase Noise Across Temperature

Figure 6-12 High Output Power (50-Ω Pullup, Single-Ended) vs Output Frequency

Figure 6-14 Typical PFD Spur for 5.4-GHz Output

Figure 6-16 Impact of Channel Divider Settings on Phase Noise

Figure 6-3 900-MHz Output - Open-Loop Phase Noise

Figure 6-5 1.8-GHz Output - Open-Loop Phase Noise

Figure 6-7 5.5-GHz Output - Open-Loop Phase Noise

Figure 6-9 5.4-GHz Output Wide Loop Bandwidth – Showing PLL Performance

Figure 6-11 Impact of Supply Ripple on 1.8-GHz Output Phase Noise

Figure 6-13 Output Power at 5.4-GHz Output vs OUTx_POW Code (1 - 31, 48 - 63)

Figure 6-15 20-µs Frequency Change Time to 1.8 GHz With Fast Calibration

Figure 6-17 Noise Floor Variation With Output Frequency

The LMX2582 is a high performance wideband synthesizer (PLL with integrated VCO). The output frequency range is from 20 MHz to 5.5 GHz. The VCO core covers an octave from 3.55 to 7.1 GHz. The output channel divider covers the frequency range from 20 MHz to the low bound of the VCO core.

The input signal frequency has a wide range from 5 to 1400 MHz. Following the input, there is an programmable OSCin doubler, a pre-R divider (previous to multiplier), a multiplier, and then a post-R divider (after multiplier) for flexible frequency planning between the input (OSCin) and the phase detector.

The phase detector (PFD) can take frequencies from 5 to 200 MHz, but also has extended modes down to 0.25 MHz and up to 400 MHz. The phase-lock loop (PLL) contains a Sigma-Delta modulator (1st to 4th order) for fractional N-divider values. The fractional denominator is programmable to 32-bit long, allowing a very fine resolution of frequency step. There is a phase adjust feature that allows shifting of the output phase in relation to the input (OSCin) by a fraction of the size of the fractional denominator.

The output power is programmable and can be designed for high power at a specific frequency by the pullup component at the output pin.

The digital logic is a standard 4-wire SPI or uWire interface and is 1.8-V and 3.3-V compatible.

An input signal is required for the PLL to lock. The input signal is also used for the VCO calibration, so a proper signal needs to be applied before the start of programming. The input signal goes to the OSCinP and OSCinM pins of the device (there is internal biasing which requires AC-coupling caps in series before the pin). This is a differential buffer so the total swing is the OSCinM signal subtracted by the OSCinP signal. Both differential signals and single-ended signal can be used. Below is an example of the max signal level in each mode. It is important to have proper termination and matching on both sides (see Section 8).

Figure 7-1 Differential vs. Single-Ended Mode

The input signal path contains the components between the input (OSCin) buffer and the phase detector. The best PLL noise floor is achieved with a 200-MHz input signal for the highest dual-phase detector frequency. To address a wide range of applications, the input signal path contains the below components for flexible configuration before the phase detector. Each component can be bypassed. See Table 7-1 for usage boundaries if engaging a component.

• OSCin doubler: This is low noise frequency doubler which can be used to multiply input frequencies by two. The doubler uses both the rising and falling edge of the input signal so the input signal must have 50% duty cycle if enabling the doubler. The best PLL noise floor is achieved with 200-MHz PFD, thus the doubler is useful if, for example, a very low-noise, 100-MHz input signal is available instead.
• Pre-R divider: This is a frequency divider capable of very high frequency inputs. Use this to divide any input frequency up to 1400-MHz, and then the post-R divider if lower frequencies are needed.
• Multiplier: This is a programmable, low noise multiplier. In combination with the Pre-R and Post-R dividers, the multiplier offers the flexibility to set a PFD away from frequencies that may create critical integer boundary spurs with the VCO and output frequencies. See the Section 8 section for an example. The user should not use the doubler while using the low noise programmable multiplier.
• Post-R divider: Use this divider to divide down to frequencies below 5 MHz in extended PFD mode.

The PLL phase detector, also known as phase frequency detector (PFD), compares the outputs of the post-R divider and N divider and generates a correction current with the charge pump corresponding to the phase error until the two signals are aligned in phase (the PLL is locked). The charge pump output goes through external components (loop filter) which turns the correction current pulses into a DC voltage applied to the tuning voltage (Vtune) of the VCO. The charge pump gain level is programmable and allow to modify the loop bandwidth of the PLL.

The default architecture is a dual-loop PFD which can operate between 5 to 200 MHz. To use it in extended range mode the PFD has to be configured differently:

• Extended low phase detector frequency mode: For frequencies between 250 kHz and 5 MHz, low PFD mode can be activated (FCAL_LPFD_ADJ = 3). PLL_N_PRE also needs to be set to 4.
• Extended high phase detector frequency mode: For frequencies between 200 and 400 MHz, high PFD mode can be activated (FCAL_HPFD_ADJ = 3). The PFD also has to be set to single-loop PFD mode (PFD_CTL = 3). This mode only works if using integer-N, and PLL noise floor will be about 6-dB higher than in dual-loop PFD mode.

The N divider (12 bits) includes a multi-stage noise shaping (MASH) sigma-delta modulator with programmable order from 1st to 4th order, which performs fractional compensation and can achieve any fractional denominator from 1 to (2³² – 1). Using programmable registers, PLL_N is the integer portion and PLL_NUM / PLL_DEN is the fractional portion, thus the total N divider value is determined by PLL_N + PLL_NUM / PLL_DEN. This allows the output frequency to be a fractional multiplication of the phase detector frequency. The higher the denominator the finer the resolution step of the output. There is a N divider prescaler (PLL_N_PRE) between the VCO and the N divider which performs a division of 2 or 4. 2 is selected typically for higher performance in fractional mode and 4 may be desirable for lower power operation and when N is approaching max value.

Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)

Minimum output frequency step = Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]

Typically, higher modulator order pushes the noise out in frequency and may be filtered out with the PLL. However, several tradeoff needs to be made. Table 7-2 shows the suggested minimum N value while in fractional mode as a function of the sigma-delta modulator order. It also describe the recommended register setting for the PFD delay (register PFD_DLY_SEL).

The voltage controlled oscillator (VCO) is fully integrated. The frequency range of the VCO is from 3.55 to 7.1 GHz so it covers one octave. Channel dividers allow the generation of all other lower frequencies. The VCO-doubler allow the generation of all other higher frequencies. The output frequency of the VCO is inverse proportional to the DC voltage present at the tuning voltage point on pin Vtune. The tuning range is 0 V to 2.5 V. 0 V generates the maximum frequency and 2.5 V generates the minimum frequency. This VCO requires a calibration procedure for each frequency selected to lock on. Each VCO calibration will force the tuning voltage to mid value and calibrate the VCO circuit. Any frequency setting in fast calibration occurs in the range of Vtune pin 0 V to 2.5 V. The VCO is designed to remained locked over the entire temperature range the device can support. Table 7-3 shows the VCO gain as a function of frequency.