ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The output section is made up of six high-speed output MUX’s. The first two MUX’s are able to each select between the divided PLL1 and PLL2 clocks by programming R31.7 and R34.7. One MUX distributes to outputs 0, 1 and the other MUX distributes to outputs 2 and 3. The remaining four output MUX’s are able to each select between primary reference, secondary reference or the divided PLL1 or PLL2 clocks by programming R37[7-6], R39[7-6], R41[7-6], and R43[7-6]. Each of the four MUX’s distributes individually to outputs 4, 5, 6, and 7. When reference doubler is enabled and any output MUX selects that reference input, the output frequency will be the same as the reference frequency (non-doubled) but the output phase could be the same or complementary of the reference input.