ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The PLL1_NDIV_BY0 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7:0] | PLL1_NDIV[7:0] | RW | 0x66 | Y | PLL1 N Divider Byte 0. PLL1 Integer N Divider bits 7 to 0. |