AMC1304x 具有 LDO 的高精度、增强隔离式 Δ-Σ 调制器
1 特性
- 针对基于分流电阻的电流测量进行优化的引脚兼容系列：
- 出色的直流性能，支持系统级高精度感测：
- 安全相关认证：
- 7000 VPK 增强型隔离，符合 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 标准
- 符合 UL 1577 标准且长达 1 分钟的 5000 VRMS 隔离
- CAN/CSA No. 5A 组件接受服务通知、IEC 60950-1 和 IEC 60065 终端设备标准
- 瞬态抗扰度：15kV/µs（最小值）
- 高电磁场抗扰度
（请参见应用手册 SLLA181A） - 外部 5MHz 至 20MHz 时钟输入
可更加轻松地实现系统级同步 - 18V 片载低压降 (LDO) 稳压器
- 可在扩展工业温度范围内运行
2 应用
- 基于分流电阻的电流感测用于下列应用：
- 工业电机驱动
- 光电逆变器
- 不间断电源
- 隔离电压测量
3 说明
AMC1304 是一款高精度 Δ-Σ (ΔΣ) 调制器，通过磁场抗扰度较高的电容式双隔离栅隔离输出与输入电路。根据 DIN V VDE V 0884-10、UL1577 和 CSA 标准，该隔离栅经认证可提供高达 7000 VPEAK 的增强型隔离。当与隔离电源配合使用时，该器件可防止共模高电压线路上的噪声电流进入本地系统接地，从而干扰或损害低电压电路。
AMC1304 的输入针对直接连接分流电阻或其他低电压等级信号源进行了优化。凭借独特的 ±50mV 低输入电压范围，器件可通过分流显著降低功耗，同时具有出色的交流和直流性能。通过使用适当的数字滤波器（即集成于 TMS320F2807x 或 TMS320F2837x 系列）来抽取位流，该器件可在 78kSPS 数据速率下实现 81dB (13.2 ENOB) 动态范围的 16 位分辨率。
在高侧，调制器由集成的低压降 (LDO) 稳压器供电，该稳压器支持介于 4V 和 18V 之间的未经稳压的输入电压 (LDOIN)。隔离数字接口由 3.3V 或 5V 电源 (DVDD) 供电。
AMC1304 采用宽体小外形尺寸集成电路 (SOIC)-16 (DW) 封装，工作温度范围为 –40°C 至 +125°C。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| AMC1304x | SOIC (16) | 10.30mm x 7.50mm |
- 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
4 修订历史记录
Changes from D Revision (August 2016) to E Revision
- Changed V(ESD) for Human-body model (HBM) from ±2000 V to ±2500 VGo
- Changed 1G and 10G to 1M and 10M, respectively, in Quantization Noise Shaping figureGo
Changes from C Revision (September 2015) to D Revision
- 已更改“特性”部分：删除了经过认证的隔离隔栅分项，增加了安全相关认证和瞬态抗扰度分项Go
- 已更改简化原理图 Go
- Changed Specifications section to comply with ISO data sheet format Go
- Changed Maximum virtual junction parameter to Junction temperature in Absolute Maximum Ratings table Go
- Moved Power Rating, Insulation Specifications, Safety-Related Certifications, and Safety Limiting Values tables, changed to current standardsGo
- Changed Insulation Specifications table as per ISO standard Go
- Added Safety and Insulation Characteristics section Go
- Changed Figure 54 (The AMC1304 in a Frequency Inverter Application)Go
- Changed Figure 58 (Decoupling the AMC1304)Go
Changes from B Revision (July 2015) to C Revision
- 已将文档状态更改为完整量产数据：已将 AMC1304Mx5 发布为量产数据Go
- Changed status of AMC1304Mx5 rows to Production in Device Comparison Table Go
- Changed title of AMC1304x05 Electrical Characteristics table from AMC1304L05 to AMC1304x05 Go
- Changed typical specification in second row of DC Accuracy, PSRR parameter of AMC1304x05 Electrical Characteristics tableGo
- Added CMOS Logic Family (AMC1304M05) section to AMC1304x05 Electrical Characteristics tableGo
- Added last two rows to the Power Supply, IDVDD and PDVDD parameters of AMC1304x05 Electrical Characteristics tableGo
- Changed title of AMC1304x25 Electrical Characteristics table from AMC1304L25 to AMC1304x25Go
- Changed typical specification in second row of DC Accuracy, PSRR parameter of AMC1304x25 Electrical Characteristics table Go
- Added CMOS Logic Family (AMC1304M05) section to AMC1304x25 Electrical Characteristics table Go
- Added footnote 4 to AMC1304x25 Electrical Characteristics tableGo
- Added last two rows to the Power Supply, IDVDD and PDVDD parameters of AMC1304x25 Electrical Characteristics table Go
- Changed legends of Figure 6 and Figure 7 to include all devices, changed conditions of Figure 10 and Figure 11 Go
- Changed conditions of Figure 12, Figure 13, and Figure 14 Go
- Changed legends of Figure 19 to Figure 22, changed conditions of Figure 23 Go
- Changed conditions of Figure 24 and Figure 29 Go
- Changed conditions of Figure 30 and Figure 35 Go
- Changed conditions of Figure 36 to Figure 40 Go
- Added CMOS curve to Figure 44 to Figure 47 Go
- Changed legend of Figure 57 Go
Changes from A Revision (May 2015) to B Revision
- 已将 AMC1304L25 发布为量产数据Go
- 已更改第二个特性要点的偏移误差和增益误差 分项 ，以包括 AMC1304L25 规范Go
- Changed status of second row to Production Go
- Changed table order in Specifications section to match correct SDS flowGo
- Added AMC1304L25 Electrical Characteristics table Go
- Changed Typical Characteristics section: changed condition statement to reflect AINP difference between device, added AMC1304L25 related curvesGo
- Added AMC1304L25 plot to Figure 6 and Figure 7 Go
- Changed Figure 10 Go
- Added Figure 11 Go
- Added Figure 12 and condition to Figure 13 Go
- Changed Figure 14 Go
- Added AMC1304L25 plot to Figure 19, Figure 20, Figure 21, and Figure 22 Go
- Added Figure 23 Go
- Added Figure 29 and condition to Figure 24 Go
- Added condition to Figure 30 Go
- Added Figure 35 Go
- Added condition to Figure 36 Go
- Added device name to conditions of Figure 37 and Figure 38 Go
- Added Figure 39 and Figure 40 Go
Changes from * Revision (September 2014) to A Revision
- 已更改产品预览文档；已将 AMC1304L05 发布为量产数据Go
6 Pin Configurations and Functions
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| AMC1304Lx (LVDS) |
AMC1304Mx (CMOS) |
|||
| AGND | 4 | 4 | — | This pin is internally connected to pin 8 and can be left unconnected or tied to high-side ground |
| 8 | 8 | — | High-side ground reference | |
| AINN | 3 | 3 | I | Inverting analog input |
| AINP | 2 | 2 | I | Noninverting analog input |
| CLKIN | 13 | 13 | I | Modulator clock input, 5 MHz to 20.1 MHz |
| CLKIN_N | 12 | — | I | Inverted modulator clock input |
| DGND | 9, 16 | 9, 16 | — | Controller-side ground reference |
| DOUT | 11 | 11 | O | Modulator data output |
| DOUT_N | 10 | — | O | Inverted modulator data output |
| DVDD | 14 | 14 | — | Controller-side power supply, 3.0 V to 5.5 V. See the Power-Supply Recommendations section for decoupling recommendations. |
| LDOIN | 6 | 6 | — | Low dropout regulator input, 4 V to 18 V |
| NC | 1 | 1 | — | This pin can be connected to VCAP or left unconnected |
| 5 | 5 | — | This pin can be left unconnected or tied to AGND only | |
| — | 10, 12 | — | These pins have no internal connection | |
| 15 | 15 | — | This pin can be left unconnected or tied to DVDD only | |
| VCAP | 7 | 7 | — | LDO output. See the Power-Supply Recommendations section for decoupling recommendations. |
7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| LDOIN | LDO input supply voltage (LDOIN pin) | 4.0 | 15.0 | 18.0 | V |
| DVDD | Digital (controller-side) supply voltage (DVDD pin) | 3.0 | 3.3 | 5.5 | V |
| TA | Operating ambient temperature range | –40 | 125 | °C | |
7.4 Thermal Information
| THERMAL METRIC (1) | AMC1304x | UNIT | |
|---|---|---|---|
| DW (SOIC) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 80.2 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 40.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 45.1 | °C/W |
| ψJT | Junction-to-top characterization parameter | 11.9 | °C/W |
| ψJB | Junction-to-board characterization parameter | 44.5 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
7.5 Power Ratings
7.6 Insulation Specifications
| PARAMETER | TEST CONDITIONS | VALUE | UNIT | |
|---|---|---|---|---|
| GENERAL | ||||
| CLR | Minimum air gap (clearance)(1) | Shortest pin-to-pin distance through air | ≥ 8 | mm |
| CPG | Minimum external tracking (creepage)(1) | Shortest pin-to-pin distance across the package surface | ≥ 8 | mm |
| DTI | Distance through insulation | Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm) | 0.027 | mm |
| CTI | Comparative tracking index | DIN EN 60112 (VDE 0303-11); IEC 60112 | ≥ 600 | V |
| Material group | According to IEC 60664-1 | I | ||
| Overvoltage category per IEC 60664-1 | Rated mains voltage ≤ 300 VRMS | I-IV | ||
| Rated mains voltage ≤ 600 VRMS | I-III | |||
| Rated mains voltage ≤ 1000 VRMS | I-II | |||
| DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12(2) | ||||
| VIORM | Maximum repetitive peak isolation voltage | At ac voltage (bipolar or unipolar) | 1414 | VPK |
| VIOWM | Maximum-rated isolation working voltage | At ac voltage (sine wave) | 1000 | VRMS |
| At dc voltage | 1500 | VDC | ||
| VIOTM | Maximum transient isolation voltage | VTEST = VIOTM, t = 60 s (qualification test) | 7000 | VPK |
| VTEST = 1.2 x VIOTM, t = 1 s (100% production test) | 8400 | |||
| VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 60065, 1.2/50-μs waveform, VTEST = 1.6 x VIOSM = 10000 VPK (qualification) | 6250 | VPK |
| qpd | Apparent charge(4) | Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM = 1697 VPK, tm = 10 s | ≤ 5 | pC |
| Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM = 2263 VPK, tm = 10 s | ≤ 5 | pC | ||
| Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s | ≤ 5 | pC | ||
| CIO | Barrier capacitance, input to output(5) | VIO = 0.5 VPP at 1 MHz | 1.2 | pF |
| RIO | Insulation resistance, input to output(5) | VIO = 500 V at TS = 150°C | > 109 | Ω |
| Pollution degree | 2 | |||
| Climatic category | 40/125/21 | |||
| UL1577 | ||||
| VISO | Withstand isolation voltage | VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification test), VTEST = 1.2 x VISO = 6000 VRMS, t = 1 s (100% production test) | 5000 | VRMS |
7.7 Safety-Related Certifications
| VDE | UL | ||
|---|---|---|---|
| Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11 | Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs | ||
| Reinforced insulation | Single protection | ||
| File number: 40040142 | File number: E181974 |
7.8 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IS | Safety input, output, or supply current | θJA = 80.2°C/W, LDOIN = 18 V, TJ = 150°C, TA = 25°C, see Figure 3 |
86.5 | mA | ||
| PS | Safety input, output, or total power | θJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see Figure 4 | 1558(1) | mW | ||
| TS | Maximum safety temperature | 150 | °C | |||
The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
7.9 Electrical Characteristics: AMC1304x05
All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG INPUTS | ||||||
| VClipping | Maximum differential voltage input range (AINP-AINN) |
±62.5 | mV | |||
| FSR | Specified linear full-scale range (AINP-AINN) |
–50 | 50 | mV | ||
| VCM | Operating common-mode input range | –0.032 | 1.2 | V | ||
| CID | Differential input capacitance | 2 | pF | |||
| IIB | Input bias current | Inputs shorted to AGND | –97 | –72 | –57 | μA |
| RID | Differential input resistance | 5 | kΩ | |||
| IIO | Input offset current | ±5 | nA | |||
| CMTI | Common-mode transient immunity | 15 | kV/μs | |||
| CMRR | Common-mode rejection ratio | fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max |
–98 | dB | ||
| fIN from 0.1 Hz to 50 kHz, VCM min ≤ VIN ≤ VCM max |
–85 | |||||
| BW | Input bandwidth | 800 | kHz | |||
| DC ACCURACY | ||||||
| DNL | Differential nonlinearity | Resolution: 16 bits | –0.99 | 0.99 | LSB | |
| INL | Integral nonlinearity (1) | Resolution: 16 bits | –4 | ±1.5 | 4 | LSB |
| EO | Offset error | Initial, at 25°C | –50 | ±2.5 | 50 | µV |
| TCEO | Offset error thermal drift (2) | –1.3 | 1.3 | μV/°C | ||
| EG | Gain error | Initial, at 25°C | –0.3% | –0.02% | 0.3% | |
| TCEG | Gain error thermal drift (3) | –40 | ±20 | 40 | ppm/°C | |
| PSRR | Power-supply rejection ratio | LDOIN from 4 V to 18 V, at dc | –110 | dB | ||
| LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz | –110 | |||||
| AC ACCURACY | ||||||
| SNR | Signal-to-noise ratio | fIN = 1 kHz | 76 | 81.5 | dB | |
| SINAD | Signal-to-noise + distortion | fIN = 1 kHz | 76 | 81 | dB | |
| THD | Total harmonic distortion | fIN = 1 kHz | –90 | –81 | dB | |
| SFDR | Spurious-free dynamic range | fIN = 1 kHz | 81 | 90 | dB | |
| DIGITAL INPUTS/OUTPUTS | ||||||
| External Clock | ||||||
| fCLKIN | Input clock frequency | 5 | 20 | 20.1 | MHz | |
| DutyCLKIN | Duty cycle | 5 MHz ≤ fCLKIN ≤ 20.1 MHz | 40% | 50% | 60% | |
| CMOS Logic Family (AMC1304M05, CMOS with Schmitt Trigger) | ||||||
| IIN | Input current | DGND ≤ VIN ≤ DVDD | –1 | 1 | μA | |
| CIN | Input capacitance | 5 | pF | |||
| VIH | High-level input voltage | 0.7 × DVDD | DVDD + 0.3 | V | ||
| VIL | Low-level input voltage | –0.3 | 0.3 × DVDD | V | ||
| CLOAD | Output load capacitance | fCLKIN = 20 MHz | 30 | pF | ||
| VOH | High-level output voltage | IOH = –20 µA | DVDD – 0.1 | V | ||
| IOH = –4 mA | DVDD – 0.4 | |||||
| VOL | Low-level output voltage | IOL = 20 µA | 0.1 | V | ||
| IOL = 4 mA | 0.4 | |||||
| LVDS Logic Family (AMC1304L05)(4) | ||||||
| VT | Differential output voltage | RLOAD = 100 Ω | 250 | 350 | 450 | mV |
| VOC | Common-mode output voltage | 1.125 | 1.23 | 1.375 | V | |
| VID | Differential input voltage | 100 | 350 | 600 | mV | |
| VIC | Common-mode input voltage | VID = 100 mV | 0.05 | 1.25 | 3.25 | V |
| II | Receiver input current | DGND ≤ VIN ≤ 3.3 V | –24 | 0 | 20 | µA |
| POWER SUPPLY | ||||||
| LDOIN | LDOIN pin input voltage | 4.0 | 15.0 | 18.0 | V | |
| VCAP | VCAP pin voltage | 3.45 | V | |||
| ILDOIN | LDOIN pin input current | 5.3 | 6.5 | mA | ||
| DVDD | Controller-side supply voltage | 3.0 | 3.3 | 5.5 | V | |
| IDVDD | Controller-side supply current | LVDS, RLOAD = 100 Ω | 6.1 | 8 | mA | |
| CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, CLOAD = 5 pF |
2.7 | 4.0 | ||||
| CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 5 pF |
3.2 | 5.5 | ||||
7.10 Electrical Characteristics: AMC1304x25
All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG INPUTS | ||||||
| VClipping | Maximum differential voltage input range (AINP-AINN) |
±312.5 | mV | |||
| FSR | Specified linear full-scale range (AINP-AINN) |
–250 | 250 | mV | ||
| VCM | Operating common-mode input range | –0.16 | 1.2 | V | ||
| CID | Differential input capacitance | 1 | pF | |||
| IIB | Input bias current | Inputs shorted to AGND | –82 | –60 | –48 | μA |
| RID | Differential input resistance | 25 | kΩ | |||
| IIO | Input offset current | ±5 | nA | |||
| CMTI | Common-mode transient immunity | 15 | kV/μs | |||
| CMRR | Common-mode rejection ratio | fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max |
–98 | dB | ||
| fIN from 0.1 Hz to 50 kHz, VCM min ≤ VIN ≤ VCM max |
–98 | |||||
| BW | Input bandwidth | 1000 | kHz | |||
| DC ACCURACY | ||||||
| DNL | Differential nonlinearity | Resolution: 16 bits | –0.99 | 0.99 | LSB | |
| INL | Integral nonlinearity(1) | Resolution: 16 bits | –4 | ±1.5 | 4 | LSB |
| EO | Offset error | Initial, at 25°C | –100 | ±25 | 100 | µV |
| TCEO | Offset error thermal drift(2) | –1.3 | 1.3 | μV/°C | ||
| EG | Gain error | Initial, at 25°C | –0.2% | –0.05% | 0.2% | |
| TCEG | Gain error thermal drift(3) | –40 | ±20 | 40 | ppm/°C | |
| PSRR | Power-supply rejection ratio | LDOIN from 4 V to 18 V, at dc | –110 | dB | ||
| LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz |
–110 | |||||
| AC ACCURACY | ||||||
| SNR | Signal-to-noise ratio | fIN = 1 kHz | 82 | 85 | dB | |
| SINAD | Signal-to-noise + distortion | fIN = 1 kHz | 80 | 84 | dB | |
| THD | Total harmonic distortion | fIN = 1 kHz | –90 | –81 | dB | |
| SFDR | Spurious-free dynamic range | fIN = 1 kHz | 81 | 90 | dB | |
| DIGITAL INPUTS/OUTPUTS | ||||||
| External Clock | ||||||
| fCLKIN | Input clock frequency | 5 | 20 | 20.1 | MHz | |
| DutyCLKIN | Duty cycle | 5 MHz ≤ fCLKIN ≤ 20.1 MHz | 40% | 50% | 60% | |
| CMOS Logic Family (AMC1304M25, CMOS with Schmitt Trigger) | ||||||
| IIN | Input current | DGND ≤ VIN ≤ DVDD | –1 | 1 | μA | |
| CIN | Input capacitance | 5 | pF | |||
| VIH | High-level input voltage | 0.7 × DVDD | DVDD + 0.3 | V | ||
| VIL | Low-level input voltage | –0.3 | 0.3 × DVDD | V | ||
| CLOAD | Output load capacitance | fCLKIN = 20 MHz | 30 | pF | ||
| VOH | High-level output voltage | IOH = –20 µA | DVDD – 0.1 | V | ||
| IOH = –4 mA | DVDD – 0.4 | V | ||||
| VOL | Low-level output voltage | IOL = 20 µA | 0.1 | V | ||
| IOL = 4 mA | 0.4 | V | ||||
| LVDS Logic Family (AMC1304L25)(4) | ||||||
| VT | Differential output voltage | RLOAD = 100 Ω | 250 | 350 | 450 | mV |
| VOC | Common-mode output voltage | 1.125 | 1.23 | 1.375 | V | |
| VID | Differential input voltage | 100 | 350 | 600 | mV | |
| VIC | Common-mode input voltage | VID = 100 mV | 0.05 | 1.25 | 3.25 | V |
| II | Receiver input current | DGND ≤ VIN ≤ 3.3 V | –24 | 0 | 20 | µA |
| POWER SUPPLY | ||||||
| LDOIN | LDOIN pin input voltage | 4.0 | 15.0 | 18.0 | V | |
| VCAP | VCAP pin voltage | 3.45 | V | |||
| ILDOIN | LDOIN pin input current | 5.3 | 6.5 | mA | ||
| DVDD | Controller-side supply voltage | 3.0 | 3.3 | 5.5 | V | |
| IDVDD | Controller-side supply current | LVDS, RLOAD = 100 Ω | 6.1 | 8.0 | mA | |
| CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, CLOAD = 5 pF |
2.7 | 4.0 | ||||
| CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 5 pF |
3.2 | 5.5 | ||||
. .7.11 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tCLK | CLKIN, CLKIN_N clock period | 49.75 | 50 | 200 | ns | |
| tHIGH | CLKIN, CLKIN_N clock high time | 19.9 | 25 | 120 | ns | |
| tLOW | CLKIN, CLKIN_N clock low time | 19.9 | 25 | 120 | ns | |
| tD | Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay | 0 | 15 | ns | ||
| tISTART | Interface startup time | DVDD at 3.0 V (min) to DOUT, DOUT_N valid with LDO_IN > 4 V | 32 | 32 | CLKIN cycles | |
| tASTART | Analog startup time | LDOIN step to 4 V with DVDD ≥ 3.0 V, and 0.1 µF at VCAP pin | 1 | ms | ||
Figure 1. Digital Interface Timing
Figure 2. Digital Interface Startup Timing
7.12 Insulation Characteristics Curves
7.13 Typical Characteristics
At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted.
Ripple Frequency
Figure 24. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude
Input Signal Frequency
Input Signal Frequency
| AMC1304x05, 4096-point FFT, VIN = 100 mVPP |
| AMC1304x25, 4096-point FFT, VIN = 500 mVPP |
Input Signal Frequency
| AMC1304x05 |
LDO Input Supply Voltage
LDO Input Supply Voltage
Clock Frequency
LDO Input Supply Voltage
Controller-Side Supply Voltage (5 V, min)
Clock Frequency
8 Detailed Description
8.1 Overview
The differential analog input (AINP and AINN) of the AMC1304 is a fully-differential amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The isolated data output (DOUT and DOUT_N) of the converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to 20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1304. The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the ISO72x Digital Isolator Magnetic-Field Immunity application report (SLLA181A), available for download at www.ti.com. The external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The extended frequency range of up to 20 MHz supports higher performance levels compared to the other solutions available on the market.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Analog Input
The AMC1304 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for devices with a specified input voltage range of ±250 mV (this value is for the AMC1304x25), or to a factor of 20 in devices with a ±50-mV input voltage range (for the AMC1304x05), resulting in a differential input impedance of 5 kΩ (for the AMC1304x05) or 25 kΩ (for the AMC1304x25).
Consider the input impedance of the AMC1304 in designs with high-impedance signal sources that can cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is ±250 mV (for the AMC1304x25) or ±50 mV (for the AMC1304x05), and within the specified input common-mode range.
8.3.2 Modulator
The modulator implemented in the AMC1304 is a second-order, switched-capacitor, feed-forward ΔΣ modulator, such as the one conceptualized in Figure 48. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input.
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304 family. Also, SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a system-level solution for multichannel, isolated current sensing. An additional option is to use a suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-programmable gate array (FPGA) can be used to implement the digital filter.
8.3.3 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 250 mV (for the AMC1304x25) or 50 mV (for the AMC1304x05) produces a stream of ones and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1304x05) produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified linear ranges of the different AMC1304 versions with performance as specified in this data sheet. If the input voltage value exceeds these ranges, the output of the modulator shows non-linear behavior when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –312.5 mV (–62.5 mV for the AMC1304x05) or with a stream of only ones with an input greater than or equal to 312.5 mV (62.5 mV for the AMC1304x05). In this case, however, the AMC1304 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in Figure 50.
The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using Equation 1:
The AMC1304 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details, see the Switching Characteristics table.
Figure 50. Analog Input versus AMC1304 Modulator Output
8.4 Device Functional Modes
8.4.1 Fail-Safe Output
In the case of a missing high-side supply voltage (LDOIN), the output of a ΔΣ modulator is not defined and can cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. Therefore, the AMC1304 implements a fail-safe output function that ensures the device maintains its output level in case of a missing LDOIN, as shown in Figure 51.
Figure 51. Fail-Safe Output of the AMC1304
8.4.2 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1304 (that is, VIN ≥ VClipping), the device generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52. In this way, differentiating between a missing LDOIN and a full-scale input signal is possible on the system level.
Figure 52. Overrange Output of the AMC1304
