AMC1304x 具有 LDO 的高精度、增强隔离式 Δ-Σ 调制器

8.3.1 Analog Input

The AMC1304 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for devices with a specified input voltage range of ±250 mV (this value is for the AMC1304x25), or to a factor of 20 in devices with a ±50-mV input voltage range (for the AMC1304x05), resulting in a differential input impedance of 5 kΩ (for the AMC1304x05) or 25 kΩ (for the AMC1304x25).

Consider the input impedance of the AMC1304 in designs with high-impedance signal sources that can cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing these effects.

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is ±250 mV (for the AMC1304x25) or ±50 mV (for the AMC1304x05), and within the specified input common-mode range.

8.3.2 Modulator

The modulator implemented in the AMC1304 is a second-order, switched-capacitor, feed-forward ΔΣ modulator, such as the one conceptualized in Figure 48. The analog input voltage V_IN and the output V₅ of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V₁ at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V₃ that is differentiated with the input signal V_IN and the output of the first integrator V₂. Depending on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input.

Figure 48. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304 family. Also, SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a system-level solution for multichannel, isolated current sensing. An additional option is to use a suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-programmable gate array (FPGA) can be used to implement the digital filter.

Figure 49. Quantization Noise Shaping

8.3.3 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 250 mV (for the AMC1304x25) or 50 mV (for the AMC1304x05) produces a stream of ones and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1304x05) produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified linear ranges of the different AMC1304 versions with performance as specified in this data sheet. If the input voltage value exceeds these ranges, the output of the modulator shows non-linear behavior when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –312.5 mV (–62.5 mV for the AMC1304x05) or with a stream of only ones with an input greater than or equal to 312.5 mV (62.5 mV for the AMC1304x05). In this case, however, the AMC1304 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in Figure 50.

The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using Equation 1:

Equation 1.

The AMC1304 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details, see the Switching Characteristics table.

Figure 50. Analog Input versus AMC1304 Modulator Output

8.4.1 Fail-Safe Output

In the case of a missing high-side supply voltage (LDOIN), the output of a ΔΣ modulator is not defined and can cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. Therefore, the AMC1304 implements a fail-safe output function that ensures the device maintains its output level in case of a missing LDOIN, as shown in Figure 51.

Figure 51. Fail-Safe Output of the AMC1304

8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1304 (that is, V_IN ≥ V_Clipping), the device generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52. In this way, differentiating between a missing LDOIN and a full-scale input signal is possible on the system level.

Figure 52. Overrange Output of the AMC1304

9.1.1 Digital Filter Usage

The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort and hardware, is a sinc³-type filter, as shown in Equation 2:

Equation 2.

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All the characterization in this document is also done with a sinc³ filter with an oversampling ratio (OSR) of 256 and an output word duration of 16 bits.

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. Figure 53 shows the ENOB of the AMC1304 with different oversampling ratios. In this document, this number is calculated from the SNR by using Equation 3:

Equation 3.

Figure 53. Measured Effective Number of Bits versus Oversampling Ratio

An example code for implementing a sinc³ filter in an FPGA is discussed in the Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications application note (SBAA094), available for download at www.ti.com.

9.2.1 Frequency Inverter Application

Isolated ΔΣ modulators are being widely used in new-generation frequency inverter designs because of their high ac and dc performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string and central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and other industrial applications. The input structure of the AMC1304 is optimized for use with low-impedance shunt resistors and is therefore tailored for isolated current sensing using shunts.

Figure 54. The AMC1304 in a Frequency Inverter Application

9.2.1.3 Application Curve

In motor control applications, a very fast response time for overcurrent detection is required. The time for fully settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc³ filter requires three data updates for full settling (with f_DATA = f_CLK / OSR). Therefore, for overcurrent protection, filter types other than sinc³ can be a better choice; an alternative is the sinc² filter. Figure 55 compares the settling times of different filter orders.

The delay time of the sinc filter with a continuous signal is half of its settling time.

Figure 55. Measured Effective Number of Bits versus Settling Time

9.2.2 Isolated Voltage Sensing

The AMC1304 is optimized for usage in current-sensing applications using low-impedance shunts. However, the device can also be used in isolated voltage-sensing applications if the affect of the (usually higher) impedance of the resistor used in this case is considered.

Figure 56. Using the AMC1304 for Isolated Voltage Sensing

9.2.2.1 Design Requirements

Figure 56 shows a simplified circuit typically used in high-voltage-sensing applications. The high impedance resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of the sensing resistor R3 is chosen to meet the input voltage range of the AMC1304. This resistor and the differential input impedance of the device (the AMC1304x25 is 25 kΩ, the AMC1304x05 is 5 kΩ) also create a voltage divider that results in an additional gain error. With the assumption of R1, R2, and R_IN having a considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with E_G being the gain error of the AMC1304.

Equation 4.

This gain error can be easily minimized during the initial system-level gain calibration procedure.

9.2.2.2 Detailed Design Procedure

As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode voltage of 2 V. This voltage results in a bias current I_IB through the resistive network R4 and R5 (or R4' and R5') used for setting the gain of the amplifier. The value range of this current is specified in the Electrical Characteristics table. This bias current generates additional offset error that depends on the value of the resistor R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as illustrated in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems with high accuracy requirements, TI recommends using a series resistor at the negative input (AINN) of the AMC1304 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 56) to eliminate the affect of the bias current.

This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1304x05) or 12.5 kΩ (for the AMC1304x25).

Equation 5.

9.2.2.3 Application Curve

Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the AMC1304.

Figure 57. Input Current vs Input Common-Mode Voltage

9.2.3 Do's and Don'ts

Do not leave the inputs of the AMC1304 unconnected (floating) when the device is powered up. If both modulator inputs are left floating, the input bias current drives them to the output common-mode of the analog front end of approximately 2 V that is above the specified input common-mode range. As a result, the front gain diminishes and the modulator outputs a bitstream resembling a zero input differential voltage.