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  • ISO5851 具有有源保护特性的高 CMTI 2.5A 和 5A 隔离式 IGBT、MOSFET 栅极驱动器

    • ZHCSDT0C june   2015  – may 2023 ISO5851

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  • ISO5851 具有有源保护特性的高 CMTI 2.5A 和 5A 隔离式 IGBT、MOSFET 栅极驱动器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Characteristics
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5851 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  15. 14Mechanical, Packaging, and Orderable Information
  16. 重要声明
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Data Sheet

ISO5851 具有有源保护特性的高 CMTI 2.5A 和 5A 隔离式 IGBT、
MOSFET 栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 在 VCM = 1500V 时，共模瞬态抗扰度 (CMTI) 的最小值为 100kV/μs
  • 2.5A 峰值拉电流和 5A 峰值灌电流
  • 短传播延迟：76ns（典型值），
    110ns（最大值）
  • 2A 有源米勒钳位
  • 输出短路钳位
  • 在检测到去饱和故障时通过 FLT 发出故障报警并通过 RST 复位
  • 具有就绪 (RDY) 引脚指示的输入和输出欠压锁定 (UVLO)
  • 有源输出下拉特性，在低电源或输入悬空的情况下默认输出低电平
  • 3V 至 5.5V 输入电源电压
  • 15V 至 30V 输出驱动器电源电压
  • 互补金属氧化物半导体 (CMOS) 兼容输入
  • 抑制短于 20ns 的输入脉冲和瞬态噪声
  • 工作温度：–40°C 至 +125°C（环境温度）
  • 可承受的隔离浪涌电压 12800VPK
  • 安全相关认证：
    • 符合 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 标准的 8000 VPK VIOTM 和 2121 VPK VIORM 增强型隔离
    • 符合 UL 1577 标准且长达 1 分钟的 5700 VRMS 隔离
    • CSA 组件验收通知 5A，IEC 60950-1 和 IEC 60601-1 终端设备标准
    • 符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证
    • 经 GB4943.1-2011 CQC 认证

2 应用

  • 隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物半导体场效应晶体管 (MOSFET) 驱动器：
    • 工业电机控制驱动
    • 工业电源
    • 太阳能逆变器
    • HEV 和 EV 电源模块
    • 感应加热

3 说明

ISO5851 是一款用于 IGBT 和 MOSFET 的 5.7 kVRMS 增强型隔离栅极驱动器，具有 2.5A 的拉电流能力和 5A 的灌电流能力。输入端由 3V 至 5.5V 的单电源供电运行。输出侧支持的电源电压范围为 15V 至 30V。两路互补 CMOS 输入控制栅极驱动器输出状态。76ns 的短暂传播时间保证了对于输出级的精确控制。

内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何时处于过载状态。当检测到 DESAT 时，栅极驱动器输出会被拉低为 VEE2 电势，从而将 IGBT 立即关断。

当发生去饱和故障时，器件会通过隔离隔栅发送故障信号，以将输入端的 FLT 输出拉为低电平并阻断隔离器的输入。FLT 的输出状态将被锁存，可通过 RST 输入上的低电平有效脉冲复位。

器件信息(1)
器件型号 封装 封装尺寸（标称值）
ISO5851 SOIC (16) 10.30mm x 7.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
GUID-0189D3BA-A8EE-4552-835D-3ACD8B6E282F-low.gif功能方框图

4 Revision History

Changes from Revision B (January 2017) to Revision C (May 2023)

  • Added Additional manufacturing certification pending in the Safety-Related Certifications tableGo

Changes from Revision A (June 2015) to Revision B (January 2017)

  • 将标题从“有源安全特性”更改为“有源保护特性”Go
  • 将“特性”从“浪涌抗扰度为 12800VPK（根据 IEC 61000-4-5）”更改为“可承受的隔离浪涌电压 12800VPK”Go
  • 向安全和监管认证 添加了“特性”：符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证Go
  • Added the Power Ratings table Go
  • Moved Insulation Characteristics to the Specifications Go
  • Changed the Test Conditions and values for qpd in Insulation Characteristics Go
  • Changed RIO From: 100°C ≤ TA ≤ max To: 100°C ≤ TA ≤ 125°C in the Insulation Characteristics Go
  • Moved Safety-Related Certifications to the Specifications Go
  • Changed the CSA status from planned to certifiedGo
  • Moved Safety Limiting Values to the Specifications Go
  • Added the Reinforced High-Voltage Capacitor Life Time Projection figure to Insulation Characteristics Curves Go
  • Changed the Thermal Derating Curve for Limiting Current per VDE figure and Added the Thermal Derating Curve for Limiting Power per VDE figureGo
  • Added the ICC1 Supply Current vs Temperature figure to the Typical Characteristics Go
  • Changed the OUT Propagation Delay, Non-Inverting Configuration figure Go
  • Changed the OUT Propagation Delay, Inverting Configuration figureGo
  • Added text ", but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue." to Supply and Active Miller Clamp Go
  • Changed the second paragraph of the Section 10.2 Go
  • Added text "and RST input signal" to Section 10.2.1 Go
  • Deleted text " and a 220-pF filtering capacitor." from Recommended ISO5851 Application Circuit Go
  • Deleted text "thereby, providing protection against further catastrophic failures." From: the Global-Shutdown and Reset sectionGo
  • Changed the Normal Operation - Bipolar Supply and Normal Operation - Unipolar Supply figuresGo
  • Changed the PCB Material sectionGo

Changes from Revision * (June 2015) to Revision A (June 2015)

  • 将首页的“产品预发布”更改为完整数据表Go

5 说明（续）

如果在由双极输出电源供电的正常运行期间关断 IGBT，输出电压会被硬钳位为 VEE2。如果输出电源为单极，那么可采用有源米勒钳位，这种钳位会在一条低阻抗路径上灌入米勒电流，从而防止 IGBT 在高电压瞬态条件下发生动态导通。

当发生去饱和故障时，器件会通过隔离隔栅发送故障信号，以将输入端的 FLT 输出拉为低电平并阻断隔离器的输入。FLT 的输出状态将被锁存，可通过 RST 输入上的低电平有效脉冲复位。

如果在由双极输出电源供电的正常运行期间关断 IGBT，输出电压会被硬钳位为 VEE2。如果输出电源为单极，那么可采用有源米勒钳位，这种钳位会在一条低阻抗路径上灌入米勒电流，从而防止 IGBT 在高电压瞬态条件下发生动态导通。

栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制，这两个电路会监视输入端和输出端的电源。如果任意一端电源不足，RDY 输出会变为低电平；否则，该输出为高电平。

ISO5851 采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -40°C 至 +125°C。

6 Pin Configuration and Function

GUID-44320C01-B3B6-44DB-B62D-02D023F1193B-low.gifFigure 6-1 DW Package16-Pin SOICTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CLAMP 7 O Miller clamp output
DESAT 2 I Desaturation voltage input
FLT 13 O Fault output, low-active during DESAT condition
GND1 9, 16 — Input ground
GND2 3 — Gate drive common. Connect to IGBT emitter.
IN+ 10 I Non-inverting gate drive voltage control input
IN– 11 I Inverting gate drive voltage control input
NC 4 — Not connected
OUT 6 O Gate drive voltage output
RDY 12 O Power-good output, active high when both supplies are good.
RST 14 I Reset input, apply a low pulse to reset fault latch.
VCC1 15 — Positive input supply (3 V to 5.5 V)
VCC2 5 — Most positive output supply potential.
VEE2 1, 8 — Output negative supply. Connect to GND2 for Unipolar supply application.

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VCC1Supply voltage input sideGND1 – 0.36V
VCC2Positive supply voltage output sideVCC2 – GND2–0.335V
VEE2Negative supply voltage output sideVEE2 – GND2–17.50.3V
V(SUP2)Total supply output voltageVCC2 – VEE2–0.335V
VOUTGate driver output voltageVEE2 – 0.3VCC2 + 0.3V
I(OUTH)Gate driver high output currentGate driver high output current
max pulse width = 10 μs, max duty cycle = 0.2%		2.7A
I(OUTL)Gate driver low output currentGate driver high output current
max pulse width = 10 μs, max duty cycle = 0.2%		5.5A
V(LIP)Voltage at IN+, IN–, FLT, RDY, RSTGND1 – 0.3VCC1 + 0.3V
I(LOP)Output current of FLT, RDY10mA
V(DESAT)Voltage at DESAT GND2 – 0.3 VCC2 + 0.3V
V(CLAMP)Clamp voltageVEE2 – 0.3VCC2 + 0.3V
TJJunction temperature–40150°C
TSTGStorage temperature–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±4000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
VCC1Supply voltage input side35.5V
VCC2Positive supply voltage output side (VCC2 – GND2)1530V
VEE2Negative supply voltage output side (VEE2 – GND2)–150V
V(SUP2)Total supply voltage output side (VCC2 – VEE2)1530V
VIHHigh-level input voltage (IN+, IN–, RST)0.7 × VCC1VCC1V
VILLow-level input voltage (IN+, IN–, RST)00.3 × VCC1V
tUIPulse width at IN+, IN– for full output (CLOAD = 1 nF)40ns
tRSTPulse width at RST for resetting fault latch800ns
TAAmbient temperature–4025125°C

7.4 Thermal Information

THERMAL METRIC(1)ISO5851UNIT
DW (SOIC)
16 PINS
RθJAJunction-to-ambient thermal resistance99.6°C/W
RθJC(top)Junction-to-case (top) thermal resistance48.5°C/W
RθJBJunction-to-board thermal resistance56.5°C/W
ψJTJunction-to-top characterization parameter29.2°C/W
ψJBJunction-to-board characterization parameter56.5°C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

7.5 Power Ratings

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PDMaximum power dissipation(1)1255mW
PIDMaximum input power dissipation175mW
PODMaximum output power dissipation1080mW
(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that Junction temperature does not exceed 150°C.

7.6 Insulation Characteristics

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air8mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface8mm
DTIDistance through the insulationMinimum internal gap (internal clearance)21μm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A>600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum isolation working voltageAC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 7-11500VRMS
DC voltage2121VDC
VIOTMMaximum Transient isolation voltageVTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production)8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK (qualification)		8000
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK,
tm = 10 s		≤5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK,
tm = 10 s		≤5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 3977 VPK,
tm = 10 s		≤5
RIOIsolation resistance, input to output(5)VIO = 500 V at TS> 109Ω
VIO = 500 V, TA = 25°C>1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011Ω
CIOBarrier capacitance, input to output(5)VIO = 0.4 x sin (2πft), f = 1 MHz~1pF
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstanding Isolation voltageVTEST = VISO, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100% production)		5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.

7.7 Safety-Related Certifications

VDECSAULCQCTUV
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01		Certified according to CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1Certified according to UL 1577 Component Recognition ProgramCertified according to GB 4943.1-2011Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced Insulation Maximum Transient isolation voltage, 8000 VPK;
Maximum surge isolation voltage, 8000 VPK,
Maximum repetitive peak isolation voltage, 2121 VPK		Isolation Rating of 5700 VRMS;
Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 VRMS max working voltage (pollution degree 2, material group I) ;

2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage		Single Protection, 5700 VRMSReinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 VRMS maximum working voltage5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS

5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working voltage of 800 VRMS
Certification completed
Certificate number: 40040142		Certification completed
Master contract number: 220991		Certification completed
File number: E181974		Certification completed
Certificate number: CQC16001141761
Additional manufacturing certification pending		Certification completed
Client ID number: 77311

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ISSafety input, output or supply currentRθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C349mA
RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C228
RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C84
RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C42
PSSafety input, output, or total powerRθJA = 99.6°C/W, TJ = 150°C, TA = 25°C1255(1)mW
TSMaximum ambient safety temperature150°C
(1) Input, output, or the sum of input and output power should not exceed this value

The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Section 7.4 table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE SUPPLY
VIT+(UVLO1) Positive-going UVLO1 threshold voltage input side (VCC1 – GND1) 2.25 V
VIT-(UVLO1) Negative-going UVLO1 threshold voltage input side (VCC1 – GND1) 1.7 V
VHYS(UVLO1) UVLO1 Hysteresis voltage (VIT+ – VIT–) input side 0.24 V
VIT+(UVLO2) Positive-going UVLO2 threshold voltage output side (VCC2 – GND2) 12 13 V
VIT-(UVLO2) Negative-going UVLO2 threshold voltage output side (VCC2 – GND2) 9.5 11 V
VHYS(UVLO2) UVLO2 Hysteresis voltage (VIT+ – VIT–) output side 1 V
IQ1 Input supply quiescent current 2.8 4.5 mA
IQ2 Output supply quiescent current 3.6 6 mA
LOGIC I/O
VIT+(IN, RST) Positive-going input threshold voltage (IN+, IN–, RST) 0.7 × VCC1 V
VIT-(IN, RST) Negative-going input threshold voltage (IN+, IN–, RST) 0.3 × VCC1 V
VHYS(IN, RST) Input hysteresis voltage (IN+, IN–, RST) 0.15 × VCC1 V
IIH High-level input leakage at (IN+) IN+ = VCC1 100 µA
IIL Low-level input leakage at (IN–, RST) IN– = GND1, RST = GND1 –100 µA
IPU Pull-up current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 100 µA
VOL Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.2 V
GATE DRIVER STAGE
V(OUTPD) Active output pulldown voltage IOUT = 200 mA, VCC2 = open 2 V
V(OUTH) High-level output voltage IOUT = –20 mA VCC2 – 0.5 VCC2 – 0.24 V
V(OUTL) Low-level output voltage IOUT = 20 mA VEE2 + 13 VEE2 + 50 mV
I(OUTH) High-level output peak current IN+ = high, IN– = low,
VOUT = VCC2 - 15 V		 1.5 2.5 A
I(OUTL) Low-level output peak current IN+ = low, IN– = high,
VOUT = VEE2 + 15 V		 3.4 5 A
ACTIVE MILLER CLAMP
V(CLP) Low-level clamp voltage I(CLP) = 20 mA VEE2 + 0.015 VEE2 + 0.08 V
I(CLP) Low-level clamp current V(CLAMP) = VEE2 + 2.5 V 1.6 2.5 A
V(CLTH) Clamp threshold voltage 1.6 2.1 2.5 V
SHORT CIRCUIT CLAMPING
V(CLP_OUT) Clamping voltage
(VOUT - VCC2)		 IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA 0.8 1.3 V
V(CLP_CLAMP) Clamping voltage
(VCLP - VCC2)		 IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA 1.3 V
V(CLP_CLAMP) Clamping voltage at CLAMP IN+ = High, IN– = Low, I(CLP) = 20 mA 0.7 1.1 V
DESAT PROTECTION
I(CHG) Blanking capacitor charge current V(DESAT) - GND2 = 2 V 0.42 0.5 0.58 mA
I(DCHG) Blanking capacitor discharge current V(DESAT) - GND2 = 6 V 9 14 mA
V(DSTH) DESAT threshold voltage with respect to GND2 8.3 9 9.5 V
V(DSL) DESAT voltage with respect to GND2, when OUT is driven low 0.4 1 V

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trOutput signal rise timeCLOAD = 1 nF, see Figure 8-1, Figure 8-2, and Figure 8-3122035ns
tfOutput signal fall time122037ns
tPLH, tPHLPropagation Delay76110ns
tsk-pPulse Skew |tPHL – tPLH|20ns
tsk-ppPart-to-part skew30(1)ns
tGFGlitch filter on IN+, IN–, RST203040ns
tDESAT (10%)DESAT sense to 10% OUT delay300415500ns
tDESAT (GF)DESAT glitch filter delay330ns
tDESAT ( FLT)DESAT sense to FLT-low delaysee Figure 8-320002420ns
tLEBLeading edge blanking timesee Figure 8-1 and Figure 8-2330400500ns
tGF(RSTFLT)Glitch filter on RST for resetting FLT300800ns
CIInput capacitance(2)VI = VCC1 /2 + 0.4 x sin (2πft), f = 1 MHz, VCC1 = 5 V2pF
CMTICommon-mode transient immunityVCM = 1500 V, see Figure 8-4100120kV/μs
(1) Measured at same supply voltage and temperature condition
(2) Measured from input pin to ground.

 
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