• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TPS65982 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器

    • ZHCSDS8E March   2015  – August 2021 TPS65982

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • TPS65982 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics (1)
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Characteristics
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input/Output (I/O) Characteristics
    20. 7.20 I2C Slave Characteristics
    21. 7.21 SPI Controller Characteristics
    22. 7.22 BUSPOWERZ Configuration Characteristics
    23. 7.23 Thermal Shutdown Characteristics
    24. 7.24 Oscillator Characteristics
    25. 7.25 Single-Wire Debugger (SWD) Timing Requirements
    26. 7.26 HPD Timing Requirements
    27. 7.27 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink with RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C Port Data Multiplexer
        1. 9.3.4.1  USB Top and Bottom Ports
        2. 9.3.4.2  Multiplexer Connection Orientation
        3. 9.3.4.3  Digital Crossbar Multiplexer
        4. 9.3.4.4  SBU Crossbar Multiplexer
        5. 9.3.4.5  Signal Monitoring and Pullup/Pulldown
        6. 9.3.4.6  Port Multiplexer Clamp
        7. 9.3.4.7  USB2.0 Low-Speed Endpoint
        8. 9.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 9.3.4.9  BC1.2 Data Contact Detect
        10. 9.3.4.10 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 UART
      13. 9.3.13 I2C Slave
      14. 9.3.14 SPI Controller
      15. 9.3.15 Single-Wire Debugger Interface
      16. 9.3.16 DisplayPort HPD Timers
      17. 9.3.17 ADC
        1. 9.3.17.1 ADC Divider Ratios
        2. 9.3.17.2 ADC Operating Modes
        3. 9.3.17.3 Single Channel Readout
        4. 9.3.17.4 Round Robin Automatic Readout
        5. 9.3.17.5 One Time Automatic Readout
      18. 9.3.18 I/O Buffers
        1. 9.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.18.2 IOBUF_OD
        3. 9.3.18.3 IOBUF_UTX
        4. 9.3.18.4 IOBUF_URX
        5. 9.3.18.5 IOBUF_PORT
        6. 9.3.18.6 IOBUF_I2C
        7. 9.3.18.7 IOBUF_GPIOHSPI
        8. 9.3.18.8 IOBUF_GPIOHSSWD
      19. 9.3.19 Thermal Shutdown
      20. 9.3.20 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
      8. 9.4.8 UART Download
    5. 9.5 Programming
      1. 9.5.1 SPI Controller Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65982 External Flash
          2. 10.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Source Power Delivery Profiles for Type-C Ports
          2. 10.2.2.1.2 Sink Power Delivery Profile for Type-C Ports
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 TPS65982 and System Controller Interaction
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 9.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 10.2.2.2.4 Primary TPS65982 Flash Controller and Secondary Port
          5. 10.2.2.2.5 TPS65982 Dead Battery Support Primary and Secondary Port
          6. 10.2.2.2.6 Debugging Methods
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3-V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VOUT_3V3 Output Switch
      3. 11.1.3 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65982 Recommended Footprints
        1. 12.1.1.1 Standard TPS65982 Footprint (Circular Pads)
      2. 12.1.2  Alternate TPS65982 Footprint (Oval Pads)
      3. 12.1.3  Top TPS65982 Placement and Bottom Component Placement and Layout
      4. 12.1.4  Oval Pad Footprint Layout and Placement
      5. 12.1.5  Component Placement
      6. 12.1.6  Designs Rules and Guidance
      7. 12.1.7  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      8. 12.1.8  Routing Top and Bottom Passive Components
      9. 12.1.9  Void Via Placement
      10. 12.1.10 Top Layer Routing
      11. 12.1.11 Inner Signal Layer Routing
      12. 12.1.12 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information
  15. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPS65982 USB Type-C® 和 USB PD 控制器、电源开关和高速多路复用器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 该器件由 USB-IF 进行了 PD2.0 认证
    • 截至 2020 年 6 月，PD2.0 认证对于新设计不再适用
    • 所有需要认证的新设计应使用符合 PD3.0 的器件
    • 有关 PD2.0 与 PD3.0 的文章
  • 完全可配置的 USB PD 控制器
    • 通过 GPIO 控制外部直流/直流电源
      • 例如：TPS65982EVM
    • 端口数据多路复用器
      • USB 2.0 HS 数据和低速端点
      • 用于交替模式的边带使用数据
    • 用于为各种应用轻松配置 TPS65982 的 GUI 工具
    • 支持 DisplayPort 交替模式和 thunderbolt 交替模式
    • 有关更详尽的选择指南和入门信息，请参阅 www.ti.com/usb-c 和 E2E 指南
  • 完全管理的集成电源路径：
    • 集成的 5V、3A、50mΩ 电源开关
    • 集成 5V-20V、3A、95mΩ 双向负载开关
    • 适用于外部 5V-20V/5A 双向开关（背靠背 NFET）的栅极控制和电流检测
    • UL2367 认证编号：E169910-20150728
    • IEC62368-1 认证编号：111895
  • 集成强大的电源路径保护
    • 集成式反向电流保护、欠压保护、过压保护和压摆率可控制高压双向电源路径
    • 集成了欠压和过压保护以及限流功能，可为 5V/3A 拉电流电源路径提供浪涌电流保护
  • USB Type-C® 功率传输 (PD) 控制器
    • 8 个可配置 GPIO
    • 支持 BC1.2 充电
    • 符合 USB PD 2.0 标准
    • 符合 USB Type-C 规范
    • 线缆连接和方向检测
    • 集成式 VCONN 开关
    • 物理层和策略引擎
    • 3.3V LDO 输出，在电池电量耗尽时提供支持
    • 通过 3.3V 或 VBUS 源供电
    • 1 个 I2C 主要端口
    • 1 个 I2C 次级端口

2 应用

  • 耐用 PC 和笔记本电脑
  • 集线站
  • 平板监视器

3 说明

TPS65982 器件是一款独立式 USB Type-C 和供电 (PD) 控制器，可在 USB Type-C 连接器中提供电缆插头和方向检测。进行线缆检测时，TPS65982 器件会使用 USB PD 协议在 CC 线路上进行通信。在成功完成 USB PD 协商后，TPS65982 会启用合适的电源路径并为内部和（可选）外部多路复用器配置交替模式设置。

CC 引脚上的混合信号前端可为 USB Type-C 电源提供默认值、1.5A 或 3A 三种电流，检测电缆插入事件和确定 Type-C 电缆方向，以及利用双相标记编码 (BMC) 和物理层 (PHY) 协议自主协商 USB PD 合约。

器件信息(1)
器件型号封装封装尺寸（标称值）
TPS65982BGA MicroStar Junior (96)6.00mm × 6.00mm
NFBGA (96)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-F1921552-0ADD-4DE7-A06C-06AB7EAB5176-low.gif 简化版图表

4 Revision History

Changes from Revision D (June 2019) to Revision E (August 2021)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将提到 SPI 的旧术语实例全局更改为控制器和外设Go
  • 更新了 Section 1 列表Go
  • 更新了 Section 2 部分Go

Changes from Revision C (August 2016) to Revision D (June 2019)

  • 在器件信息 表中添加了 NFBGA 封装Go
  • Added NFBGA package to the Section 6 sectionGo
  • Added NFBGA package to the Section 7.4 tableGo

Changes from Revision B (May 2016) to Revision C (August 2016)

  • Added the HRESET I/O voltage parameter to the Absolute Maximum Ratings tableGo
  • Changed the value for the HBM from ±2000 to ±1500 in the ESD Ratings tableGo
  • Changed the maximum values for the ILDO_3V3 (50 to 70 mA) and ILDO_3V3EX (10 to 30 mA) current parameters in the Power Supply Requirements and Characteristics Go
  • Updated the GPIO_RPU parameter to show values for DEBUG_CTL1/2 separately in the Input/Output (I/O) Characteristics tableGo
  • Added parameters for HRESET in the Input/Output (I/O) Characteristics tableGo

Changes from Revision A (June 2015) to Revision B (May 2016)

  • 完成了编辑更改以修复印刷错误并提高术语的一致性Go

Changes from Revision * (March 2015) to Revision A (June 2015)

  • 量产数据表的初始发行版Go

5 说明（续）

端口电源开关在 5V 电压下可为传统 USB 电源和 Type-C USB 电源提供高达 3A 的下行电流。当 USB PD 电源用作供电器件（主机）、受电器件（设备）或供电-受电器件时，附加的双向开关路径可在最高 20V 的电压下为其提供高达 3A 的电流。

此外，TPS65982 还可用作上行数据端口 (UFP)、下行数据端口 (DFP) 或者双角色数据端口。端口数据多路复用器可实现端口与顶部或底部 D+/D- 信号对之间的 USB 2.0 HS 数据传输；此外，还可以将边带使用 (SBU) 信号对用于交替模式。当 3.3V 电源不可用时，电源管理电路可将 VBUS 用作主电源，在电池电量耗尽或无电池的情况下运行。

6 Pin Configuration and Functions

GUID-E55D8C26-8807-4A0A-B855-4F3809C15292-low.gifFigure 6-1 ZQZ and ZBH Package 96-Pin BGA MicroStar Junior and NFBGATop View
GUID-609514AA-8AAF-449C-B7EF-1460A8583B15-low.gifLegend for Pinout Drawing
Table 6-1 Pin Functions
PINTYPECATEGORYPOR STATEDESCRIPTION
NO.NAME
A1GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
A10SENSENAnalog inputExternal HV-FET control and sense pins and soft startAnalog inputPositive sense for external high-voltage power-path current-sense resistance. Short pin to VBUS when unused.
A11PP_5V0PowerHigh-current power pins—5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
A2LDO_1V8DPowerLow-current power pins—Output of the 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
A3SPI_CLKDigital outputDigital core I/O and control pinsDigital inputSPI serial clock. Ground pin when unused
A4SPI_POCIDigital inputDigital core I/O and control pinsDigital inputSPI serial controller input from peripheral. This pin is used during boot sequence to determine if the flash memory is valid. Refer to the Boot Code section for more details. Ground pin when unused.
A5I2C_SDA2Digital I/ODigital core I/O and control pinsDigital inputI2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
A6PP_HVPowerHigh-current power pins—HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused.
A7
A8
A9HV_GATE2Analog outputExternal HV-FET control and sense pins and soft startShort to VBUSExternal NFET gate control for high-voltage power path. Float pin when unused.
B1VDDIOPower Low-current power pins—VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
B10SENSEPAnalog inputExternal HV-FET control and sense pins and soft startAnalog inputPositive sense for external high-voltage power-path current-sense resistance. Short pin to VBUS when unused.
B11PP_5V0PowerHigh-current power pins—5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
B2GPIO0Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
B3SPI_CSZDigital outputDigital core I/O and control pinsDigital inputSPI chipselect. Ground pin when unused.
B4SPI_PICODigital outputDigital core I/O and control pinsDigital inputSPI serial controller output to peripheral. Ground pin when unused.
B5I2C_SCL2Digital I/ODigital core I/O and control pinsDigital inputI2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
B6I2C_IRQ2ZDigital outputDigital core I/O and control pinsHi-ZI2C port 2 interrupt. Active-low. Implement externally as an open-drain with a pullup resistance. Float pin when unused.
B7PP_HVPowerHigh-current power pins—HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused.
B8GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
B9HV_GATE1Analog outputExternal HV-FET control and sense pins and soft startShort to SENSEPExternal NFET gate control for high-voltage power path. Float pin when unused.
C1I2C_IRQ1ZDigital outputDigital core I/O and control pinsHi-ZI2C port 1 interrupt. Active-low. Implement externally as an open-drain with a pullup resistance. Float pin when unused.
C10GPIO4
(HPD TXRX)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 4. Configured as hot-plug detect (HPD) TX, HPD RX, or both when DisplayPort mode is supported. Ground pin with a 1-MΩ resistor when unused in the application.
C11PP_5V0PowerHigh-current power pins—5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
C2GPIO1Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 1. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
C3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
C4
C5
C6
C7
C8
C9
D1I2C_SDA1Digital I/ODigital core I/O and control pinsDigital inputI2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
D10GPIO2Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
D11PP_5V0PowerHigh-current power pins—5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
D2I2C_SCL1Digital I/ODigital core I/O and control pinsDigital inputI2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
D3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
D4
D5DEBUG_CTL2
(GPIO17, I2C ADDR B5)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address.
D6HRESETDigital I/ODigital core I/O and control pinsHi-ZActive high hardware reset input. Will re-load settings from external flash memory. Ground pin when HRESET functionality is not used.
D7GPIO7Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
D8GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
D9No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
E1LDO_BMCPowerLow-current power pins—Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND.
E10GPIO5
(HPD RX)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 5. Can be configured as Hot Plug Detect (HPD) RX when DisplayPort mode supported. Must be tied high or low through a 1-kΩ pullup or pulldown resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application.
E11MRESET
(GPIO11)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1MΩ resistor when unused in the application.
E2UART_TXDigital outputPort multiplexer pinsUART_RXUART serial transmit data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982.
E3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
E4DEBUG_CTL1
(GPIO16, I2C ADDR B4)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address.
E5GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
E6
E7
E8
E9No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
F1I2C_ADDRAnalog I/ODigital core I/O and control pinsAnalog inputSets the I2C address for both I2C ports as well as determine the master and slave devices for memory code sharing.
F10BUSPOWERZ
(GPIO10)		Analog InputDigital core I/O and control pinsInput (Hi-Z)General purpose digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details.
F11RESETZ
(GPIO9)		Digital I/ODigital core I/O and control pinsPush-pull output (Low)General purpose digital I/O 9. Active-low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused.
F2UART_RXDigital inputPort multiplexer pinsDigital inputUART serial receive data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982 and ground pin through a 100-kΩ resistance.
F3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
F4SWD_DATADigital I/OPort multiplexer pinsResistive pull highSWD serial data. Float pin when unused.
F5GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
F6
F7
F8
F9No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
G1LDO_3V3PowerLow-current power pins—Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND.
G10GPIO6Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
G11GPIO3Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
G2R_OSCAnalog I/ODigital core I/O and control pinsHi-ZExternal resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
G3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
G4SWD_CLKDigital inputPort multiplexer pinsResistive pull highSWD serial clock. Float pin when unused.
G5GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
G6
G7
G8
G9No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
H1VIN_3V3PowerLow-current power pins—Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
H10PP_CABLEPowerHigh-current power pins—5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
H11VBUSPowerHigh-current power pins—5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
H2VOUT_3V3PowerLow-current power pins—Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused.
H3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
H4GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
H5
H6GPIO8Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
H7SSAnalog outputExternal HV-FET control and sense pins and soft startDriven lowSoft Start. Tie pin to capacitance CSS to ground.
H8GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
H9No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
J1AUX_PAnalog I/OPort multiplexer pinsHi-ZSystem-side DisplayPort connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
J10VBUSPowerHigh-current power pins—5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
J11
J2AUX_NAnalog I/OPort multiplexer pinsHi-ZSystem-side DisplayPort connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
J3No BallBlankGround and no connect pins—Unpopulated ball for A1 marker and unpopulated inner ring.
J4
J5
J6
J7
J8
J9
K1LDO_1V8APowerLow-current power pins—Output of the 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
K10RPD_G2Analog I/OType-C port pinsHi-ZTie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
K11VBUSPowerHigh-current power pins—5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
K2DEBUG2
(GPIO14)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 14. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
K3DEBUG4
(GPIO12)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 12. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
K4LSX_P2RDigital outputPort multiplexer pinsHi-ZSystem side low speed RX to system from port. This pin is configurable to be an output from the digital core or the crossbar multiplexer from the port. Float pin when unused.
K5USB_RP_NAnalog I/OPort multiplexer pinsHi-ZSystem side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
K6C_USB_TPAnalog I/OType-C port pinsHi-ZPort-side top USB D+ connection to port multiplexer.
K7C_USB_BPAnalog I/OType-C port pinsHi-ZPort-side bottom USB D+ connection to port multiplexer.
K8C_SBU1Analog I/OType-C port pinsHi-ZPort-side Sideband Use connection of port multiplexer.
K9RPD_G1Analog I/OType-C port pinsHi-ZTie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
L1GNDGroundGround and no connect pins—Ground. Connect all balls to ground plane.
L10C_CC2Analog I/OType-C port pinsHi-ZOutput to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.
L11NCBlankGround and no connect pins—Populated ball that must remain unconnected.
L2DEBUG1
(GPIO15)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 15. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
L3DEBUG3
(GPIO13)		Digital I/ODigital core I/O and control pinsHi-ZGeneral purpose digital I/O 13. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
L4LSX_R2PDigital inputPort multiplexer pinsDigital inputSystem side low speed TX from system to port. This pin is configurable to be an input to the digital core or the crossbar multiplexer to the port. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
L5USB_RP_PAnalog I/OPort multiplexer pinsHi-ZSystem side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
L6C_USB_TNAnalog I/OType-C port pinsHi-ZPort-side top USB D– connection to port multiplexer.
L7C_USB_BNAnalog I/OType-C port pinsHi-ZPort-side bottom USB D– connection to port multiplexer.
L8C_SBU2Analog I/OType-C port pinsHi-ZPort-side Sideband Use connection of port multiplexer.
L9C_CC1Analog I/OType-C port pinsHi-ZOutput to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VIInput voltage(2)PP_CABLE, PP_5V0–0.36V
VIN_3V3–0.33.6
SENSEP(3), SENSEN(3)–0.324
VDDIO, UART_RX–0.3LDO_3V3 + 0.3
VIOOutput voltage (2)LDO_1V8A, LDO_1V8D, LDO_BMC, SS–0.32V
LDO_3V3–0.33.45
VOUT_3V3, RESETZ, I2C _IRQ1Z, I2C_IRQ2Z, SPI_PICO, SPI_CLK, SPI_CSZ, LSX_P2R, SWD_CLK, UART_TX–0.3LDO_3V3 + 0.3
HV_GATE1, HV_GATE2–0.330
HV_GATE1 (relative to SENSEP),–0.36
HV_GATE2 (relative to VBUS)
VIOI/O voltage (2)PP_HV, VBUS(3)–0.324V
I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_POCI, I2C_SDA2, I2C_SCL2, LSX_R2P, USB_RP_P, USB_RP_N, AUX_N, AUX_P, DEBUG1, DEBUG2, DEBUG3, DEBUG4, DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ, GPIO0-8–0.3LDO_3V3 + 0.3
R_OSC, I2C_ADDR–0.32
HRESET–0.3LDO_1V8D + 0.3
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (switches open)–26
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (switches closed)–0.36
C_CC1, C_CC2, RPD_G1, RPD_G2–0.36
TJOperating junction temperature–10125°C
TstgStorage temperature–55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(3) The 24-V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (< 100 ns) may occur up to 30 V.

7.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±1500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VIInput voltage range(1)VIN_3V32.853.45V
PP_5V04.755.5
PP_CABLE2.955.5
PP_HV4.522
VDDIO1.73.45
VIOI/O voltage range(1)VBUS422V
C_USB_PT, C_USB_NT, C_USB_PB, C_USB_NB, C_SBU1, C_SBU2–25.5
C_CC1, C_CC205.5
TAAmbient operating temperature range–1085°C
TBOperating board temperature range–10100°C
TJOperating junction temperature range–10125°C
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

7.4 Thermal Information

THERMAL METRIC(1)TPS65982UNIT
ZQZ (BGA)ZBH (NFBGA)
96 BALLS96 BALLS
RθJAJunction-to-ambient thermal resistance42.442.4°C/W
RθJC(top)Junction-to-case (top) thermal resistance12.412.4°C/W
RθJBJunction-to-board thermal resistance1313°C/W
ψJTJunction-to-top characterization parameter0.30.3°C/W
ψJBJunction-to-board characterization parameter1313°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Supply Requirements and Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL
VIN_3V3Input 3.3-V supply2.853.33.45V
PP_CABLEInput voltage to power C_CC pins. This input is also available to power core circuitry and the VOUT_3V3 output2.9555.5V
VBUSBi-direction DC bus voltage. Output from the TPS65982 or input to the TPS659824522V
PP_5V05V supply input to power VBUS. This supply does not power the TPS659824.7555.5V
VDDIO(1)Optional supply for I/O cells1.73.45V
INTERNAL
VLDO_3V3DC 3.3V generated internally by either a switch from VIN_3V3, an LDO from PP_CABLE, or an LDO from VBUS2.73.33.45V
VDO_LDO3V3Drop Out Voltage of LDO_3V3 from PP_CABLEILOAD = 50 mA250mV
Drop Out Voltage of LDO_3V3 from VBUS250500750mV
VLDO_1V8DDC 1.8V generated for internal digital circuitry1.71.81.9V
VLDO_1V8ADC 1.8V generated for internal analog circuitry1.71.81.9V
VLDO_BMCDC voltage generated on LDO_BMC. Setting for USB-PD1.051.1251.2V
ILDO_3V3DC current supplied by the 3.3V LDOs. This includes internal core power and external load on LDO_3V370mA
ILDO_3V3EXExternal DC current supplied by LDO_3V330mA
IOUT_3V3External DC current supplied by VOUT_3V3100mA
ILDO_1V8DDC current supplied by LDO_1V8D. This is intended for internal loads only but small external loads may be added50mA
ILDO_1V8DEXExternal DC current supplied by LDO_1V8D5mA
ILDO_1V8ADC current supplied by LDO_1V8A. This is intended for internal loads only but small external loads may be added20mA
ILDO_1V8AEXExternal DC current supplied by LDO_1V8A5mA
ILDO_BMCDC current supplied by LDO_BMC. This is intended for internal loads only5mA
ILDO_BMCEXExternal DC current supplied by LDO_BMC0mA
VFWD_DROPForward voltage drop across VIN_3V3 to LDO_3V3 switchILOAD = 50 mA256090mV
RIN_3V3Input switch resistance from VIN_3V3 to LDO_3V3VVIN_3V3 – VLDO_3V3 > 50 mV0.51.11.75Ω
ROUT_3V3Output switch resistance from VIN_3V3 to VOUT_3V30.350.7Ω
TR_OUT3V310-90% rise time on VOUT_3V3 from switch enableCVOUT_3V3 = 1 μF35120µs
(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.

7.6 Power Supervisor Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
UV_LDO3V3Undervoltage threshold for LDO_3V3. Locks out 1.8-V LDOsLDO_3V3 rising2.22.3252.45V
UVH_LDO3V3Undervoltage hysteresis for LDO_3V3LDO_3V3 falling2080150mV
UV_VBUS_LDOUndervoltage threshold for VBUS to enable LDOVBUS rising3.353.753.95V
UVH_VBUS_LDOUndervoltage hysteresis for VBUS to enable LDOVBUS falling2080150mV
UV_PCBLUndervoltage threshold for PP_CABLEPP_CABLE rising2.52.6252.75V
UVH_PCBLUndervoltage hysteresis for PP_PCABLEPP_CABLE falling205080mV
UV_5V0Undervoltage threshold for PP_5V0PP_5V0 rising3.53.7253.95V
UVH_5V0Undervoltage hysteresis for PP_P5V0PP_5V0 falling2080150mV
OV_VBUSOvervoltage threshold for VBUS. This value is a 6-bit programmable thresholdVBUS rising524V
OVLSB_VBUSOvervoltage threshold step for VBUS. This value is the LSB of the programmable thresholdVBUS rising328mV
OVH_VBUSOvervoltage hysteresis for VBUSVBUS falling, % of OV_VBUS0.9%1.3%1.7%
UV_VBUSUndervoltage threshold for VBUS. This value is a 6-bit programmable thresholdVBUS falling2.518.21V
UVLSB_VBUSUndervoltage threshold step for VBUS. This value is the LSB of the programmable thresholdVBUS falling249mV
UVH_VBUSUndervoltage hysteresis for VBUSVBUS rising, % of UV_VBUS0.9%1.3%1.7%
UVR_OUT3V3Configurable undervoltage threshold for VOUT_3V3 rising. Deasserts RESETZSetting 02.0192.1252.231V
Setting 12.1382.252.363
Setting 22.2562.3752.494
Setting 32.3752.52.625
Setting 42.4942.6252.756
Setting 52.6132.752.888
Setting 62.7312.8753.019
Setting 72.8533.15
UVRH_OUT3V3Undervoltage hysteresis for VOUT_3V3 fallingOUT_3V3 falling3050mV
TUVRASSERTDelay from falling VOUT_3V3 or MRESET assertion to RESETZ asserting low75μs
TUVRDELAYConfigurable delay from VOUT_3V3 to RESETZ deassertion0161.3ms

7.7 Power Consumption Characteristics(4)

Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IVIN_3V3Sleep(1)VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz oscillator running58µA
Idle (2)VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE = 0; 100-kHz oscillator running,
48-MHz oscillator running		1.66mA
Active(3)VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz Oscillator running,
48-MHz oscillator running		5.64mA
(1) Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.
(2) Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and a selectable clock to the digital core of 3 MHz or 4 MHz.
(3) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all core functionality active, and the digital core is clocked at 12 MHz.
(4) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).

7.8 Cable Detection Characteristics

Recommended operating conditions; TA = -10 to 85°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IH_CC_USBSource Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising Default USB current to a peripheral device73.68086.4μA
IH_CC_1P5Source Current through each C_CC pin when in a disconnected state when Configured as a DFP advertising 1.5 A to a UFP169180191μA
IH_CC_3P0Source Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising 3.0 A to a UFP.VIN_3V3 ≥ 3.135 V303330356μA
VD_CCH_USBVoltage Threshold for detecting a DFP attach when configured as a UFP and the DFP is advertising Default USB current source capability0.150.20.25V
VD_CCH_1P5Voltage Threshold for detecting a DFP advertising 1.5 A source capability when configured as a UFP0.610.660.7V
VD_CCH_3P0Voltage Threshold for detecting a DFP advertising 3 A source capability when configured as a UFP1.1691.231.29V
VH_CCD_USBVoltage Threshold for detecting a UFP attach when configured as a DFP and advertising Default USB current source capabilityIH_CC = IH_CC_USB1.4731.551.627V
VH_CCD_1P5Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 1.5 A source capabilityIH_CC = IH_CC_1P51.4731.551.627V
VH_CCD_3P0Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 3 A source capabilityIH_CC = IH_CC_3P0
VIN_3V3 ≥ 3.135 V		2.4232.552.67V
VH_CCA_USBVoltage Threshold for detecting an active cable attach when configured as a DFP and advertising Default USB current capability0.150.20.25V
VH_CCA_1P5Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 1.5 A capability0.350.40.45V
VH_CCA_3P0Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 3 A capability0.760.80.84V
RD_CCPulldown resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 poweredV = 1 V, 1.5 V4.855.15.35kΩ
RD_CC_OPENPulldown resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 poweredV = 0 V to LDO_3V3500kΩ
RD_DBPulldown resistance through each C_CC pin when in a disconnect state and configured as a UFP when configured for dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpoweredV = 1.5 V, 2.0 V
RPD_Gn tied to C_CCn		4.085.16.12kΩ
RD_DB_OPENPulldown resistance through each C_CC pin when in a disconnect state and configured as a UFP when not configured for dead battery (RPD_Gn tied to GND). LDO_3V3 unpoweredV = 1.5 V, 2.0 V
RPD_Gn tied to GND		500kΩ
VTH_DBThreshold Voltage of the pulldown FET in series with RD during dead batteryI_CC = 80 μA0.50.91.2V
R_RPDResistance between RPD_Gn and the gate of the pulldown FET255085MΩ

7.9 USB-PD Baseband Signal Requirements and Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
COMMON
PD_BITRATEPD data bit rate270300330Kbps
UI(1)Unit interval (1/PD_BITRATE)3.033.33 3.7μs
CCBLPLUG(2)Capacitance for a cable plug (each plug on a cable may have up to this value)25pF
ZCABLECable characteristic impedance3265Ω
CRECEIVER(3)Receiver capacitance. Capacitance looking into C_CCn pin when in receiver mode 70120pF
TRANSMITTER
ZDRIVERTX output impedance. Source output impedance at the Nyquist frequency of USB2.0 low speed (750kHz) while the source is driving the C_CCn line3375Ω
TRISERise Time. 10% to 90% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask300ns
TFALLFall Time. 90% to 10% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask300ns
RECEIVER
VRXTRRx Receive Rising Input threshold605630655mV
VRXTFRx Receive Falling Input threshold450 470490mV
NCOUNT(4)Number of transitions for signal detection (number to count to detect non-idle bus)3
TTRANWIN(4)Time window for detecting non-idle bus1220μs
ZBMCRXReceiver input impedanceDoes not include pullup or pulldown resistance from cable detect. Transmitter is Hi-Z.10MΩ
TRXFILTER(5)Rx bandwidth limiting filter. Time constant of a single pole filter to limit broadband noise ingression100ns
(1) UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the transition at the start of the cell.
(2) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends to add capacitance to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle.
(5) Broadband noise ingression is because of coupling in the cable interconnect.

7.10 USB-PD TX Driver Voltage Adjustment Parameter

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted(1)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
VTXP0TX transmit peak voltage1.6151.71.785V
VTXP1TX transmit peak voltage1.521.61.68V
VTXP2TX transmit peak voltage1.4251.51.575V
VTXP3TX transmit peak voltage1.331.41.47V
VTXP4TX transmit peak voltage1.2351.31.365V
VTXP5TX transmit peak voltage1.1881.251.312V
VTXP6TX transmit peak voltage1.141.21.26V
VTXP7TX transmit peak voltage1.1161.1751.233V
VTXP8TX transmit peak voltage1.0921.151.208V
VTXP9TX transmit peak voltage1.0681.1251.181V
VTXP10TX transmit peak voltage1.0451.11.155V
VTXP11TX transmit peak voltage1.0211.0751.128V
VTXP12TX transmit peak voltage0.9981.051.102V
VTXP13TX transmit peak voltage0.9741.0251.076V
VTXP14TX transmit peak voltage0.9511.05V
VTXP15TX transmit peak voltage0.9030.950.997V
(1) VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to the USB-PD Specifications.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale