• Menu
  • Product
  • Email
  • PDF
  • Order now

  • 具有集成时钟恢复器的 LMH1218 低功耗超高清电缆驱动器

    • ZHCSDJ6E February   2015  – June 2018 LMH1218

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • 具有集成时钟恢复器的 LMH1218 低功耗超高清电缆驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化 SPI 电路原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息
  13. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

具有集成时钟恢复器的 LMH1218 低功耗超高清电缆驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 支持 ST-2082（推荐）、ST-2081（推荐）、SMPTE 424M、344M、292M、259M、DVB-ASI、SFF-8431 (SFP+) 和适用于 SMPTE 2022-5/6 的 10GbE 以太网
  • 锁定为以下速率：11.88Gbps、5.94Gbps、2.97Gbps、1.485Gbps 或 1.001 分频子速率、DVB-ASI (270Mbps) 和 10GbE (10.3125Gbps)
  • 无基准，锁定迅速，涵盖所有支持的或选定的数据速率
  • 75Ω 和 100Ω 发送器输出
  • 集成了 2:1 复用输入，1:2 解复用/扇出输出
  • 基于输入速率检测的自动转换率
  • 片上眼图监视器
  • 功耗仅 300mW，输入信号丢失时自动断电
  • 可通过 SPI 或 SMBus 接口进行编程
  • 2.5V 单电源运行
  • 小型 4mm × 4mm 24 引脚 WQFN 封装
  • 运行温度范围：–40°C 至 +85°C

2 应用

  • UHDTV/4K/8K/HDTV/SDTV 视频
  • 数字视频路由器和交换机
  • 数字视频处理和编辑
  • DVB-ASI 和分布式放大器
  • 适用于 SMPTE 2022-5/6 的 10GbE 以太网

3 说明

LMH1218 是一款具有集成时钟恢复器的低功耗电缆驱动器，可驱动符合 SMPTE-SDI、SMPTE 2022-5/6、10GbE 以太网和 DVB-ASI 标准的串行视频数据。LMH1218 支持高达 11.88Gbps 的数据传输速率，可以在 4K/8K 应用中实现超高清视频 显示。LMH1218 具有 75Ω 和 50Ω 的发送器输出，支持同轴电缆、光纤及 FR-4 PCB 等多种介质选项。

LMH1218 的输入端集成了 2:1 多路复用器，支持在两个视频源之间进行选择，同时可编程均衡器可以补偿印刷电路板损耗，以此延长信号传输距离。该片上时钟恢复器借助宽范围时钟和数据恢复 (CDR) 电路，在无需外部参考时钟和环路滤波器组件的情况下，自动检测并锁定 270Mbps 至 11.88Gbps 的串行数据，从而简化了电路板设计并降低了系统成本。经时钟恢复的串行数据可路由到 75Ω 或 50Ω 发送器输出或同时路由到这两个输出（1 对 2 扇出模式）。输出电压摆幅兼容 SFF-8431 (SFP+)、ST-2082/1（推荐）、SMPTE 424M、344M、292M 以及 259M 标准。

非破坏性眼图监视器支持实时测量串行数据，从而简化系统启动或现场调试过程。LMH1218 可通过 SPI 或 SMBus 接口进行编程。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LMH1218 WQFN (24) 4.00mm × 4.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

简化 SPI 电路原理图

LMH1218 simplified_spi_schem_no_pin_snls474.gif

4 修订历史记录

Changes from D Revision (December 2017) to E Revision

  • Changed the note under Float(Default) setting from: Reserved to: Power down until valid signal detectedGo
  • Changed MISO pin I/O description from 3-Level back to 2-LevelGo
  • Changed the Acknowledge (ACK) graphic text from: Clock Line Held Low by Receiver While Interrupt is Serviced to: Host may held clock line low to delay transactionGo
  • Changed Channel Register 0x80 default from: 0xXX to: 0x20 Go
  • Changed the OUT0_VOD bit 7 default from x to 0Go
  • Changed the bit description for the OUT0_VOD bits 7-3 from: drv_0_sel_vod[3:0] default value may change from part to part to: drv_0_sel_vod[3:0] is typically 42 mV per step.Go
  • Changed the OUT0_VOD bit 6 default from x to 0Go
  • Changed the OUT0_VOD bit 5 default from x to 1Go
  • Changed the OUT0_VOD bit 4 default from x to 0Go

Changes from C Revision (December 2016) to D Revision

  • Changed Channel Register 0x80 default value from 0101 0100’b to XXXX 0000’bGo

Changes from B Revision (February 2016) to C Revision

  • Changed MISO pin I/O description from 2-Level to 3-LevelGo
  • Added test conditions to the source transmit differential launch amplitude parametersGo
  • Changed OUT0 VOD_Scaling_PD description for bits 7 through 4Go

Changes from A Revision (March 2015) to B Revision

  • Changed ESD Ratings for Human-body model (HBM) From: ±2500 To ±4500 Go
  • Added typical launch amplitude for 20 and 30 inch FR4 trace in the Recommended Operating ConditionsGo
  • Added new Note to the Electrical Characteristics: "ATE Production tested using DC method.."Go
  • Changed the VVOD_OUT0 row information and values in the Electrical CharacteristicsGo
  • Added MAX value of 45 ps to TR_F_OUT0 in the Electrical CharacteristicsGo
  • Changed the TYP value From: 900 To: 950 ps, Added MIN and MAX values to TR_F_OUT0 (270 Mbps) in the Electrical CharacteristicsGo
  • Changed the TYP value to 3 ps, Added MAX value of 18 ps to TR_F_OUT0_delta in the Electrical CharacteristicsGo
  • Changed the TYP value From: 100 To: 72 ps, Added MAX value of 500 ps to TR_F_OUT0_delta (270 Mbps) in the Electrical CharacteristicsGo
  • Changed the VOVR_UDR_SHOOT row information and values in the Electrical CharacteristicsGo
  • Added tSU MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tH MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tSSSu MIN = 14 ns, Changed TYP value From: 14 To: 18 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added tSSh MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing SpecificationsGo
  • Added Selective Data Rate Lock in Application and Implementation section. Go

Changes from * Revision (February 2015) to A Revision

  • Changed 文档状态产品预览至量产数据Go

5 Pin Configuration and Functions

RTW Package
24-Pin WQFN
(Top View)
LMH1218 pin_configuration_2_16.gif

Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD

PIN TYPE DESCRIPTION
NAME NO.
CONTROL/INDICATOR I/O
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default):
  • Power down until valid signal detected

20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock detect status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output,
LVCMOS Open-Drain, 2-Level		 Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MISO 15 Output, 2.5-V LVCMOS, 2-Level SPI Master Input / Slave Output. LMH1218 SPI data transmit
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
  • SPI mode. See Initialization Set Up.
MOSI 4 Input, 2-Level SPI Master Output / Slave Input. LMH1218 SPI data receive
RESERVED 5, 17, 18 — No Connect
SCK 3 Input, 2.5V LVCMOS, 2-Level SPI serial clock input
SMPTE_10GbE 14 — No Connect
SS_N 2 Input, 2-Level SPI Slave Select. This pin has internal pullup
HIGH-SPEED DIFFERENTIAL I/O
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100-Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
POWER
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground

Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND

PIN TYPE DESCRIPTION
NAME NO.
ADDR0 2 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note the SMBus section for further details. The four strap options include:
1 kΩ to VDD:
  • Represents logic state 11’b

Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
  • Represents logic state 01'b

1 kΩ to GND:
  • Represents logic state 00'b
ADDR1 15
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default): Reserved
20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock Status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output, LVCMOS
Open-Drain, 2-Level 		Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
RESERVED 5, 17, 18 — No Connect
SCL 3 Input, 2-Level SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SDA 4 I/O, Open-Drain, 2-Level SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SMPTE_10GbE 14 No Connect
HIGH-SPEED DIFFERENTIAL I/O
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (VDD to GND) –0.5 2.75 V
3.3-V open-drain I/O input and output voltage (SDA, SCL, LOS_INT_N) –0.5 4.0 V
2.5-V LVCMOS input and output voltage –0.5 VDD + 0.5 V
High-speed input voltage –0.5 VDD + 0.5 V
High-speed input current –30 30 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage(1) 2.375 2.5 2.625 V
3.3-V open-drain I/O input and output voltage 3 3.3 3.6 V
Supply noise, 50 Hz to 10 MHz, sinusoidal(1) 40 mVP-P
Ambient temperature –40 25 85 ºC
Source transmit differential launch amplitude (up to 20 inch FR4 trace) PRBS15, EQ, and PLL pathological pattern. Reg 0x03 = 0x50 300 500 1000 mVP-P
Source transmit differential launch amplitude (up to 35 inch FR4 trace) PRBS15, EQ, and PLL pathological pattern. Reg 0x03 = 0x95 600 700 800 mVP-P
SMBus clock frequency (SCL) in SMBus slave mode 100 400 kHz
SMBUS SDA and SCL voltage level 3.6 V
SPI clock frequency 10 20 MHz
(1) DC plus AC power should not exceed these limits.

6.4 Thermal Information

THERMAL METRIC(1)(2) UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 34 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.4 °C/W
RθJB Junction-to-board thermal resistance 11.8 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 11.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power dissipation Locked 75 Ω OUT0 only (800 mVpp), EOM powered down 300 mW
Locked OUT1 only (600 mVpp, diff), EOM powered down 195 mW
Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down 400 500 mW
PD_RAW Power dissipation in force RAW mode (CDR bypass) EQ bypass, OUT0 720mVpp, OUT1 600mVpp
IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1		 195 mW
IN0 to OUT0, OUT1 powered down 160 mW
IN1 to OUT1, OUT0 powered down 80 mW
4-LEVEL INPUT AND 2.5 V LVCMOS DC SPECIFICATIONS
VIH High level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.95 × VDD V
VIF Float level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.67 × VDD V
VI20K 20K to GND input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.33 × VDD V
VIL Low level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.1 V
VOH High level output voltage IOH = -3 mA 2 V
VOL Low level output voltage IOL = 3 mA 0.4 V
IIH Input high leakage current Vinput = VDD
SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins		 15 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins 15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins 20 44 80 µA
4-Levels (MODE_SEL, ENABLE) pins 20 44 80 µA
IIL Input low leakage current Vinput = GND
SPI Mode: LVCMOS (SPI_MOSI, SPI_SCK) pins		 –15 µA
Vinput = GND
SPI Mode: LVCMOS (SPI_SS_N) pins		 –37 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL pins –15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins –160 –93 –40 µA
4-Levels (MODE_SEL, ENABLE) pins –160 –93 –40 µA
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
VIH25 High level input voltage 2.5-V Supply Voltage 1.75 3.6 V
VIL Low level input voltage GND 0.8 V
VOL Low level output voltage IOL = 1.25 mA 0.4 V
IIH Input high current VIN = 2.5 V, VDD = 2.5 V 20 40 μA
IIL Input low current VIN = GND, VDD = 2.5 V -10 10 μA
SIGNALDETECT
SDH Signal detect (default)
Assert threshold level(2)(3) 		11.88 Gbps, SMPTE (EQ, PLL) Pathological Pattern 26 mVP-P
10.3125 Gbps, 1010 Clock Pattern, no media 30 mVP-P
10.3125 Gbps, PRBS31 Pattern 21 mVP-P
SDL Signal detect (default)
De-assert threshold level(2) 		11.88 Gbps, SMPTE (EQ, PLL) Pathological Patterns 20 mVP-P
10.3125 Gbps, 1010 Clock Pattern 15 mVP-P
10.3125 Gbps, PRBS31 Pattern 12 mVP-P
HIGH-SPEED RECEIVE RX INPUTS (IN_n+, IN_n–)
R_RD DC Input differential resistance 75 100 125 Ω
RLRX-SDD Input differential return loss(1) Measured with the device powered up.
SDD11 10 MHz to 2 GHz		 –14  dB
SDD11 2 GHz to 6 GHz –6.5  dB
SDD11 6 GHz to 12 GHz –6.5  dB
RLRX-SCD Differential to common mode Input conversion(1) Measure with the device powered up.SCD11, 10 MHz to 12 GHz  –20 dB
HIGH-SPEED OUTPUTS (OUT_n+, OUT_n–)
VVOD_OUT1 Output differential voltage(1)(5) Default setting, 8T clock pattern 400 600 700 mVP-P
VVOD_OUT1_DE De-emphasis Level VOD = 600 mV, maximum De-Emphasis with 16T clock pattern –9 dB
VVOD_OUT1_CLK Clock output differential voltage 2.97 GHz,1.485 GHz, 297 MHz, and 270 MHz 560 mVP-P
VVOD_OUT0 Output single ended voltage at OUT0+ with OUT0– terminated(1)(5)(9) Default setting 720 778 880 mVP-P
RDIFF_OUT1 DC output differential resistance 100 Ω
RDIFF_OUT0 DC output single-ended resistance 75 Ω
TR_F_OUT1 Output rise/fall time Full Slew Rate, 20% to 80% using 8T Pattern 45 ps
TR_F_OUT0 Output rise/fall time, PRBS10(1)(5) 11.88 Gbps 35 45 ps
5.94 Gbps 35 45 ps
2.97 Gbps 35 45 ps
1.485 Gbps 35 45 ps
270 Mbps 400 950 1500 ps
TR_F_OUT0_delta Output rise/fall time mismatch(1)(5) 11.88 Gbps 3 18 ps
5.94 Gbps 3 18 ps
2.97 Gbps 3 18 ps
1.485 Gbps 3 18 ps
270 Mbps 72 500 ps
VOVR_UDR_SHOOT Output overshoot, undershoot(1)(5) 12G/6G/3G/HD/SD
Measured with 8T pattern		 2.4% 3.4%
VDC_OFFSET DC offset(1) 12G/6G/3G/HD/SD ±0.2 V
VDC_WANDER DC wander(1) 12G/6G/3G/HD/SD EQ Pathological 20 mV
RLOUT0_S22 OUT0 single-ended 75-Ω return loss(1)(5)(7) S22 5 MHz to 1.485 GHz < –15 dB
S22 1.485 GHz to 3 GHz < –10 dB
S22 3 GHz to 6 GHz < –7 dB
S22 6 GHz to 12 GHz < –4 dB
RLOUT1_SDD22 OUT1 differential 100-Ω return loss(1)(5)(6) SDD22 10 MHz - 2 GHz –20  dB
SDD22 2 GHz - 6 GHz  –17 dB
SDD22 6 GHz - 11.1 GHz  –14 dB
RLOUT1_SCC22 OUT1 common-mode 50-Ω return loss(1)(5)(6) SCC22 10 MHz - 4.75 GHz –11 dB
SCC22 4.75 GHz - 11.1 GHz –12 dB
VVCM_OUT1_NOISE AC common-mode voltage noise(1)(5) VOD = 0.6 Vpp, DE = 0dB, PRBS31, 10.3125 Gbps 8 mVRMS
TRCK_LATENCY Latency reclocked Reclocked Data 1.5 UI +195 ps
TRAW_LATENCY Latency CDR bypass Raw Data 230 ps
TRANSMIT OUTPUT JITTER SPECIFICATIONS
AJ_OUT0 Alignment jitter(1)(5) OUT0, PRBS15, 11.88 Gbps 0.18 UI
TJ_OUT1 Total jitter (1E-12)(1)(5) OUT1, PRBS15 10.3125 Gbps 0.12 UI
RJ_OUT1 Random jitter (rms) OUT1, PRBS15, 10.3125 Gbps 0.38 psRMS
DJ_OUT1 Deterministic jitter OUT1, PRBS15, 10.3125 Gbps 7 psP-P
DJ_OUT1_RAW Deterministic jitter OUT1, RAW MODE (CDR bypass)
PRBS15, 11.88 Gbps, 35 inch FR4 trace, EQ=0x95, VID = 800mVpp		 25 psP-P
CLOCK DATA RECOVERY
DDATA_RATE ST-2082 (proposed)(8) 11.88, 11.868 Gbps
ST-2081 (proposed)(8) 5.94, 5.934 Gbps
SMPTE 424(8) 2.97, 2.967 Gbps
SMPTE 292(8) 1.485, 1.4835 Gbps
SMPTE 259M(8) 270 Mbps
10 GbE(8) 10.3125 Gbps
PPLL_BW PLL bandwidth at –3 dB Measured with 0.2UI SJ at 10.3125 Gbps 8 MHz
Measured with 0.2UI SJ at 11.88 Gbps 13 MHz
Measured with 0.2UI SJ at 5.94 Gbps 7 MHz
Measured with 0.2UI SJ at 2.97 Gbps 5 MHz
Measured with 0.2UI SJ at 1.485 Gbps 3 MHz
Measured with 0.2UI SJ at 270 Mbps 1 MHz
JTOL Total input jitter tolerance TJ = DJ + RJ + SJ,
DJ+RJ = 0.15 UI
SJ/PJ, low to high upward sweep (10 kHz to 80 MHz)		 0.65 UI
TLOCK Lock time(1)(4) From signal detected to the lock asserted, HEO/VEO lock monitor disable, same setting for 11.88G, 5.94G, 2.97G, 1.485G and 270-MHz data rates <5 ms
TTEMP_LOCK CDR lock with temperature ramp Temperature Lock Range, 5ºC per minute ramp up and down, –40ºC to 85ºC operating range 125 °C
(1) These limits are ensured by bench characterization and are not production tested.
(2) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
(3) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal detect assert condition
(4) The total CDR lock time depends on number of rate settings enabled and application data rate
(5) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
(6) Measure with the device powered up and outputs a clock signal.
(7) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board
(8) Data rate tolerance is within ±1000 ppm
(9) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in 75 Ω.

6.6 Recommended SMBus Interface AC Timing Specifications(1)(2)(3)

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMB Bus operating frequency MODE_SEL = 0 10 100 400 kHz
tBUF Bus free time between stop and start condition 1.3 μs
tHD:STA Hold time after (repeated) start condition
After this period, the first clock is generated		 0.6 μs
tSU:STA Repeated start condition setup time 0.6 μs
tSU:STO Stop condition setup time 0.6 μs
tHD:DAT Data hold time 0 ns
tSU:DAT Data setup time 100 ns
tLOW Clock low period 1.3 μs
tHIGH Clock high period 0.6 50 μs
tF SDA fall time read operation 300 ns
tR SDA rise time read operation 300 ns
(1) SMBus operation is available 20ms after power up
(2) These specifications support SMBus 2.0 specifications
(3) These Parameters are not production tested

6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(1)(2)

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f SCK SCK frequency MODE_SEL = 1 10 20 MHz
TSCK SCK period 50 ns
tPH SCK pulse width high 0.4 × TSCK ns
tPL SCK pulse width low 0.4 × TSCK ns
tSU MOSI setup time 4 4 ns
tH MOSI hold time 4 4 ns
tSSSu SS_N setup time 14 18 ns
tSSH SS_N hold time 4 4 ns
tSSOF SS_N off time 1 μs
tODZ MISO driven to TRI-STATE time 20 ns
tOZD MISO TRI-STATE-to-Driven time 10 ns
tOD MISO output delay time 15 ns
(1) Typical values are parametric norms at VDD = 2.5 V, TA = 25ºC, and recommended operating conditions at the time of product characterization. Typical values are not production tested.
(2) These specifications support SPI 1.0 specifications.

6.8 Typical Characteristics

Typical device characteristics at TA = +25°C and VDD = 2.5 V, unless otherwise noted.
LMH1218 output1_totaljitter_8point6.png
Figure 1. 11.88 Gbps 50 Ω OUT1
LMH1218 output01188gbps_totaljitter26point4.png
Figure 3. 11.88 Gbps 75 Ω OUT0
LMH1218 2point97_gbps_output1_totaljitter21point4.png
Figure 5. 2.97 Gbps 75 Ω OUT0
LMH1218 eye_diagram_green_lmh1218.gif
Figure 7. Internal Input Eye Monitor Plot
LMH1218 output1_totaljitter_ninepointthree.png
Figure 2. 10.3125 Gbps 50 Ω OUT1
LMH1218 output0_5point94_gbps_total_jitter19point1.png
Figure 4. 5.94 Gbps 75 Ω OUT0
LMH1218 output1_totaljitter_thirtyeight_point_two.png
Figure 6. 1.485 Gbps 75 Ω OUT0
LMH1218 eye_diagram_eye_hit_density.gif
Figure 8. 11.88 Gbps Internal Eye Monitor Hit Density Plot

7 Detailed Description

7.1 Overview

The LMH1218 is a 11.88Gbps/5.94Gbps/2.97Gbps/1.485Gbps/0.27Gbps/10GbE multi-rate serial digital video data cable driver with integrated reclocker intended for equalizing, reclocking, and driving data compatible to the SMPTE standards, proposed ST-2081/2, and 10GbE specifications. It is a 2-input, 2-output single-core chip, enabling 1:2 fan-out or 2:1 MUX operation. Each input has a 100-Ω continuous time linear equalizer (CTLE) at the front-end, intended to compensate for loss over STP coax, fiber, or FR-4 backplane. OUT1 is a 100-Ω driver compatible to 10GbE SFF-8431 optical module requirements. The LMH1218 OUT0 is a 75-Ω cable driver compatible to the SMPTE and proposed ST-2081/2 requirements.

The referenceless Clock-and-Data Recovery (CDR) circuit selects between the two inputs based on user choice. The reclocked output can be driven to one or two outputs. One of the outputs supports 100-Ω differential cable connection, while the other output can drive a 75-Ω SMPTE specified cable while meeting transmitter requirements as specified in SMPTE standard. The LMH1218 locks to all required SDI data rates, including 270Mbps, 1.485 Gbps, 1.4835 Gbps, 2.97 Gbps, 2.967 Gbps, 5.94 Gbps, 5.934 Gbps, 11.88 Gbps, and 11.868 Gbps as well as 10.3125 Gbps. The LMH1218 is assembled in a 4 mm × 4 mm 24-pin QFN package. The chip can be programmed using SPI or SMBus interface.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale