LM5175 42V 宽 VIN 同步 4 开关 降压 - 升压控制器

8.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation

The LM5175 implements a fixed frequency current mode control of both the buck and boost switches. The output voltage, scaled down by the feedback resistor divider, appears at the FB pin and is compared to the internal reference (V_REF) by an internal error amplifier. The error amplifier produces an error voltage by driving the COMP pin. An adaptive slope compensation signal based on V_IN, V_OUT, and the capacitor at the SLOPE pin is added to the current sense signal measured across the CS and CSG pins. The result is compared to the COMP error voltage by the PWM comparator.

The LM5175 regulates the output using valley current mode control in buck mode and peak current mode control in boost mode. For valley current mode control, the high-side buck MOSFET controlled by HDRV1 is turned on by the PWM comparator at the valley of the inductor ripple current and turned off by the oscillator clock signal. Valley current mode control is advantageous for buck converters where the PWM controller must resolve very short on-times. For peak current mode control in the boost mode, the low-side boost MOSFET controlled by LDRV2 is turned on by the clock signal in each switching cycle and turned off by the PWM comparator at the peak of the inductor ripple current.

The low-side gate drive LDRV1, complementary to the HDRV1 drive signal, controls the synchronous rectification MOSFET of the buck stage. The high-side gate drive HDRV2, complementary to the low-side gate drive LDRV2, controls the high-side synchronous rectifier of the boost stage. For operation with V_IN close to V_OUT, the LM5175 uses a proprietary buck or boost transition scheme to achieve smooth, low ripple transition zone behavior.

Peak and valley current mode controllers require slope compensation for stable current loop operation at duty cycle greater than 50% in peak current mode control and less than 50% in valley current mode control. The LM5175 provides a SLOPE pin to program optimum slope for any V_IN and V_OUT combination using an external capacitor.

8.3.2 VCC Regulator and Optional BIAS Input

The VCC regulator provides a regulated 7.5-V bias supply to the gate drivers. When EN/UVLO is above the 0.7-V (typical) standby threshold, the VCC regulator is turned on. For V_IN less than 7.5 V, the VCC voltage tracks V_IN with a small voltage drop as shown in Figure 4. If the EN/UVLO input is above the 1.23 V operating threshold and VCC exceeds the 3.3 V (typical) VCC UV threshold, the controller is enabled and switching begins.

The VCC regulator draws power from V_IN when there is no supply voltage connected to the BIAS pin. If the BIAS pin is connected to an external voltage source that exceeds VCC by one diode drop, the VCC regulator draws power from the BIAS input instead of V_IN. Connecting the BIAS pin to V_OUT in applications with V_OUT greater than 8.5 V improves the efficiency of the regulator in the buck mode. The BIAS pin voltage should not exceed 36 V.

For low V_IN operation, ensure that the VCC voltage is sufficient to fully enhance the MOSFETs. Use an external bias supply if V_IN dips below the voltage required to sustain the VCC voltage. For these conditions, use a series blocking diode between the input supply and the VIN pin (Figure 20). This prevents VCC from back-feeding into V_IN through the body diode of the VCC regulator.

A 1-µF capacitor to PGND is required to supply the VCC regulator load transients.

Figure 20. VCC Regulator

8.3.3 Enable/UVLO

The LM5175 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has three distinct voltage ranges: shutdown, standby, and operating (see Shutdown, Standby, and Operating Modes). When the EN/UVLO pin is below the standby threshold (0.7 V typical), the converter is held in a low power shutdown mode. When EN/UVLO voltage is greater than the standby threshold but less than the 1.23 V operating threshold, the internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held low and the PWM controller is disabled. A 1.5 µA pull-up current is sourced out of the EN/UVLO pin in standby mode to provide hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than the 1.23 V operating threshold, the controller commences operation if VCC is above VCC UV threshold (3.3 V). A hysteresis current of 3.5 µA is sourced into the EN/UVLO pin when the EN/UVLO input exceeds the 1.23 V operation threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input voltage.

The V_IN undervoltage lockout turn-on threshold is typically set by a resistor divider from the VIN pin to AGND with the mid-point of the divider connected to EN/UVLO. The turn-on threshold VIN_UV is calculated using Equation 1 where R_UV2 is the upper resistor and R_UV1 is the lower resistor in the EN/UVLO resistor divider:

Equation 1.

The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by:

Equation 2.

Figure 21. UVLO Threshold Programming

8.3.4 Soft-Start

The LM5175 soft-start time is programmed using a soft-start capacitor from the SS pin to AGND. When the converter is enabled, an internal 5-µA current source charges the soft-start capacitor. When the SS pin voltage is below the 0.8-V feedback reference voltage V_REF, the soft-start pin controls the regulated FB voltage. Once SS exceeds V_REF, the soft-start interval is complete and the error amplifier is referenced to V_REF. The soft-start time is given by Equation 3:

Equation 3.

The soft-start capacitor is internally discharged when the converter is disabled because of EN/UVLO falling below the operation threshold or VCC falling below the VCC UV threshold. The soft-start pin is also discharged when the converter is in hiccup mode current limiting or in thermal shutdown. When average input or output current limiting is active, the soft-start capacitor is discharged by the constant current loop transconductance (gm) amplifier to limit either input or output current.

8.3.5 Overcurrent Protection

The LM5175 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions. In buck operation, the sensed valley voltage across the CSG and CS pins is limited to 76 mV. The high-side buck switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time. In boost operation, the maximum peak voltage across CS and CSG is limited to 170mV. If the peak current in the low-side boost switch causes the CS pin to exceed this threshold voltage, the boost switch is turned off for the remainder of the clock cycle.

Applying the appropriate voltage to the MODE pin of the LM5175 enables hiccup mode fault protection (see MODE Pin Configuration). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current limiting for 128 consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is automatically released after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is not enabled through the MODE pin, the LM5175 will operate in cycle-by-cycle current limiting as long as the overload condition persists.

8.3.6 Average Input/Output Current Limiting

The LM5175 provides optional average current limiting capability to limit either the input or the output current of the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected in series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50 mV reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the soft-start capacitor. When the soft-start capacitor discharges below the 0.8-V feedback reference voltage V_REF, the output voltage of the converter decreases to limit the input or output current. The average current limiting feature can be used in applications requiring a regulated current from the input supply or into the load. The target constant current is given by Equation 4:

Equation 4.

The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together.

8.3.7 CCM/DCM Operation

The LM5175 allows selection of continuous conduction mode (CCM) or discontinuous conduction mode (DCM) operation using the MODE pin (see MODE Pin Configuration). In CCM operation the inductor current can flow in either direction and the controller switches at a fixed frequency regardless of the load current. This mode is useful for noise-sensitive applications where a fixed switching eases filter design. In DCM operation the synchronous rectifier MOSFETs emulate diodes as LDRV1 or HDRV2 turn-off for the remainder of the PWM cycle when the inductor current reaches zero. The DCM mode results in reduced frequency operation at light loads, which lowers switching losses and increases light load efficiency of the converter.

8.3.8 Frequency and Synchronization (RT/SYNC)

The LM5175 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from the RT/SYNC pin to AGND. The R_T resistor is related to the nominal switching frequency (F_sw) by the following equation:

Equation 5.

Figure 3 in the Typical Characteristics shows the relationship between the programmed switching frequency (F_sw) and the R_T resistor.

The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The external synchronization pulse is ac coupled using a capacitor to the RT/SYNC pin. The voltage at the RT/SYNC pin must not exceed 3.3 V peak. The external synchronization pulse frequency should be higher than the internally set oscillator frequency and the pulse width should be between 75 ns and 500 ns.

Figure 22. Using External SYNC

8.3.9 Frequency Dithering

The LM5175 provides an optional frequency dithering function that is enabled by connecting a capacitor from DITH to AGND. Figure 23 illustrates the dithering circuit. A triangular waveform centered at 1.22 V is generated across the C_DITH capacitor. This triangular waveform modulates the oscillator frequency by ±5% of the nominal frequency set by the R_T resistor. The C_DITH capacitance value sets the rate of the low frequency modulation. A lower C_DITH capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the dithering circuit to effectively reduce peak EMI, the modulation rate must be much less than the oscillator frequency (F_sw). Equation 6 calculates the DITH pin capacitance required to set the modulation frequency, F_MOD. Connecting the DITH pin directly to AGND disables frequency dithering, and the internal oscillator operates at a fixed frequency set by the RT resistor. Dither is disabled when external SYNC is used.

Equation 6.

Figure 23. Dither Operation

8.3.10 Output Overvoltage Protection (OVP)

The LM5175 provides an output overvoltage protection (OVP) circuit that turns off the gate drives when the feedback voltage is 7.5% above the 0.8 V feedback reference voltage V_REF. Switching resumes once the output falls within 5% of V_REF.

8.3.11 Power Good (PGOOD)

PGOOD is an open drain output that is pulled low when the voltage at the FB pin is outside -9% / +10% of the nominal 0.8-V reference voltage. The PGOOD internal N-Channel MOSFET pull-down strength is typically 4.2 mA. This pin can be connected to a voltage supply of up to 8 V through a pull-up resistor.

8.3.12 Gm Error Amplifier

The LM5175 has a gm error amplifier for loop compensation. The gm amplifier output (COMP) range is 0.3 V to 3 V. Connect an R_c1-C_c1 compensation network between COMP and ground for type II (PI) compensation (see Figure 24). Another pole is usually added using C_c2 to suppress higher frequency noise.

The COMP output voltage (V_COMP) range limits the possible V_IN and I_OUT range for a given design. In buck mode, the maximum V_IN for which the converter can regulate the output at no load is when V_COMP reaches 0.3 V. Equation 7 gives V_COMP as a function of V_IN at no load in CCM buck mode:

Equation 7.

Where D_BUCK in the equation Equation 7 is the buck duty cycle given by:

Equation 8.

A larger L1, lower slope ripple (higher C_SLOPE), smaller sense resistor (R_SENSE), and higher frequency can increase the maximum V_IN range for buck operation.

For boost mode, the minimum V_IN for which the converter can regulate the output at full load is when V_COMP reaches 3 V. Equation 9 gives V_COMP as a function of V_IN in boost mode:

Equation 9.

Where D_BOOST in the Equation 9 is the boost duty cycle given by:

Equation 10.

A larger L1, lower slope ripple (higher C_SLOPE), smaller sense resistor (R_SENSE), and higher frequency can extend the minimum V_IN range for boost operation.

8.3.13 Integrated Gate Drivers

The LM5175 provides four N-channel MOSFET gate drivers: two floating high-side gate drivers at the HDRV1 and HDRV2 pins, and two ground referenced low-side drivers at the LDRV1 and LDRV2 pins. Each driver is capable of sourcing 1.5 A and sinking 2 A peak current. In buck operation, LDRV1 and HDRV1 are switched by the PWM controller while HDRV2 remains continuously on. In boost operation, LDRV2 and HDRV2 are switched while HDRV1 remains continuously on.

In DCM buck operation, LDRV1 and HDRV2 turn off when the inductor current drops to zero (diode emulation). In a DCM boost operation, HDRV2 turns off when inductor current drops to zero.

The gate drive output HDRV2 remains off during soft-start to prevent reverse current flow from a pre-biased output.

The low-side gate drivers are powered from VCC and the high-side gate drivers HDRV1 and HDRV2 are powered from bootstrap capacitors C_BOOT1 (between BOOT1 and SW1) and C_BOOT2 (between BOOT2 and SW2) respectively. The C_BOOT1 and C_BOOT2 capacitors are charged through external Schottky diodes connected to the VCC pin as shown in Figure 24.

8.3.14 Thermal Shutdown

The LM5175 is protected by a thermal shutdown circuit that shuts down the device when the internal junction temperature exceeds 165°C (typical). The soft-start capacitor is discharged when thermal shutdown is triggered and the gate drivers are disabled. The converter automatically restarts when the junction temperature drops by the thermal shutdown hysteresis of 15°C below the thermal shutdown threshold.

8.4.1 Shutdown, Standby, and Operating Modes

8.4.2 MODE Pin Configuration

The MODE pin is used to select CCM/DCM operation and hiccup mode current limit. Mode is latched at startup.

9.2.1 Design Requirements

For this design example, the following are used as the input parameters.

9.2.2 Detailed Design Procedure

9.2.2.2 V_OUT

The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally the bottom resistor in the resistor divider is selected to be in the 1 kΩ to 100 kΩ range. Select

Equation 11.

The top resistor in the feedback resistor divider is selected using Equation 12:

Equation 12.

9.2.2.3 Inductor Selection

The inductor selection is based on consideration of both buck and boost modes of operation. For the buck mode, inductor selection is based on limiting the peak to peak current ripple ΔI_L to ~40% of the maximum inductor current at the maximum input voltage. The target inductance for the buck mode is:

Equation 13.

For the boost mode, the inductor selection is based on limiting the peak to peak current ripple ΔI_L to ~40% of the maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:

Equation 14.

In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the converter by moving the right half plane zero to lower frequencies. Therefore a judicious compromise should be made based on the application requirements. For this design a 4.7-µH inductor is selected. With this inductor selection, the inductor current ripple is 5.7 A, 4.3 A, and 2.1 A, at V_IN of 36 V, 24 V, and 6 V respectively.

The maximum average inductor current occurs at the minimum input voltage and maximum load current:

Equation 15.

where a 90% efficiency is assumed. The peak inductor current occurs at minimum input voltage and is given by:

Equation 16.

To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in boost operation. To ensure that the inductor does not saturate in current limit, the peak saturation current of the inductor should be higher than the maximum current limit. Adjusting for a ±20% current limit threshold tolerance, the peak inductor current limit is:

Equation 17.

Therefore, the inductor saturation current should be greater than 21.6 A. If hiccup mode protection is not enabled, the RMS current rating of the inductor should be sufficient to tolerate continuous operation in cycle-by-cycle current limiting.

9.2.2.4 Output Capacitor

In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is given by Equation 18 where the minimum V_IN corresponds to the maximum capacitor current.

Equation 18.

In this example the maximum output ripple RMS current is I_COUT(RMS) = 6 A. A 5-mΩ output capacitor ESR causes an output ripple voltage of 60 mV as given by:

Equation 19.

A 400 µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:

Equation 20.

Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current capacity. The complete schematic in Figure 24 at the end of this section shows a good starting point for C_OUT for typical applications.

9.2.2.5 Input Capacitor

In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given by:

Equation 21.

The maximum RMS current occurs at D = 0.5, which gives I_CIN(RMS) = I_OUT/2 = 3 A. A combination of ceramic and bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple. The complete schematic in Figure 24 is a good starting point for C_IN for typical applications.

9.2.2.6 Sense Resistor (R_SENSE)

The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is given by:

Equation 22.

For the boost mode of operation, the current limit resistor is given by:

Equation 23.

The closest standard value of R_SENSE = 8 mΩ is selected based on the boost mode operation.

The maximum power dissipation in R_SENSE happens at V_IN(MIN):

Equation 24.

Based on this, select the current sense resistor with power rating of 2 W or higher.

For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG sense lines. Please see Figure 24 for typical values. The filter resistance should not exceed 100 Ω.

9.2.2.7 Slope Compensation

For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected based on Equation 25:

Equation 25.

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated slope capacitor value in Equation 25). A smaller slope capacitor results in larger slope signal which is better for noise immunity in the transition region (V_IN~V_OUT). A larger slope signal, however, restricts the achievable input voltage range for a given output voltage, switching frequency, and inductor. For this design C_SLOPE = 100 pF is selected for better transition region behavior while still providing the required V_IN range. This selection of slope capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error Amplifier section.

9.2.2.8 UVLO

The UVLO resistor divider must be designed for turn-on below 6V. Selecting a R_UV2 = 249 kΩ gives a UVLO hysteresis of 0.8 V. The lower UVLO resistor is the selected using Equation 26:

Equation 26.

A standard value of 59.0 kΩ is selected for R_UV1.

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs with gate (Miller) plateau voltage lower than the minimum V_IN.

9.2.2.9 Soft-Start Capacitor

The soft-start time is programmed using the soft-start capacitor. The relationship between C_SS and the soft-start time is given by:

Equation 27.

C_SS = 0.1 µF gives a soft-start time of 16 ms.

9.2.2.10 Dither Capacitor

The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching frequency. A larger C_DITH results in lower modulation frequency. For proper operation the modulation frequency (F_MOD) must be much lower than the switching frequency. Use Equation 28 to select C_DITH for the target modulation frequency.

Equation 28.

For the current design dithering is not being implemented. Therefore a 0 Ω resistor from the DITH pin to AGND disables this feature.

9.2.2.11 MOSFETs QH1 and QL1

The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 36 V. In addition they must withstand the transient spikes at SW1 during switching. Therefore QH1 and QL1 should be rated for 60 V. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.

The power loss in QH1 in the boost mode of operation is approximated by:

Equation 29.

The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss components given by Equation 30 and Equation 31 respectively:

Equation 30.

Equation 31.

The rise (t_r) and the fall (t_f) times are based on the MOSFET datasheet information or measured in the lab. Typically a MOSFET with smaller R_DSON (smaller conduction loss) will have longer rise and fall times (larger switching loss).

The power loss in QL1 in the buck mode of operation is given by the following equation:

Equation 32.

9.2.2.12 MOSFETs QH2 and QL2

The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2 during switching. Therefore QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.

The power loss in QH2 in the buck mode of operation is approximated by:

Equation 33.

The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss components given by Equation 34 and Equation 35 respectively:

Equation 34.

Equation 35.

The rise (t_r) and the fall (t_f) times can be based on the MOSFET datasheet information or measured in the lab. Typically a MOSFET with smaller R_DSON (lower conduction loss) has longer rise and fall times (larger switching loss).

The power loss in QH2 in the boost mode of operation is given by the following equation:

Equation 36.

9.2.2.13 Frequency Compensation

This section presents the control loop compensation design procedure for the LM5175 buck-boost controller. The LM5175 operates mainly in buck or boost modes, separated by a transition region, and therefore the control loop design is done for both buck and boost operating modes. Then a final selection of compensation is made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter designed to go deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the presence of a right half plane zero (RHPZ) in the boost mode.

The boost power stage output pole location is given by:

Equation 37.

where R_OUT = 2 Ω corresponds to the maximum load of 6 A.

The boost power stage ESR zero location is given by:

Equation 38.

The boost power stage RHP zero location is given by:

Equation 39.

where D_MAX is the maximum duty cycle at the minimum V_IN.

The buck power stage output pole location is given by:

Equation 40.

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 39 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:

Equation 41.

For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum duty cycle (D_MAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by the RHP zero (f_RHP/3) with 1/20 of the switching frequency and use the smaller of the two values as the achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost loop:

Equation 42.

If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the crossover, the compensation gain resistor R_c1 is calculated using the approximation:

Equation 43.

where D_MAX is the maximum duty cycle at the minimum V_IN in boost mode and A_CS is the current sense amplifier gain. The compensation capacitor C_c1 is then calculated from:

Equation 44.

The standard values of compensation components are selected to be R_c1 = 10 kΩ and C_c1 = 22 nF.

A high frequency pole is added to suppress switching noise using a 100 pF capacitor (C_c2) in parallel with R_c1 and C_c1. These values provide a good starting point for the compensation design. Each design should be tuned in the lab to achieve the desired balance between stability margin across the operating range and transient response time.

9.2.3 Application Curves

Figure 25. Efficiency vs Load

Figure 27. Load Transient Response

Figure 26. Output Voltage Ripple

Figure 28. Line Transient Response (8 V - 24 V, I_OUT = 2 A)