DS90UB927Q-Q1 具有双向控制通道的 5MHz 至 85MHz 24 位彩色 FPD-Link III 串行器

7.3.1 High-Speed Forward Channel Data Transfer

The High Speed Forward Channel is composed of a 35-bit frame containing RGB data, sync signals, I²C, and I²S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the serial stream generated per PCLK cycle into RxCLKIN±. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, DC-balanced and scrambled.

Figure 13. FPD-Link III Serial Stream

The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0). This corresponds to an application payload rate range of 155 Mbps to 2.635 Gbps, with an actual line rate range of 525 Mbps to 2.975 Gbps.

7.3.2 Low-Speed Back Channel Data Transfer

The Low-Speed Back Channel of the DS90UB927Q-Q1 provides bidirectional communication between the display and host processor. Data is transferred simultaneously over the same physical link as the high-speed forward channel data. The back channel transports I²C, CRC, and 4 bits of standard GPIO information with a 10-Mbps line rate.

7.3.3 Common Mode Filter Pin (CMF)

The serializer provides access to the center tap of the internal CML termination. A 0.1-μF capacitor must be connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 29). This increases noise rejection capability in high-noise environments.

7.3.4 Video Control Signals

The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations relative to the video pixel clock period (PCLK). By default, the DS90UB927Q-Q1 applies a minimum pulse width filter on these signals to help eliminate spurious transitions.

Normal Mode Control Signals (VS, HS, DE) have the following restrictions:

• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 5. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 5. DE can have at most two transitions per 130 PCLKs.

7.3.5 EMI Reduction Features

7.3.6 Built-In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-speed back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics.

7.3.6.2 Sample BIST Sequence

Step 1: For the DS90UB927Q-Q1 paired with a FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the deserializer BISTC pin.

Step 2: The DS90UB927Q-Q1 serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may be of any length.

The link returns to normal operation after the deserializer BISTEN pin is low. Figure 15 shows the waveform diagram of a typical BIST for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx Equalization).

Figure 14. BIST Mode Flow Diagram

7.3.7 Forward Channel and Back Channel Error Checking

While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all zeroes pattern. The internal all-zeroes pattern goes through scrambler, DC-balancing, and so forth, and is transmitted over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the recovered serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.

The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream, as indicated by link detect status (register bit 0x0C[0] - Table 5). CRC errors are recorded in an 8-bit register in the serializer. The register is cleared when the serializer enters BIST mode. As soon as the serializer enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps a record of the last BIST run until cleared or the serializer enters BIST mode again.

Figure 15. BIST Waveforms

7.3.8 Internal Pattern Generation

The DS90UB927Q-Q1 serializer provides an internal pattern generation feature. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application Note AN-2198.

7.3.9 Remote Auto Power-Down Mode

The DS90UB927Q-Q1 serializer features a Remote Auto Power Down mode. This feature is enabled and disabled through the register bit 0x01[7] (Table 5). When the back channel is not detected, either due to an idle or powered-down deserializer, the serializer enters remote auto power down mode. Power dissipation of the serializer is significantly reduced in this mode. The serializer automatically attempts to resume normal operation upon detection of an active back channel from the deserializer. To complete the wake-up process and reactivate forward channel operation, the remote power-down feature must be disabled by either a local I²C host, or by an auto-ACK I²C transaction from a remote I²C host located at the deserializer. The Remote Auto Power Down Sleep/Wake cycle is shown below in Figure 16:

Figure 16. Remote Auto Power Down Sleep/Wake Cycle

To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control register. This may be accomplished from a local I²C controller by writing reg_0x01[7]=0 (Table 5). To disable from a remote I²C controller located at the deserializer, perform the following procedure to complete the wake-up process:

1. Power up remote deserializer (back channel must be active)
2. Enable I²C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1
3. Enable I²C AUTO ACK by setting deserializer register reg_0x03[2]=1
4. Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0
5. Disable I²C AUTO ACK by setting deserializer register reg_0x03[2]=0
6. Disable I²C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0

7.3.10 Input RxCLKIN Loss Detect

The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A clock loss condition is detected when PCLK drops below approximately 1 MHz. When a PCLK is detected again, the serializer will then lock to the incoming RxCLKIN±. Note – when RxCLKIN± is lost, the optional Serial Bus Control Registers values are still retained. See (Table 5) for more information.

7.3.11 Serial Link Fault Detect

The DS90UB927Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 5). The DS90UB927Q-Q1 will detect any of the following conditions:

1. Cable open
2. “+” to “-” short
3. ”+” to GND short
4. ”-” to GND short
5. ”+” to battery short
6. ”-” to battery short
7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed)

Note: The device will detect any of the above conditions, but does not report specifically which one has occurred.

7.3.12 Interrupt Pin (INTB)

1. On the DS90UB927Q-Q1 serializer, set register reg_0xC6[5] = 1 and 0xC6[0] = 1 (Table 5) to configure the interrupt.
2. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.
3. When INTB_IN on the deserializer (DS90UB926Q-Q1 or DS90UB928Q-Q1) is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
4. The external controller detects INTB = LOW and reads the ISR register (Table 5) to determine the interrupt source. Reading this register also clears and resets the interrupt.

7.3.13 General-Purpose I/O

7.3.14 I²S Audio Interface

The DS90UB927Q-Q1 serializer features six I²S input pins that, when paired with a DS90UB928Q-Q1 deserializer, supports surround sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1 MHz and <PCLK/2 (or <13 MHz). Four I²S data inputs transport two channels of I²S-formatted digital audio each, with each channel delineated by the word select (I2C_WC) input. I²S audio transport is not available in Backwards Compatibility Mode (BKWD = 1).

Figure 17. I²S Connection Diagram

Figure 18. I²S Frame Timing Diagram

When paired with a DS90UB926Q-Q1, the DS90UB927Q-Q1 I²S interface supports a single I²S data input through I2S_DA (24-bit video mode), or two I²S data inputs through I2S_DA and I2S_DB (18-bit video mode).

Table 3 covers several common I²S sample rates:

7.3.15 Additional Features

Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 5) and the Pattern Generator Indirect Data (PGID reg_0x67 — Table 5). See TI application Note AN-2198.

7.4.1 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device, or through V_DDIO, where V_DDIO = 3.0 V to 3.6 V or V_DD33. To save power, disable the link when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before releasing or driving high. In the case where PDB is pulled up to V_DDIO = 3.0 V to 3.6 V or V_DD33 directly, a 10-kΩ pullup resistor and a >10-µF capacitor to ground are required (See Figure 29).

Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held low for a minimum period of time. See AC Electrical Characteristics for more information.

7.4.2 Backward Compatible Mode

The DS90UB927Q-Q1 is also backward compatible to DS90UR906Q, DS90UR908Q FPD, and DS90UR916Q FPD-Link II deserializers for PCLK frequencies ranging from 5MHz to 65MHz. It is also backward compatible with the DS90UR910Q for PCLK frequencies ranging from 5 MHz to 75 MHz. The serializer transmits 28-bits of data over a single serial FPD-Link II pair operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1 Gbps. The Backward Compatibility configuration can be selected through the BKWD pin or programmed through the configuration register (Table 5). The bidirectional control channel, bidirectional GPIOs, I²S, and interrupt (INTB) are not active in this mode. However, local I²C access to the serializer is still available. Note: PCLK frequency range in this mode is 15 MHz to 75 MHz for LFMODE=0 and 5 MHZ to <15 MHz for LFMODE=1.

7.4.3 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (Table 5) or LFMODE Pin. This mode optimizes device operation for lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE = 0, default), the RxCLKIN± frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE = 1), the RxCLKIN± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by four. Thus, for the operating range of 5MHz to <15MHz, the line rate is 700Mbps to <2.1Gbps with an effective data payload of 175Mbps to 525Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative to the input data rate remains the same.

7.4.4 FPD-Link Input Frame and Color Bit Mapping Select

The DS90UB927Q-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN[3]±, shown in Figure 19, or MSBs on RxIN[3], shown in Figure 20. Each frame corresponds to a single-pixel clock (PCLK) cycle. The LVDS clock input to RxCLKIN± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 5).

Figure 19. FPD-Link Mapping: LSBs on RxIN3 (MAPSEL=L)

Figure 20. FPD-Link Mapping: MSBs on RxIN3 (MAPSEL=H)

7.4.5 Repeater

The supported Repeater application provides a mechanism to extend transmission over multiple links to multiple display devices.

7.4.5.1 Repeater Configuration

In the repeater application, this document refers to the DS90UB927Q-Q1 as the Transmitter (TX), and refers to the DS90UB928Q-Q1 as the Receiver (RX). Figure 21 shows the maximum configuration supported for Repeater implementations using the DS90UB925/7Q-Q1 (TX), and DS90UB926/8Q-Q1 (RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver. To ensure parallel video interface compatibility, repeater nodes should feature either the DS90UB926Q-Q1/DS90UB925Q (RX/TX) chipset or the DS90UB927Q-Q1/DS90UB928Q-Q1 (TX/RX) chipset.

Figure 21. Maximum Repeater Application

In a repeater application, the I²C interface at each TX and RX may be configured to transparently pass I²C communications upstream or downstream to any I²C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

At each repeater node, the FPD-Link interface fans out to up to three serializer devices, providing video, audio, and control signals and, optionally, packetized audio data (transported during video blanking intervals). Alternatively, the I²S audio interface may be used to transport digital audio data between receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the receiver and is received by the transmitter.

If video data is output to a local display, White Balancing and Hi-FRC dithering functions should not be used as they will block encrypted I²S audio.

Figure 22. 1:2 Repeater Configuration

7.4.5.2 Repeater Connections

The Repeater requires the following connections between the Receiver and Transmitter Figure 23.

1. Video Data – Connect all FPD-Link data and clock pairs
2. I²C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33 or V_DDIO = 3.0 V to 3.6 V with 4.7-kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have a unique I²C address.
5. REPEAT pin — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UB928Q-Q1 INTB_IN pin to DS90UB927Q-Q1 INTB pin. The signal must be pulled up to V_DDIO.

Figure 23. Repeater Connection Diagram

7.4.5.2.1 Repeater Fan-Out Electrical Requirements

Repeater applications requiring fan-out from one DS90UB928Q-Q1 deserializer to up to three DS90UB927Q-Q1 serializers requires special considerations for routing and termination of the FPD-Link differential traces. Figure 24 details the requirements that must be met for each signal pair:

Figure 24. FPD-Link Fan-Out Electrical Requirements

7.5.1 Serial Control Bus

The DS90UB927Q-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 25 below) connected to the IDx pin.

Figure 25. Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to V_DD33 or V_DDIO = 3.0 V to 3.6 V. For most applications, a 4.7-kΩ pullup resistor to V_DD33 is recommended. However, the pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

The IDx pin configures the control interface to one of 10 possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each ratio corresponding to a specific device address. See Table 5 below.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 26.

Figure 26. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 27 and a WRITE is shown in Figure 28.

Figure 27. Serial Control Bus — READ

Figure 28. Serial Control Bus — WRITE

The I²C Master located at the DS90UB927Q-Q1 serializer must support I²C clock stretching. For more information on I²C interface requirements and throughput considerations, refer to TI Application Note SNLA131.

Table 5. Serial Control Bus Registers

8.2.1 Design Requirements

For the typical design application, use the following as input parameters.

8.2.2 Detailed Design Procedure

Figure 29 shows a typical application of the DS90UB927Q-Q1 serializer for an 85-MHz 24-bit Color Display Application. The CML outputs must have an external 0.1-μF AC coupling capacitor on the high speed serial lines. Bypass capacitors are placed near the power supply pins. At a minimum, six 4.7-μF capacitors and two additional 1-μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two VDDs (VDD33 and VDDIO) for effective noise suppression. An RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.

8.2.3 Application Curves

Figure 30. Serializer Output Stream with 48-MHz Input Clock

Figure 31. Serializer Eye with 48-MHz Input Clock

10.1.1 CML Interconnect Guidelines

See SNLA008 and SNLA035 for full details.

• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
  • – S = space between the pair
  • – 2S = space between pairs
  • – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible.

Additional general guidance can be found in the LVDS Owner’s Manual - available at: SNLA187