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  • ISO7842x 高性能、8000VPK 增强型四通道数字隔离器

    • ZHCSD14G October   2014  – March 2017 ISO7842

      PRODUCTION DATA.  

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  • ISO7842x 高性能、8000VPK 增强型四通道数字隔离器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics-5-V Supply
    10. 6.10 Supply Current Characteristics-5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Switching Characteristics—5-V Supply
    16. 6.16 Switching Characteristics—3.3-V Supply
    17. 6.17 Switching Characteristics—2.5-V Supply
    18. 6.18 Insulation Characteristics Curves
    19. 6.19 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

ISO7842x 高性能、8000VPK 增强型四通道数字隔离器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 信号传输速率：高达 100Mbps
  • 宽电源电压范围：2.25V 至 5.5V
  • 2.25V 至 5.5V 电平转换
  • 宽温度范围：–55°C 至 +125°C
  • 低功耗：电流典型值为 1.7mA/通道（1Mbps 时）
  • 低传播延迟：典型值为 11ns
    （5V 电源供电时）
  • 行业领先的 CMTI（最小值）：±100 kV/μs
  • 优异的电磁兼容性 (EMC)
  • 系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪涌保护
  • 低辐射
  • 隔离层寿命：40 年以上
  • 宽体 SOIC-16 封装和超宽体 SOIC-16 封装选项
  • 安全及管理批准：中的“安全及管理批准”列表中的“安全及管理批准”列表
    • 8000 VPK 增强型隔离，符合 DIN V VDE V 0884-10 (VDE V 0884-10)：2006-12
    • 符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS 隔离
    • CSA 组件验收通知 5A，IEC 60950-1 和 IEC 60601-1 终端设备标准
    • 符合 GB4943.1-2011 标准的 CQC 认证
    • 符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证
    • 完成了所有 DW 封装认证；完成了符合 UL、VDE、TUV 标准的 DWW 封装认证并且已针对 CSA 和 CQC 进行了规划

2 应用

  • 工业自动化
  • 电机控制
  • 电源
  • 太阳能逆变器
  • 医疗设备
  • 混合动力电动汽车

3 说明

ISO7842x 器件是一款高性能四通道数字隔离器，隔离电压为 8000VPK。该器件已通过符合 VDE、CSA、CQC 和 TUV 标准的增强型隔离认证。在隔离互补金属氧化物半导体 (CMOS) 或者低电压互补金属氧化物半导体 (LVCMOS) 数字 I/O 时，该隔离器可提供高电磁抗扰度和低辐射，同时具备低功耗特性。每个隔离通道都有一个由二氧化硅 (SiO2) 绝缘隔栅分开的逻辑输入和输出缓冲器。

该器件配有使能引脚，可用于将多个主驱动应用中的相应输出置于 高阻抗状态， 也可用于降低功耗。ISO7842 器件具有 2 个正向通道和 2 个反向通道。如果出现输入功率或信号丢失，ISO7842 器件默认输出高电平，ISO7842F 器件默认输出低电平。有关更多详细信息，请参阅 Device Functional Modes器件功能模式部分。

与隔离式电源结合使用时，该器件有助于防止数据总线或者其他电路中的噪声电流进入本地接地，进而干扰或损坏敏感电路。凭借创新的芯片设计和布线技术，ISO7842 器件的电磁兼容性得到了显著增强，可确保提供系统级 ESD、EFT 和浪涌保护并符合辐射标准。

ISO7842 器件采用 16 引脚 SOIC 宽体 (DW) 和超宽体 (DWW) 封装。

器件信息(1)

产品型号 封装 封装尺寸（标称值）
ISO7842
ISO7842F		 DW (16) 10.30mm x 7.50mm
DWW (16) 10.30mm x 14.0mm
  1. 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简化电路原理图

ISO7842 ISO7842F Simplified_Schematic_sllsei6.gif
VCCI 和 GNDI 分别是输入通道的电源和接地连接。
VCCO 和 GNDO 分别是输出通道的电源和接地连接。

4 修订历史记录

Changes from F Revision (April 2016) to G Revision

  • Changed part numbers in the Power Ratings table (previously Power Dissipation Characteristics) Go
  • Changed the input-to-output test voltage parameter to apparent charge in the Insulation Specifications Go
  • Added 接收文档更新通知部分Go

Changes from E Revision (March 2016) to F Revision

  • Changed 隔离层寿命年数（特性部分）Go
  • VDE 认证现在已完成Go
  • Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical characteristics tablesGo
  • Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics tablesGo
  • Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section Go

Changes from D Revision (December 2015) to E Revision

  • 更改了特性Go
  • 在特性中添加了“符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证”Go
  • 将说明的第一段中的文本从“符合 VDE、CSA 和 CQC 的认证” 更改为“符合 VDE、CSA、CQC 和 TUV 的认证。”Go
  • Added Note 1 to Insulation Characteristics Go
  • Changed IEC 60664-1 Ratings TableGo
  • Added TUV to the Regulatory Information section and Regulatory Information. Deleted Note 1 in Regulatory Information Go
  • Changed Device I/O Schematics Go

Changes from C Revision (July 2015) to D Revision

  • 在特性中添加了“完成了 DW 封装认证；规划了 DWW 认证”Go
  • 向说明部分添加了文本：“和超宽体 (DWW) 封装”。Go
  • 已将封装“超宽 SOIC、DWW (16)”添加至器件信息表Go
  • Added the 16-DWW Package to Package Insulation and Safety-Related SpecificationsGo
  • Added the DWW package information to Package Insulation and Safety-Related SpecificationsGo
  • Added the DWW package information to Regulatory InformationGo
  • Changed the MIN value of CMTI in Electrical Characteristics–5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics–5-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics–5-V SupplyGo
  • Changed the MIN value of CMTI in Electrical Characteristics—3.3-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—3.3-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—3.3-V SupplyGo
  • Changed the MIN value of CMTI in Electrical Characteristics—2.5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—2.5-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—2.5-V SupplyGo
  • Added text to the Application Information section: " isolation voltage per UL 1577." Go

Changes from B Revision (April 2015) to C Revision

  • 已添加器件 ISO7482F 至数据表Go
  • 已更改 说明以包含“ISO7842 器件默认输出为“高”，ISO7842F 器件默认输出为“低””。Go
  • Changed Thermal Derating Curve for Safety Limiting Current per VDE , Added Thermal Derating Curve for Safety Limiting Power per VDEGo
  • Changed From: tPLH and tPHLat 5.5V To: tPLH and tPHL at 5.0 V Go
  • Changed Default Output Delay Time Test Circuit and Voltage WaveformsGo
  • Added the Device I/O Schematics section Go

Changes from A Revision (November 2014) to B Revision

  • 已将文档标题从“四通道数字隔离器”更改为“四通道 2/2 数字隔离器”Go
  • 在特性部分添加了“2.25V 至 5.5V 电平转换”Go
  • 将特性中的“宽体 SOIC-16 封装”更改为“宽体和超宽体 SOIC-16 封装选项”Go
  • 更改了特性Go
  • VDE 认证现在已完成Go
  • 更改了简化电路原理图并增加了注释 1 和注释 2Go
  • Added the Power Dissipation Characteristics tableGo
  • Changed Package Insulation and Safety-Related SpecificationsGo
  • Changed Insulation Characteristics title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To: Insulation CharacteristicsGo
  • Changed Insulation Characteristics Go
  • Changed the Test Condition of CTI of the table in Package Insulation and Safety-Related Specifications Go
  • Changed the MIN value of CTI From" > 600 V To: 600 V Go
  • Changed the table in Regulatory InformationGo
  • Changed Switching Characteristics Test Circuit and Voltage Waveforms Go
  • Changed Enable/Disable Propagation Delay Time Test Circuit and Waveform Go
  • Changed From: VCC1 To: VCCI in Default Output Delay Time Test Circuit and Voltage WaveformsGo
  • Changed Common-Mode Transient Immunity Test CircuitGo
  • Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Function Table Go
  • Changed the Application Information section Go
  • Changed the Application Information section Go
  • Added text and typical circuit hook-up figure to the Detailed Design Procedure section Go

Changes from * Revision (October 2014) to A Revision

  • 将“特性”中的“所有机构批准待定”更改为“所有机构批准已规划”Go
  • 将 说明 部分的语句从“该器件已通过 VDE 和 CSA 认证，满足增强型隔离要求。” 更改为“该器件正在就是否满足增强型隔离要求进行 VDE 和 CSA 审核认证。”Go
  • Changed RIO MIN value From: 109 To: 1011 in the Package Insulation and Safety-Related Specifications table Go
  • Changed the first row of information in the Regulatory Information table Go

5 Pin Configuration and Functions

DW and DWW Packages
16-Pin SOIC
Top View
ISO7842 ISO7842F Po_sllsej0.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN1 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low.
GND1 2 — Ground connection for VCC1
8
GND2 9 — Ground connection for VCC2
15
INA 3 I Input, channel A
INB 4 I Input, channel B
INC 12 I Input, channel C
IND 11 I Input, channel D
OUTA 14 O Output, channel A
OUTB 13 O Output, channel B
OUTC 5 O Output, channel C
OUTD 6 O Output, channel D
VCC1 1 — Power supply, VCC1
VCC2 16 — Power supply, VCC2

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
VCC1,
VCC2 		Supply voltage(2) –0.5 6 V
Voltage INx –0.5 VCCX + 0.5(3) V
OUTx –0.5 VCCX + 0.5(3)
ENx –0.5 VCCX + 0.5(3)
IO Output current –15 15 mA
Surge immunity 12.8 kV
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(2) = 5 V –4 mA
VCCO(2) = 3.3 V –2
VCCO(2) = 2.5 V –1
IOL Low-level output current VCCO(2) = 5 V 4 mA
VCCO(2) = 3.3 V 2
VCCO(2) = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI (2) VCCI (2) V
VIL Low-level input voltage 0 0.3 × VCCI(2) V
DR Signaling rate 0 100 Mbps
TJ Junction temperature(1) –55 150 °C
TA Ambient temperature –55 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see Thermal Information.
(2) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.4 Thermal Information

ISO7842 UNIT
THERMAL METRIC(1) DW (SOIC) DWW (SOIC)
16 Pins 16 Pins
RθJA Junction-to-ambient thermal resistance 78.9 78.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 41.6 41.1 °C/W
RθJB Junction-to-board thermal resistance 43.6 49.5 °C/W
ψJT Junction-to-top characterization parameter 15.5 15.2 °C/W
ψJB Junction-to-board characterization parameter 43.1 48.8 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation by ISO7842x 200 mW
PD1 Maximum power dissipation by side-1 of ISO7842x 100 mW
PD2 Maximum power dissipation by side-2 of ISO7842x 100 mW

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
DW DWW
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air >8 >14.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surfaceHigh Voltage Feature Description >8 >14.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I–IV I–IV
Rated mains voltage ≤ 1000 VRMS I–III I–IV
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage 2121 2828 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); Time dependent dielectric breakdown (TDDB) Test, see Figure 1 and Figure 2 1500 2000 VRMS
DC voltage 2121 2828 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)		 8000 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		 8000 8000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK (DWW), tm = 10 s		 ≤5 ≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK (DWW), tm = 10 s		 ≤5 ≤5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK (DWW), tm = 1 s		 ≤5 ≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 2 2 pF
RIO Isolation resistance, input to output(5) VIO = 500 V, TA = 25°C >1012 >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011
VIO = 500 V at TS = 150°C >109 >109
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)		 5700 5700 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and planned for CSA and CQC.
VDE CSA UL CQC TUV
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 Certified according to UL 1577 Component Recognition Program Certified according to GB 4943.1-2011 Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation
Maximum transient isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage, 2121 VPK (DW), 2828 VPK (DWW);
Maximum surge isolation voltage, 8000 VPK		 Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 VRMS (DW package) and 1450 VRMS (DWW package) max working voltage (pollution degree 2, material group I);
2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage (DW package)		 Single protection, 5700 VRMS Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage 5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW package) and 1000 VRMS (DWW package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working voltage of 800 VRMS (DW package) and 1450 VRMS (DWW package)
Certificate number: 40040142 Master contract number: 220991 File number: E181974 Certificate number: CQC15001121716 Client ID number: 77311

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current RθJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 288 mA
RθJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 440
RθJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C 576
PS Safety input, output, or total power RθJA = 78.9°C/W, TJ = 150°C, TA = 25°C 1584 mW
TS Maximum safety temperature 150 °C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics–5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI (1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
CI Input capacitance VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.10 Supply Current Characteristics–5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 4.2 5.6 mA
100 Mbps ICC1, ICC2 13.7 16.6 mA
ISO7842DWW AND ISO7842FDWW
Supply current Disable EN1 = EN2 = 0V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.3 5.9 mA
100 Mbps ICC1, ICC2 14 17.3 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.11 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.12 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.5 mA
10 Mbps ICC1, ICC2 4 5.2 mA
100 Mbps ICC1, ICC2 10.8 12.9 mA
ISO7842DWW and ISO7842FDWW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.1 5.5 mA
100 Mbps ICC1, ICC2 11 13.6 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.13 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.14 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.2 4.5 mA
10 Mbps ICC1, ICC2 3.7 5.1 mA
100 Mbps ICC1, ICC2 8.9 10.8 mA
ISO7842DWW AND ISO7842FDWW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 3.8 5.3 mA
100 Mbps ICC1, ICC2 9 11.5 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.15 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 11 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.55 4.1 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.5 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 1.7 3.9 ns
tf Output signal fall time 1.9 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 12 20 ns
tPLZ Disable propagation delay, low-to-high impedance output 12 20 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 10 20 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 10 20 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.90 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.16 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 10.8 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.7 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 0.8 3 ns
tf Output signal fall time 0.8 3 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 17 32 ns
tPLZ Disable propagation delay, low-to-high impedance output 17 32 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 17 32 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 17 32 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.17 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 7.5 11.7 17.5 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.66 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction Channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 1 3.5 ns
tf Output signal fall time 1.2 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 22 45 ns
tPLZ Disable propagation delay, low-to-high impedance output 22 45 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 18 45 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 18 45 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.18 Insulation Characteristics Curves

ISO7842 ISO7842F tddb_curve_reinforced_dw.gif
TA upto 150°C Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
Figure 1. Reinforced Isolation Capacitor Life Time Projection for Devices in DW Package
ISO7842 ISO7842F tddb_curve_reinforced_dww.gif
TA upto 150°C Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 2. Reinforced Isolation Capacitor Life Time Projection for Devices in DWW Package
ISO7842 ISO7842F D014_SLLSEJ0.gif Figure 3. Thermal Derating Curve for Limiting Current per VDE
ISO7842 ISO7842F D015_SLLSEJ0.gif Figure 4. Thermal Derating Curve for Limiting Power per VDE

6.19 Typical Characteristics

ISO7842 ISO7842F D001_SLLSEJ0.gif
TA = 25°C CL = 15 pF
Figure 5. Supply Current vs Data Rate (With 15-pF Load)
ISO7842 ISO7842F D003_SLLSEJ0.gif
TA = 25°C
Figure 7. High-Level Output Voltage vs High-level Output Current
ISO7842 ISO7842F D005_SLLSEJ0.gif
Figure 9. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7842 ISO7842F D002_SLLSEJ0.gif
TA = 25°C CL = No Load
Figure 6. Supply Current vs Data Rate (With No Load)
ISO7842 ISO7842F D004_SLLSEJ0.gif
TA = 25°C
Figure 8. Low-Level Output Voltage vs Low-Level Output Current
ISO7842 ISO7842F D006_SLLSEJ0.gif
Figure 10. Propagation Delay Time vs Free-Air Temperature

7 Parameter Measurement Information

ISO7842 ISO7842F switch_test_circuit_sllsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
ISO7842 ISO7842F delay_tim_llsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7842 ISO7842F failsafe_LLSE83.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Default Output Delay Time Test Circuit and Voltage Waveforms
ISO7842 ISO7842F com_tran_imm_test_circ_sllsek9.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit

8 Detailed Description

8.1 Overview

The ISO7842 device uses an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low then the output goes to high impedance. The ISO7842 device also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions because of the high-frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 15, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

ISO7842 ISO7842F fbd_sllsej0.gif Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 16 shows a conceptual detail of how the ON-OFF keying scheme works.

ISO7842 ISO7842F on_off_keying_sllsej0.gif Figure 16. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

Table 1 lists the device features.

Table 1. Device Features

PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7842 2 Forward,
5700 VRMS / 8000 VPK (1) 100 Mbps High
2 Reverse
ISO7842F 2 Forward,
5700 VRMS / 8000 VPK (1) 100 Mbps Low
2 Reverse
(1) See for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7842 device incorporates many chip-level design improvements for overall system robustness. Some of these improvements include

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

8.4 Device Functional Modes

Table 2 lists the ISO7842 functional modes.

Table 2. Function Table(1)

VCCI VCCO INPUT
(INx)(3)		 OUTPUT ENABLE
(ENx)		 OUTPUT
(OUTx)		 COMMENTS
PU PU H H or open H Normal Operation:
A channel output assumes the logic state of its input.
L H or open L
Open H or open Default Default mode: When INx is open, the corresponding channel output goes to its default logic state. Default= High for ISO7842 and Low for ISO7842F.
X PU X L Z A low value of Output Enable causes the outputs to be high-impedance
PD PU X H or open Default Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option. Default= High for IISO7842 and Low for ISO7842F.
When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state.
X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined (2).
When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.

8.4.1 Device I/O Schematics

ISO7842 ISO7842F device_IO_sllen2.gif Figure 17. Device I/O Schematics

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO7842 device is a high-performance, quad-channel digital isolator with a 5.7-kVRMS isolation voltage per UL 1577. The device comes with enable pins on each side that can be used to put the respective outputs in high impedance for multi-master driving applications and reduce power consumption. The ISO7842 device uses single-ended CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard.

9.2 Typical Application

Figure 18 shows the typical isolated RS-232 interface implementation.

ISO7842 ISO7842F Apps_Circuits3_sllsej0.gif Figure 18. Isolated RS-232 Interface

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 3.

Table 3. Design Parameters

PARAMETER VALUE
Supply voltage 2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1 0.1 µF
Decoupling capacitor from VCC2 and GND2 0.1 µF

9.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the ISO7842 device only requires two external bypass capacitors to operate.

ISO7842 ISO7842F applications_information_sllsej0.gif Figure 19. Typical ISO7842 Circuit Hook-Up

9.2.3 Application Curve

The typical eye diagram of the ISO7842 device indicates low jitter and wide open eye at the maximum data rate of 100 Mbps.

ISO7842 ISO7842F Ch1_5p0_100M_PRBS_sllsej0.png Figure 20. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C

10 Power Supply Recommendations

To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas InstrumentsSN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies.

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to Digital Isolator Design Guide.

11.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics.

11.2 Layout Example

ISO7842 ISO7842F Layout_sllsei8.gif Figure 21. Layout Example Schematic

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

相关文档如下：

  • 数字隔离器设计指南
  • 隔离相关术语
  • 《LP2985 具有关断模式的 150mA 低噪声低压降稳压器》
  • 《MSP430G2x32、MSP430G2x02 混合信号微控制器》
  • 《SN6501 用于隔离电源的变压器驱动器》
  • 《TRS232 具有 IEC61000-4-2 保护的双路 RS-232 驱动器/接收器》

12.2 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买链接。

Table 4. 相关链接

器件 产品文件夹 立即订购 技术文档 工具与软件 支持与社区
ISO7842 请单击此处 请单击此处 请单击此处 请单击此处 请单击此处
ISO7842F 请单击此处 请单击此处 请单击此处 请单击此处 请单击此处

12.3 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

esds-image

这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

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重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据 JESD48最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权限作出任何保证或解释。TI所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。

客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而对 TI及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面向军事或航空航天用途的 TI组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949要求，TI不承担任何责任。

产品

  • 数字音频: www.ti.com.cn/audio
  • 放大器和线性器件: www.ti.com.cn/amplifiers
  • 数据转换器: www.ti.com.cn/dataconverters
  • DLP® 产品: www.dlp.com
  • DSP - 数字信号处理器: www.ti.com.cn/dsp
  • 时钟和计时器: www.ti.com.cn/clockandtimers
  • 接口: www.ti.com.cn/interface
  • 逻辑: www.ti.com.cn/logic
  • 电源管理: www.ti.com.cn/power
  • 微控制器 (MCU): www.ti.com.cn/microcontrollers
  • RFID 系统: www.ti.com.cn/rfidsys
  • OMAP应用处理器: www.ti.com/omap
  • 无线连通性: www.ti.com.cn/wirelessconnectivity

应用

  • 通信与电信: www.ti.com.cn/telecom
  • 计算机及周边: www.ti.com.cn/computer
  • 消费电子: www.ti.com/consumer-apps
  • 能源: www.ti.com/energy
  • 工业应用: www.ti.com.cn/industrial
  • 医疗电子: www.ti.com.cn/medical
  • 安防应用: www.ti.com.cn/security
  • 汽车电子: www.ti.com.cn/automotive
  • 视频和影像: www.ti.com.cn/video

德州仪器在线技术支持社区: www.deyisupport.com

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