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  • TPS65263 具有 I2C 控制型动态电压调节功能的 4.5V 至 18V 输入电压、3A/2A/2A 输出电流三路同步降压转换器

    • ZHCSCV2C june   2014  – may 2023 TPS65263

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  • TPS65263 具有 I2C 控制型动态电压调节功能的 4.5V 至 18V 输入电压、3A/2A/2A 输出电流三路同步降压转换器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  Pulse Skipping Mode (PSM)
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection
        1. 8.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 I2C Update Sequence
    5. 8.5 Register Maps
      1. 8.5.1 Register Description
      2. 8.5.2 VOUT1_SEL: Vout1 Voltage Selection Register (offset = 0x00H)
      3. 8.5.3 VOUT2_SEL: Vout2 Voltage Selection Register (offset = 0x01H)
      4. 8.5.4 VOUT3_SEL: Vout3 Voltage Selection Register (offset = 0x02H)
      5. 8.5.5 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      6. 8.5.6 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      7. 8.5.7 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      8. 8.5.8 SYS_STATUS: System Status Register (offset = 0x06H)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
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Data Sheet

TPS65263 具有 I2C 控制型动态电压调节功能的 4.5V 至 18V 输入电压、3A/2A/2A 输出电流三路同步降压转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 工作输入电压范围 4.5V 至 18V，连续输出电流 3A/2A/2A
  • 通过 I2C 控制型 7 位 VID 可为每个降压转换器实现可编程输出电压范围为 0.68V 至 1.95V，阶跃为 10mV
  • I2C 控制型 VID 电压转换压摆率
  • 通过 I2C 可针对每个降压转换器读回电源正常状态，发出过流警告
  • 通过 I2C 读回芯片温度警告
  • 具有支持标准模式 (100kHz) 和快速模式 (400kHz) 的 I2C 兼容接口
  • 反馈基准电压为 0.6V ±1%
  • 600kHz 固定频率
  • 针对每次降压的专用使能引脚和软启动引脚
  • 热过载保护

2 应用

  • 数字电视 (DTV) 液晶显示屏 (LCD) 面板
  • 机顶盒
  • 家庭网关和接入点网络
  • 监控

3 说明

TPS65263 整合了三路同步降压转换器，支持 4.5V 至 18V 宽范围输入电压，该电压范围包括大部分中间总线关闭电压为 5、9、12 或 15V 的电源总线或电池。这款转换器具有恒定频率峰值电流模式，专用于简化应用，同时方便设计人员根据目标应用来优化系统。该器件工作频率为 600kHz，buck1 与 buck2 和 buck3 之间 180° 异相（buck2 和 buck3 同相运行）。

每个降压转换器的初始启动电压都可通过外部反馈电阻设定。可使用 I2C 受控 7 位 VID 对每个降压转换器的输出电压进行动态调整，范围为 0.68V 至 1.95V，步长为 10mV。可通过 I2C 总线 3 位控制对 VID 电压转换率进行编程，以优化 VID 电压转换期间的过冲/下冲。

TPS65263 中的每个降压转换器都可通过 I2C 加以控制，从而执行以下操作：启用/禁用输出电压、设置脉冲跳跃模式 (PSM) 或轻负载条件下的强制持续电流模式 (FCC) 以及读取电源正常状态、过流警告和温度警告。

TPS65263 具有过压保护、过流保护、短路保护和过热保护功能。

封装信息(1)
器件型号 封装 封装尺寸（标称值）
TPS65263 RHB（VQFN，32） 5.00mm × 5.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
GUID-AB676A76-3BB7-438A-B110-256F35CAB6A2-low.gif典型应用
GUID-C1E6D7DF-364C-4F83-9B60-A5F3971876F5-low.png
VIN = 12V；VOUT = 3.3V
效率与输出负载之间的关系

4 Revision History

Changes from Revision B (May 2023) to Revision C (May 2023)

  • Changed the value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator and Bootstrap .Go

Changes from Revision A (September 2014) to Revision B (May 2023)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • Changed the description of V7V pin in Table 6-1.Go
  • Renamed Handling Ratings to ESD Ratings Go
  • Moved the storage temperature row in the ESD Ratings table to the Absolute Maximum Ratings tableGo
  • Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator and Bootstrap .Go
  • Changed all instances of legacy terminology to controller and target where I2C is mentioned.Go
  • Changed the recommended value of C9 in the typical application schematicGo

Changes from Revision * (June 2014) to Revision A (September 2014)

  • 将器件状态从“产品预发布”更改为“量产数据”Go

5 Device Comparison Table

PART NUMBER DESCRIPTION COMMENTS
TPS65261/-1 4.5 to 18 V, triple bucks with input voltage power failure indicator Triple bucks 3-A/2-A/2-A output current, features an open drain RESET signal to monitor input power failure, automatic power sequencing
TPS65262/-1 4.5 to 18 V, triple bucks with dual adjustable LDOs Triple bucks 3-A/1-A/1-A output current, automatic power sequencing. dual LDOs: TPS65262, 200 mA/100 mA; TPS65262-1, 350 mA/150 mA
TPS65287 4.5 to 18 V, triple bucks with power switch and push button control Triple bucks 3-A/2-A/2-A output current, up to 2.1-A USB power with over current setting by external resistor, push button control for intelligent system power-on/power-off operation
TPS65288 4.5 to 18 V, triple bucks with dual power switches Triple bucks 3-A/2-A/2-A output current, 2 USB power switches current limiting at typical 1.2 A (0.8, 1.0, 1.4, 1.6, 1.8, 2.0, 2.2 A available with manufacture trim options)

6 Pin Configuration and Functions

GUID-68AACD1B-B567-499B-88C9-18A19429D975-low.gif
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.)
Figure 6-1 RHB Package32 PinTop View
Table 6-1 Pin Functions
PIN DESCRIPTION
NAME NO.
EN3 1 Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck3 with a resistor divider.
SDA 2 I2C interface data pin
SCL 3 I2C interface clock pin
AGND 4 Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
VOUT2 5 Buck2 output voltage sense pin.
FB2 6 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
COMP2 7 Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode.
SS2 8 Soft-start and tracking input for buck2. An internal 5uA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
BST2 9 Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from BST2 pin to LX2 pin.
LX2 10 Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a diode voltage below the ground up to PVIN2 voltage.
PGND2 11 Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of PVIN2 input ceramic capacitor.
PVIN2 12 Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
PVIN3 13 Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
PGND3 14 Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of PVIN3 input ceramic capacitor.
LX3 15 Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a diode voltage below the ground up to PVIN3 voltage.
BST3 16 Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47 nF) from BST3 pin to LX3 pin.
SS3 17 Soft-start and tracking input for buck3. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
COMP3 18 Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the control loop of buck3 with peak current PWM mode.
FB3 19 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider.
VOUT3 20 Buck3 output voltage sense pin.
VOUT1 21 Buck1 output voltage sense pin.
FB1 22 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider.
COMP1 23 Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 with peak current PWM mode.
SS1 24 Soft-start and tracking input for buck1. An internal 5-µA pullup current source is connected to this pin. The soft-start time can be programmed by connecting a capacitor between this pin and ground.
BST1 25 Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47 nF) from BST1 pin to LX1 pin.
LX1 26 Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a diode voltage below the ground up to PVIN1 voltage.
PGND1 27 Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (–) terminal of PVIN1 input ceramic capacitor.
PVIN1 28 Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF).
VIN 29 Buck controller power supply.
V7V 30 Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground.
EN1 31 Enable for buck1. Float to enable. Can use this pin to adjust the input UVLO of buck1 with a resistor divider.
EN2 32 Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider.
PAD — There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1)
MINMAXUNIT
VoltagePVIN1, PVIN2, PVIN3,VIN–0.320V
LX1, LX2, LX3 (maximum withstand voltage transient <20 ns)–1.020
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively–0.37
EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA–0.37
FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3–0.33.6
AGND, PGND1, PGND2, PGND3–0.30.3
TJOperating junction temperature–40125°C
Tstg Storage temperature range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

MINMAXUNIT
V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)–20002000V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)–500500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VoltagePVIN1, PVIN2, PVIN3,VIN4.518V
LX1, LX2, LX3 (Maximum withstand voltage transient <20 ns)–0.818
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively–0.16.8
EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA–0.16.3
FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3–0.13
TAOperating ambient temperature–4085°C
TJOperating junction temperature–40125°C

7.4 Thermal Information

THERMAL METRIC(1)TPS65263UNIT
RHB (32 PINS)
RθJAJunction-to-ambient thermal resistance33.3°C/W
RθJC(top)Junction-to-case (top) thermal resistance25.7
RθJBJunction-to-board thermal resistance7.4
ψJTJunction-to-top characterization parameter0.3
ψJBJunction-to-board characterization parameter7.3
RθJC(bot)Junction-to-case (bottom) thermal resistance2.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VOLTAGE
VINInput voltage range4.518V
UVLOVIN undervoltage lockoutVIN rising44.254.5V
VIN falling3.53.754V
Hysteresis500mV
IDDSDNShutdown supply currentEN1 = EN2 = EN3 = 0 V8µA
IDDQ_NSWInput quiescent current without buck1/2/3 switchingEN1 = EN2 = EN3 = 5 V,
FB1 = FB2 = FB3 = 0.8 V		740µA
IDDQ_NSW1EN1 = 5 V, EN2 = EN3 = 0 V,
FB1 = 0.8 V		360µA
IDDQ_NSW2EN2 = 5 V, EN1 = EN3 = 0 V,
FB2 = 0.8 V		380µA
IDDQ_NSW3EN3 = 5 V, EN1 = EN2 = 0 V,
FB3 = 0.8 V		380µA
V7VV7V LDO output voltageV7V load current = 0 A66.36.6V
IOCP_V7VV7V LDO current limit185mA
FEEDBACK VOLTAGE REFERENCE
VFBFeedback voltageVCOMP = 1.2 V, TJ = 25°C0.5950.60.605V
VCOMP = 1.2 V, TJ = –40°C to 125°C0.5940.60.606V
VLINEREG_BUCKLine regulation-DC(1)IOUT1 = 1.5 A, IOUT2 = 1 A, IOUT3 = 1 A,
5 V < PVINx < 18 V		0.002%/V
VLOADREG_BUCKLoad regulation-DC(1)IOUTx = (10-100%) × IOUTx_max0.02%/A
BUCK1, BUCK2, BUCK3
VENXHEN1/2/3 high level input voltage1.21.26V
VENXLEN1/2/3 low level input voltage1.11.15V
IENX1EN1/2/3 pullup currentENx = 1 V3.8µA
IENX2EN1/2/3 pullup currentENx = 1.5 V6.8µA
IENhysHysteresis current3µA
ISSXSoft start charging current4.356µA
TON_MINMinimum on time80100ns
Gm_EAError amplifier trans-conductance–2 µA < ICOMPX < 2 µA300µS
Gm_PS1/2/3COMP1/2/3 voltage to inductor current Gm(1)ILX = 0.5 A7.4A/V
ILIMIT1Buck1 peak inductor current limit4.55.56.5A
ILIMITSOURCE1Buck1 low side source current limit4.4A
ILIMITSINK1Buck1 low side sink current limit1.3
ILIMIT2/3buck2/3 peak inductor current limit2.63.34A
ILIMITSOURCE2/3Buck2/3 low side source current limit2.5
ILIMITSINK2/3Buck2/3 low side sink current limit1A
Rdson_HS1Buck1 high-side switch resistanceVIN = 12 V105mΩ
Rdson_LS1Buck1 low-side switch resistanceVIN = 12 V65mΩ
Rdson_HS2Buck2 high-side switch resistanceVIN = 12 V140mΩ
Rdson_LS2Buck2 low-side switch resistanceVIN = 12 V90mΩ
Rdson_HS3Buck3 high-side switch resistanceVIN = 12 V140mΩ
Rdson_LS3Buck3 low-side switch resistanceVIN = 12 V90mΩ
HICCUP TIMING
THiccup_waitOver current wait time(1)0.5ms
THiccup_reHiccup time before restart(1)14ms
OSCILLATOR
FSWSwitching frequency550600650kHz
THERMAL PROTECTION
TTRIP_OTPThermal protection trip point(1)Temperature rising160°C
THYST_OTPThermal protection Hysteresis(1)Hysteresis20°C
I2C INTERFACE
AddrAddress(2)0x60H
VIH SDA,SCLInput high voltage2V
VIL SDA,SCLInput low voltage0.4V
IIInput currentSDA, SCL, VI = 0.4 to 4.5 V–1010µA
VOL SDASDA output low voltageSDA open drain, IOL = 4 mA0.4V
ƒ(SCL)Maximum SCL clock frequency(2)400kHz
tBUFBus free time between a STOP and START condition(2)1.3µs
tHD_STAHold time (repeated) START condition(2)0.6µs
tSU_STOSetup time for STOP condition(2)0.6µs
tLOWLOW Period of the SCL Clock(2)1.3µs
tHIGHHIGH period of the SCL clock(2)0.6µs
tSU_STASetup time for a repeated START condition(2)0.6µs
tSU_DATData setup time(2)0.1µs
tHD_DATData hold time(2)00.9µs
tRCLRise time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRCL1Rise time of SCL signal after a repeated START condition and after an acknowledge BIT(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFCLFall time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRDARise time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFDAFall time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
CBCapacitance of bus line(SCL and SDA)(2)400pF
(1) Lab validation result.
(2) Not production tested.

 
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