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  • ADS8860 16 位、1MSPS、串行接口、微功耗、微型、单端输入、SAR 模数转换器

    • ZHCSBG2B May   2013  – February 2019 ADS8860

      PRODUCTION DATA.  

  • CONTENTS
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  • ADS8860 16 位、1MSPS、串行接口、微功耗、微型、单端输入、SAR 模数转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      ADC 电源无需独立的 LDO
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 3-Wire Operation
    7. 7.7 Timing Requirements: 4-Wire Operation
    8. 7.8 Timing Requirements: Daisy-Chain
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Reference
      3. 9.3.3 Clock
      4. 9.3.4 ADC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode
        1. 9.4.1.1 3-Wire CS Mode Without a Busy Indicator
        2. 9.4.1.2 3-Wire CS Mode With a Busy Indicator
        3. 9.4.1.3 4-Wire CS Mode Without a Busy Indicator
        4. 9.4.1.4 4-Wire CS Mode With a Busy Indicator
      2. 9.4.2 Daisy-Chain Mode
        1. 9.4.2.1 Daisy-Chain Mode Without a Busy Indicator
        2. 9.4.2.2 Daisy-Chain Mode With a Busy Indicator
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 Charge-Kickback Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for a 1-µs, Full-Scale Step Response
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Power Saving
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14机械、封装和可订购信息
  15. 重要声明
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DATA SHEET

ADS8860 16 位、1MSPS、串行接口、微功耗、微型、单端输入、SAR 模数转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 采样率：1MHz
  • 无延迟输出
  • 单极单端输入电压范围：
    0V 至 +VREF
  • SPI™- 兼容串行接口，此接口具有
    菊链式选项
  • 出色的交流和直流性能：
    • SNR：93dB，THD：–108dB
    • INL：±1.0LSB（典型值），±2.0 LSB（最大值）
    • DNL：±1.0LSB（最大值）、16 位 NMC
  • 宽工作电压范围：
    • AVDD：2.7V 至 3.6V
    • DVDD：1.65V 至 3.6V
      （不受 AVDD 影响）
    • REF：2.5V 至 5V（不受 AVDD 影响）
    • 工作温度：-40°C 至 +85°C
  • 低功率耗散：
    • 1MSPS 时为 5.5mW
    • 100kSPS 时为 0.55mW
    • 10kSPS 时为 55µW
  • 关断电流 (AVDD)：50nA
  • 满标度步进趋稳至 16 位：290ns
  • 封装：VSSOP-10 和 VSON-10

2 应用

  • 自动测试设备 (ATE)
  • 仪器和流程控制
  • 精密医疗设备
  • 低功耗电池供电的仪器

3 说明

ADS8860 是一款 16 位、1MSPS 单端输入模数转换器 (ADC)。此器件以 2.5V 至 5V 的外部基准运行，从而在无需额外的信号调节情况下提供宽信号范围。此基准电压设置独立于，并且可超过，模拟电源电压 (AVDD)。

该器件提供一个兼容的 SPI 串口。该串口也支持菊花链操作以实现多个器件级联。一个可选的繁忙指示器位可轻松实现与数字主机的同步。

此器件支持 -0.1V 至 VREF + 0.1V 范围的单极单端模拟输入。

器件运行针对极低功耗运行进行了优化。功耗直接与速度成比例。此特性使得 ADS8860 非常适合较低速度的 应用。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADS8860 VSSOP (10) 3.00mm × 3.00mm
VSON (10) 3.00mm × 3.00mm
  1. 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

Device Images

ADC 电源无需独立的 LDO

ADS8860 fbd_8860.gif

4 修订历史记录

Changes from A Revision (December 2013) to B Revision

  • Added 添加了器件信息 表、ESD 额定值 表、建议运行条件 表、参数测量信息 部分、特性 说明部分、器件功能模式 部分、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go
  • Changed 通篇将模拟输入从伪差分更改为单端Go
  • Changed 在特性 部分中将 DVDD 值从 2.7V 至 3.6V 更改为 1.65V 至 3.6VGo
  • Changed 通篇将 MSOP 更改为 VSSOP Go
  • Changed title of Device Comparison Table from Family InformationGo
  • Changed footnotes of Family Information tableGo
  • Changed LSB footnote in Electrical Characteristics table to include how to convert LSB to ppm Go
  • Added more information about validity of data on SCLK edges in all interface modesGo
  • Changed diagrams and text for better explanation of the daisy-chain feature in the Daisy-Chain Mode sectionGo
  • Changed Equation 1 and Equation 2Go
  • Changed Charge-Kickback Filter section title and functionality description Go

Changes from * Revision (May 2013) to A Revision

  • Changed 更改了交流和直流性能 特性 项目中的子项目Go
  • Changed 更改了满标度步进趋稳 特性 项目Go
  • Deleted 删除了最后两个 应用 项目Go
  • Changed 说明 部分Go
  • Changed 首页图Go
  • Added Family Information, Absolute Maximum Ratings, and Thermal Information tablesGo
  • Added Pin Configurations sectionGo
  • Added Electrical Characteristics tableGo
  • Added Timing Characteristics sectionGo
  • Added Typical Characteristics sectionGo

5 Device Comparison Table

THROUGHPUT 18-BIT, TRUE-DIFFERENTIAL 16-BIT, SINGLE-ENDED 16-BIT, TRUE-DIFFERENTIAL
100 kSPS ADS8887 ADS8866 ADS8867
250 kSPS — ADS8339(1) —
400 kSPS ADS8885 ADS8864 ADS8865
500 kSPS — ADS8319(1) ADS8318(1)(2)
680 kSPS ADS8883 ADS8862 ADS8863
1 MSPS ADS8881 ADS8860 ADS8861
(1) Pin-to-pin compatible device with AVDD = 5 V.
(2) Supports standard for fully-differential input.

6 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
DRC Package
10-Pin VSON
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AINN 4 Analog input Inverting analog signal input
AINP 3 Analog input Noninverting analog signal input
AVDD 2 Analog Analog power supply. This pin must be decoupled to GND with a 1-µF capacitor.
CONVST 6 Digital input Convert input. This pin also functions as the CS input in 3-wire interface mode; see the Description and Timing Requirements sections for more details.
DIN 9 Digital input Serial data input. The DIN level at the start of a conversion selects the mode of operation (such as CS or daisy-chain mode). This pin also serves as the CS input in 4-wire interface mode; see the Description and Timing Requirements sections for more details.
DOUT 7 Digital output Serial data output
DVDD 10 Power supply Digital interface power supply. This pin must be decoupled to GND with a 1-µF capacitor.
GND 5 Analog, digital Device ground. Note that this pin is a common ground pin for both the analog power supply (AVDD) and digital I/O supply (DVDD). The reference return line is also internally connected to this pin.
REF 1 Analog Positive reference input. This pin must be decoupled with a 10-µF or larger capacitor.
SCLK 8 Digital input Clock input for serial interface. Data output (on DOUT) are synchronized with this clock.
Thermal pad — Exposed thermal pad (only for the DRC package option). Texas Instruments recommends connecting the thermal pad to the printed circuit board (PCB) ground.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AINP to GND or AINN to GND –0.3 REF + 0.3 V
AVDD to GND or DVDD to GND –0.3 4 V
REF to GND –0.3 5.7 V
Digital input voltage to GND –0.3 DVDD + 0.3 V
Digital output to GND –0.3 DVDD + 0.3 V
Input current to any pin except supply pins –10 10 mA
Operating temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog power supply 3 V
DVDD Digital power supply 3 V
VREF Reference voltage 5 V

7.4 Thermal Information

THERMAL METRIC(1) ADS8860 UNIT
DGS (VSSOP) DRC (VSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 151.9 111.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.4 46.4 °C/W
RθJB Junction-to-board thermal resistance 72.2 45.9 °C/W
ψJT Junction-to-top characterization parameter 3.3 3.5 °C/W
ψJB Junction-to-board characterization parameter 70.9 45.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

all minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS over the operating free-air temperature range (unless otherwise noted); typical specifications are at TA = 25°C, AVDD = 3 V, and DVDD = 3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) AINP – AINN 0 VREF V
Operating input range(1) AINP –0.1 VREF + 0.1 V
AINN –0.1 + 0.1
CI Input capacitance AINP and AINN terminal to GND 59 pF
Input leakage current During acquisition for dc input 5 nA
EXTERNAL REFERENCE INPUT
VREF Input range 2.5 5 V
Reference input current During conversion, 1-MHz sample rate, mid-code 300 μA
Reference leakage current 250 nA
CREF Decoupling capacitor at the REF input 10 22 µF
SYSTEM PERFORMANCE
Resolution 16 Bits
NMC No missing codes 16 Bits
DNL Differential linearity –0.99 ±0.6 1 LSB(2)
INL Integral linearity(5) –2 ±0.8 2 LSB(2)
EO Offset error(3) –4 ±1 4 mV
Offset error drift with temperature ±1.5 µV/°C
EG Gain error –0.01 ±0.005 0.01 %FSR
Gain error drift with temperature ±0.15 ppm/°C
CMRR Common-mode rejection ratio With common-mode input signal = 5 VPP at dc 90 100 dB
PSRR Power-supply rejection ratio At mid-code 80 dB
Transition noise 0.5 LSB
SAMPLING DYNAMICS
tconv Conversion time 500 710 ns
tACQ Acquisition time 290 ns
Maximum throughput rate
with or without latency		 1000 kHz
Aperture delay 4 ns
Aperture jitter, RMS 5 ps
Step response Settling to 16-bit accuracy 290 ns
Overvoltage recovery Settling to 16-bit accuracy 290 ns
DYNAMIC CHARACTERISTICS
SINAD Signal-to-noise + distortion(7) At 1 kHz, VREF = 5 V 90.5 92.9 dB
At 10 kHz, VREF = 5 V 92.9
At 100 kHz, VREF = 5 V 88.2
SNR Signal-to-noise ratio(7) At 1 kHz, VREF = 5 V 92 93 dB
At 10 kHz, VREF = 5 V 93
At 100 kHz, VREF = 5 V 88.5
THD Total harmonic distortion(7)(4) At 1 kHz, VREF = 5 V –108 dB
At 10 kHz, VREF = 5 V –108
At , VREF = 5 V –101
SFDR Spurious-free dynamic range(7) At 1 kHz, VREF = 5 V 108 dB
At 10 kHz, VREF = 5 V 108
At 100 kHz, VREF = 5 V 101
BW–3dB –3-dB small-signal bandwidth 30 MHz
POWER-SUPPLY REQUIREMENTS
Power-supply voltage AVDD Analog supply 2.7 3 3.6 V
DVDD Digital supply range for SCLK > 40 MHz 2.7 3 3.6
Digital supply range for SCLK < 40 MHz 1.65 1.8 3.6
Supply current AVDD 1-MHz sample rate, AVDD = 3 V 1.8 2.4 mA
PVA Power dissipation 1-MHz sample rate, AVDD = 3 V 5.5 7.2 mW
100-kHz sample rate, AVDD = 3 V 0.55
10-kHz sample rate, AVDD = 3 V 55 μW
IAPD Device power-down current(6) 50 nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
VIH High-level input voltage 1.65 V < DVDD < 2.3 V 0.8 × DVDD DVDD + 0.3 V
2.3 V < DVDD < 3.6 V 0.7 × DVDD DVDD + 0.3
VIL Low-level input voltage 1.65 V < DVDD < 2.3 V –0.3 0.2 × DVDD V
2.3 V < DVDD < 3.6 V –0.3 0.3 × DVDD
ILK Digital input leakage current ±10 ±100 nA
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
VOH High-level output voltage IO = 500-μA source, CLOAD = 20 pF 0.8 × DVDD DVDD V
VOL Low-level output voltage IO = 500-μA sink, CLOAD = 20 pF 0 0.2 × DVDD V
TEMPERATURE RANGE
TA Operating free-air temperature –40 85 °C
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit. 1 LSB at 16-bits is approximately 15.26 ppm.
(3) Measured relative to actual measured reference.
(4) Calculated on the first nine harmonics of the input frequency.
(5) This parameter is the endpoint INL, not best-fit.
(6) The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.
(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.

7.6 Timing Requirements: 3-Wire Operation

all specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
tACQ Acquisition time 290 ns
tconv Conversion time 500 710 ns
1/fsample Time between conversions 1000 ns
twh-CNV Pulse duration: CONVST high 10 ns
fSCLK SCLK frequency 66.6 MHz
tSCLK SCLK period 15 ns
tclkl SCLK low time 0.45 0.55 tSCLK
tclkh SCLK high time 0.45 0.55 tSCLK
th-CK-DO SCLK falling edge to current data invalid 3 ns
td-CK-DO SCLK falling edge to next data valid delay 13.4 ns
td-CNV-DO Enable time: CONVST low to MSB valid 12.3 ns
td-CNV-DOhz Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode) 13.2 ns
tquiet Quiet time 20 ns

 
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