ZHCSAJ4D November 2012 – September 2019 ADS1018
PRODUCTION DATA.
The 16-bit Conversion register contains the result of the last conversion in binary twos complement format. Following power up, the Conversion register is cleared to 0, and remains 0 until the first conversion is complete. The register format is shown in Figure 16.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| D3 | D2 | D1 | D0 | Reserved | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:4 | D[11:0] | R | 000h | 12-bit conversion result |
| 3:0 | Reserved | R | 0h | Always reads back 0h |