SN65HVD82 稳健耐用型 RS-485 收发器

8.3.1 Receiver Failsafe

The differential receiver is failsafe to invalid bus states caused by:

• open bus conditions such as a disconnected connector
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving

Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential.  In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input V_ID is more positive than 200 mV, and must output a Low when the V_ID is more negative than –200 mV.  The receiver parameters which determine the failsafe performance are V_IT+ and V_IT– and V_HYS.  As seen in the Electrical Characteristics table, differential signals more negative than
–200 mV will always cause a Low receiver output.  Similarly, differential signals more positive than 200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it will still be above the V_IT+ threshold, and the receiver output will be High.  Only when the differential input is more negative than V_IT– will the receiver output transition to a Low state.  So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value V_HYS (the separation between V_IT+ and V_IT– ) as well as the value of V_IT+.

Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring no spurious bits.

8.3.2 Low-Power Standby Mode

When both the driver and receiver are disabled (DE transitions to a low state and RE transitions to a high state) the device enters standby mode. If the enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode. This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.

Table 1. Driver Function Table

Table 2. Receiver Function Table

9.1.1 Device Configuration

The SN65HVD82 is a half-duplex, 250-kbps, RS-485 transceiver operating from a single 5-V supply. The driver and receiver enable pins allow for the configuration of different operating modes.

Figure 15. SN65HVD82 Transceiver Configurations

Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be turned on and off individually. While this configuration requires two control lines, it allows for selective listening into the bus traffic, whether the driver is transmitting data or not.

Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal. Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device operates as a receiver.

Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only. In this configuration a node not only receives the data from the bus, but also the data it sends and thus can verify that the correct data have been transmitted.

9.1.2 Bus – Design

An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, R_T, whose value matches the characteristic impedance, Z₀, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length.

Figure 16. Typical RS-485 Network with SN65HVD82 Transceivers

Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z₀ = 100 Ω, and proper RS-485 cable with Z₀ = 120 Ω.

Line measurements have shown that making R_T by up to 10% larger than Z₀ improves signal quality. Typical cable sizes are AWG 22 and AWG 24.

The theoretical maximum bus length is assumed with 4000 ft or 1200 m, and represents the length of an AWG 24 cable whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half or 6 dB.

The theoretical maximum number of bus nodes is determined by the ratio of the RS-485 specified maximum of 32 unit loads (UL) and the actual unit load of the applied transceiver. For example, the SN65HVD82 is a 1/8 UL transceiver. Dividing 32 UL by 1/8 UL yields 256 transceivers that can be connected to one bus.

9.1.3 Cable-Length Versus Data Rate

There is an inverse relationship between data rate and cable length. That is, the higher the data rate the shorter the cable and conversely the lower the data rate the longer the cable. While most RS-485 systems utilize data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of up to 250 kbps even at distances of 4000 feet and above. This is possible by allowing for small signal jitter of up to 5 or 10%.

Figure 17. Cable Length vs Data Rate Characteristic

9.1.4 Stub – Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. The reason for this is that a stub presents a non-terminated piece of bus line which can introduce reflections if too long. As a rule of thumb the electrical length or round-trip delay of a stub should be less than one tenth of the driver’s rise time, thus leading to a maximum physical stub length of: L_Stub ≤ 0.1 × t_r × v × c, with t_r as the driver’s 10/90 rise time, c as the speed of light (3 × 10⁸ m/s or 9.8 × 10⁸ ft/s), and v as the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c.

Thus, for the SN65HVD82 with a minimum rise time of 400 ns the maximum cable stub length yields L_Stub ≤ 0.1 × 400 × 10^-9 × 3 10⁸ × 0.78 = 9.4 m or 30.6 ft.

Figure 18. Stub Length

9.1.5 3-V to 5-V Interface

Interfacing the SN65HVD82 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept 3-V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must be level-shifted via a Schottky diode and a 10-kV resistor to connect to the controller input. When R is high, the diode is reverse biased and the controller supply potential lies at the controller input. When R is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the controller input.

Figure 19. 3 V – 5 V Interface

9.1.6 Noise Immunity

The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, V_ID, is greater than +200 mV, the receiver output turns high, for V_ID ≤ 200 mV the receiver outputs low. Bus voltages in between these levels can cause the receiver output to go high, or low, or even toggle between logic states. Small bus voltages however occur every time during the bus access hand-off from one driver to the next as the low-impedance termination resistors reduce the bus voltage to zero. To prevent receiver output toggling during bus idling, and thus increasing noise immunity, external bias resistors must be applied to create a bus voltage that is greater than the input sensitivity plus any expected differential noise.

Figure 20. SN65HVD82 Noise Immunity

The SN65HVD82 transceiver circumvents idle-bus and differential noise issues by providing a positive input threshold of –20 mV and a typical hysteresis of 60 mV. In the case of an idle-bus condition therefore, a differential noise voltage of up to 160 mV_PP can be present without causing the receiver output to change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias resistors and allows for long haul data transmissions in noisy environment.

9.1.7 Transient Protection

The bus terminals of the SN65HVD82 transceiver family possess on-chip ESD protection against ±15 kV human body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC-model produce significantly higher discharge currents than the HBM-model.

Figure 21. HBM and IEC-ESD Models and Currents in Comparison

EFTs are usually caused by relay contact bounce or the interruption of inductive loads, while surge transients often results from lightning strikes (direct strike or induced voltages and currents due to an indirect strike), or the switching of power systems including load changes and short circuits switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems.

Figure 22 compares the pulse-power of the EFT and surge transients with the power caused by an IEC-ESD transient. As can be seen the tiny blue blip in the bottom left corner of the left diagram represents the power of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike and certainly against the 500-V surge transient. This type of transient power is well representative for factory environments in industrial and process automation. The right diagram compares the enormous power of a 6-kV surge transient, which more likely occurs in e-metering applications of power generating and power grid systems, with the aforementioned 500-V surge transient. Note that the unit of the pulse-power changes from kW to MW, thus making the power of the 500-V surge transient almost dropping off the scale.

Figure 22. Power Comparison of ESD, EFT, and Surge Transients

In the case of surge transients, their long pulse duration and slowly decreasing pulse power signifies high energy content.

The electrical energy of a transient that is dumped onto the transceiver’s internal protections cells is converted into thermal energy, or heat that literally fries the protection cells, thus destroying the transceiver. Figure 23 showcases the large differences in transient energies for single ESD, EFT, and surge transients as well as for an EFT pulse train, commonly applied during compliance testing.

Figure 23. Comparison of Transient Energies

Figure 24 suggests two circuit designs providing protection against surge transients. Table 3 presents the associated bill of material.

Figure 24. Transient Protection Against ESD, EFT, and Surge Transients

Both circuits are designed for 10-kV ESD and 4-kV EFT transient protection. The left however provides surge protection of ≥ 500-V transients only, while the right protection circuits can withstand 5-kV surge transients.

9.2.1 Design Requirements

The following list outlines sample design requirements for the typical application example found in Figure 25

• RS-485-compliant bus interface (needs differential signal amplitude of at least 1.5 V under fully-loaded conditions – essentially, maximum number of nodes connected and with dual 120-Ω termination).
• Galvanic isolation of both signal and power supply lines.
• Able to withstand ESD transients up to 10 kV (per IEC 61000-4-2) and EFTs up to 4 kV (per IEC 61000-4-4).
• Full control of data flow on bus in order to prevent contention (for half-duplex communication).

9.2.2 Detailed Design Procedure

9.2.3 Application Curve

Figure 26. SN65GVD82 D Input (Top), Differential Output (Middle), and R Output (Bottom), 250 kbps Operation, PRBS Data Pattern

11.1.1 Design and Layout Considerations For Transient Protection

On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of external transient protection devices.

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design.

In order for your PCB design to be successful start with the design of the protection circuit in mind.

1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your board.
2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the Vcc-pins of transceiver, UART, controller ICs on the board.
5. Use at least two vias for Vcc and ground connections of bypass capacitors and protection devices to minimize effective via-inductance.
6. Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in theses lines during transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to some 200 mA.

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 使用 WEBENCH® 工具定制设计方案

单击此处，使用 SN65HVD82 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 在开始阶段键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

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• 打印设计方案的 PDF 报告并与同事共享

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