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  • AMC1100 全差动隔离放大器

    • ZHCS847B April   2012  – December 2019 AMC1100

      PRODUCTION DATA.  

  • CONTENTS
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  • AMC1100 全差动隔离放大器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 The AMC1100 in Frequency Inverters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 The AMC1100 in Energy Metering
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 隔离相关术语
          1. 11.1.1.1.1 绝缘：
          2. 11.1.1.1.2 污染等级：
          3. 11.1.1.1.3 安装类别：
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

AMC1100 全差动隔离放大器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 针对分流电阻器进行优化的 ±250mV 输入电压范围
  • 超低的非线性度：5V 时最大为 0.075%
  • 低失调电压误差：1.5mV（最大值）
  • 低噪声：3.1mVRMS（典型值）
  • 低高侧电源电流：
    5V 时的最大值为 8mA
  • 输入带宽：60kHz（最小值）
  • 固定增益：8（精度为 0.5%）
  • 高共模抑制比：108dB
  • 低侧运行：3.3V
  • 安全相关认证：
    • 符合 DIN VDE V 0884-11: 2017-01 标准的
      4250VPK 基础型隔离
    • 符合 UL1577 标准且长达 1 分钟的 3005VRMS 隔离
    • 符合 CAN/CSA No. 5A 组件验收服务通知和 DIN EN 61010-1 标准
    • 工作电压：1200VPEAK
    • 瞬态抗扰度：2.5kV/µs（最小值）
  • 可在扩展工业温度范围内正常工作

2 应用

    基于分流电阻器的电流感应，可用于：

    • 电表
    • 串式逆变器
    • 功率测量 或

3 说明

AMC1100 是一款高精度隔离放大器，通过具有高磁场抗扰度的二氧化硅 (SiO2) 隔栅隔离输出与输入电路。根据 DIN VDE V 0884-11: 2017-01 和 UL1577 标准，该隔离栅经认证可提供高达 4250VPEAK 的电隔离。当与隔离电源配合使用时，此器件可防止高共模电压线路上的噪声电流流入本地接地并干扰或损坏敏感电路。

AMC1100 输入进行了优化，可以直接连接到分流电阻器或其他低电压电平信号源。凭借该器件的出色性能，可在电能计量应用中实现精确的电流和电压 测量。输出信号共模电压被自动调节至 3V 或者 5V 低侧电源。

AMC1100 在扩展工业温度范围（–40°C 至 +105°C）内完全额定运行，并且采用 SMD 型宽体小外形集成电路 (SOIC)-8 (DWV) 封装以及 gullwing-8 (DUB) 封装。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
AMC1100 SOP (8) 9.50mm × 6.57mm
SOIC (8) 5.85mm × 7.50mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化原理图

AMC1100 fbd_bas562.gif

4 修订历史记录

Changes from A Revision (December 2014) to B Revision

  • Changed 根据 ISO 标准更改了安全相关认证 特性 项目中的认证详细信息Go
  • Deleted 删除了 特性 项目符号中的寿命典型值Go
  • Changed 更改了“应用”部分以包含终端设备链接Go
  • Changed 将 IEC60747-5-2 更改为 DIN VDE V 0884-11: 2017-01（位于说明 部分）Go
  • Changed 更改了第 1 页的图并添加了标题Go
  • Added Power Ratings tableGo
  • Changed Insulation Specifications table per ISO standardGo
  • Added DWV-package related details in Insulation Specifications tableGo
  • Changed Safety-Related Certification table per ISO standardGo
  • Changed Safety Limiting Values table per ISO standardGo
  • Deleted VDD1 and VDD2 from Electrical Characteristics table (repeated in Recommended Operating Conditions table) Go
  • Added Insulation Characteristics Curves sectionGo
  • Changed Zener Diode Based High-Side Supply figureGo

Changes from * Revision (April 2012) to A Revision

  • 更改了格式，以符合最新的数据表标准Go
  • 添加了 ESD 额定值 表和特性 说明、器件功能模式、应用和实施、电源相关建议、布局、器件和文档支持 以及机械、封装和可订购信息 部分Go
  • 在文档中添加了 DWV 封装Go
  • Deleted Package and Ordering Information sectionGo

5 Pin Configuration and Functions

DUB and DWV Packages
SOP-8 and SOIC-8
(Top View)
AMC1100 po_dub_so-8_bas542.gif

Pin Descriptions

PIN FUNCTION DESCRIPTION
NAME NO.
GND1 4 Power High-side analog ground
GND2 5 Power Low-side analog ground
VDD1 1 Power High-side power supply
VDD2 8 Power Low-side power supply
VINN 3 Analog input Inverting analog input
VINP 2 Analog input Noninverting analog input
VOUTN 6 Analog output Inverting analog output
VOUTP 7 Analog output Noninverting analog output

6 Specifications

6.1 Absolute Maximum Ratings

see(1)
MIN MAX UNIT
Supply voltage, VDD1 to GND1 or VDD2 to GND2 –0.5 6 V
Analog input voltage at VINP, VINN GND1 – 0.5 VDD1 + 0.5 V
Input current to any pin except supply pins ±10 mA
Maximum junction temperature, TJ Max 150 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TA Operating ambient temperature range –40 105 °C
VDD1 High-side power supply 4.5 5.0 5.5 V
VDD2 Low-side power supply 2.7 5.0 5.5 V

6.4 Thermal Information

THERMAL METRIC(1) AMC1100 UNIT
DUB (SOP) DWV (SOIC)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 75.1 102.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.6 49.8 °C/W
RθJB Junction-to-board thermal resistance 39.8 56.6 °C/W
ψJT Junction-to-top characterization parameter 27.2 16.0 °C/W
ψJB Junction-to-board characterization parameter 39.4 55.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation
(both sides)		 VDD1 = VDD2 = 5.5 V 82.5 mW
VDD1 = 5.5 V, VDD2 = 3.6 V 65.6
PD1 Maximum power dissipation
(high-side supply)		 VDD1 = 5.5 V 44.0 mW
PD2 Maximum power dissipation
(low-side supply)		 VDD2 = 5.5 V 38.5 mW
VDD2 = 3.6 V 21.6

6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air, DUB package ≥ 7 mm
Shortest pin-to-pin distance through air, DWV package ≥ 8.5
CPG External creepage(1) Shortest pin-to-pin distance across the package surface, DUB package ≥ 7 mm
Shortest pin-to-pin distance across the package surface, DWV package ≥ 8.5
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 0.014 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112, DUB package ≥ 400 V
DIN EN 60112 (VDE 0303-11); IEC 60112, DWV package ≥ 600
Material group According to IEC 60664-1, DUB package II
According to IEC 60664-1, DWV package I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-III
DIN VDE V 0884-11: 2017-01(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar) 1200 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 849 VRMS
At dc voltage 1200 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 4250 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 5100
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 6000 VPK (qualification)		 4615 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1440 VPK, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1560 VPK, tm = 10 s		 ≤ 5
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1800 VPK, tm = 1 s		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V at TA < 85°C > 1012 Ω
VIO = 500 V at 85°C < TA < 105°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 3005 VRMS or 4250 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 3606 VRMS, t = 1 s (100% production test) 3005 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

6.7 Safety-Related Certifications

VDE UL CSA
Certified according to
DIN VDE V 0884-11: 2017-01 and
DIN EN 61010-1 (VDE 0411-1) : 2011-07 		Recognized under 1577 component recognition program Recognized under CSA component acceptance NO 5 program, IEC 60950-1, and IEC 61010-1
Basic insulation Single protection Basic insulation
Certificate number: 40047657 File number: E181974 Certificate number: 2643952

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output,
or supply current		 DUB package, RθJA = 75.1°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 1 		302 mA
DWV package, RθJA =102.8°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 1 		221
PS Safety input, output,
or total power(1) 		DUB package, RθJA = 75.1°C/W, TJ = 150°C, TA = 25°C,
see Figure 2 		1664 mW
DWV package, RθJA = 102.8°C/W, TJ = 150°C,
TA = 25°C, see Figure 2 		1216 mW
TS Maximum safety temperature 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side supply voltage and VDD2max is the maximum low-side supply voltage.

6.9 Electrical Characteristics

All minimum and maximum specifications are at TA = –40°C to +105°C and are within the specified voltage range, unless otherwise noted. Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Maximum input voltage before clipping VINP – VINN ±320 mV
Differential input voltage VINP – VINN –250 250 mV
VCM Common-mode operating range –0.16 VDD1 V
VOS Input offset voltage –1.5 ±0.2 1.5 mV
TCVOS Input offset thermal drift –10 ±1.5 10 µV/K
CMRR Common-mode rejection ratio VIN from 0 V to 5 V at 0 Hz 108 dB
VIN from 0 V to 5 V at 50 kHz 95 dB
CIN Input capacitance to GND1 VINP or VINN 3 pF
CIND Differential input capacitance 3.6 pF
RIN Differential input resistance 28 kΩ
Small-signal bandwidth 60 100 kHz
OUTPUT
Nominal gain 8
GERR Gain error Initial, at TA = +25°C –0.5% ±0.05% 0.5%
–1% ±0.05% 1%
TCGERR Gain error thermal drift ±56 ppm/K
Nonlinearity 4.5 V ≤ VDD2 ≤ 5.5 V –0.075% ±0.015% 0.075%
2.7 V ≤ VDD2 ≤ 3.6 V –0.1% ±0.023% 0.1%
Nonlinearity thermal drift 2.4 ppm/K
Output noise VINP = VINN = 0 V 3.1 mVRMS
PSRR Power-supply rejection ratio vs VDD1, 10-kHz ripple 80 dB
vs VDD2, 10-kHz ripple 61 dB
Rise-and-fall time 0.5-V step, 10% to 90% 3.66 6.6 µs
VIN to VOUT signal delay 0.5-V step, 50% to 10%, unfiltered output 1.6 3.3 µs
0.5-V step, 50% to 50%, unfiltered output 3.15 5.6 µs
0.5-V step, 50% to 90%, unfiltered output 5.26 9.9 µs
CMTI Common-mode transient immunity VCM = 1 kV 2.5 3.75 kV/µs
Output common-mode voltage 2.7 V ≤ VDD2 ≤ 3.6 V 1.15 1.29 1.45 V
4.5 V ≤ VDD2 ≤ 5.5 V 2.4 2.55 2.7 V
Short-circuit current 20 mA
ROUT Output resistance 2.5 Ω
POWER SUPPLY
IDD1 High-side supply current 5.4 8 mA
IDD2 Low-side supply current 2.7 V < VDD2 < 3.6 V 3.8 6 mA
4.5 V < VDD2 < 5.5 V 4.4 7 mA
PDD1 High-side power dissipation 27.0 44.0 mW
PDD2 Low-side power dissipation 2.7 V < VDD2 < 3.6 V 11.4 21.6 mW
4.5 V < VDD2 < 5.5 V 22.0 38.5 mW

6.10 Insulation Characteristics Curves

AMC1100 D001_SBAS562.gif
Figure 1. Thermal Derating Curve for Safety-Limiting Current per VDE
AMC1100 D002_SBAS562.gif
Figure 2. Thermal Derating Curve for Safety-Limiting
Power per VDE

6.11 Typical Characteristics

At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
AMC1100 tc_offset-vdd1_bas542.png
Figure 3. Input Offset vs High-Side Supply Voltage
AMC1100 tc_offset-vdd2_45v_bas542.png
Figure 5. Input Offset vs Low-Side Supply Voltage
AMC1100 tc_cmrr-frq_bas542.png
Figure 7. Common-Mode Rejection Ratio vs
Input Frequency
AMC1100 tc_bw-tmp_bas542.png
Figure 9. Input Bandwidth vs Temperature
AMC1100 tc_gain-vdd2_27v_bas542.png
Figure 11. Gain Error vs Low-Side Supply Voltage
AMC1100 tc_gain-tmp_bas542.png
Figure 13. Gain Error vs Temperature
AMC1100 tc_phase-frq_bas542.png
Figure 15. Output Phase vs Input Frequency
AMC1100 tc_vout-vin_27v_bas542.png
Figure 17. Output Voltage vs Input Voltage
AMC1100 tc_nonlinearity-vdd2_27v_bas542.png
Figure 19. Nonlinearity vs Low-Side Supply Voltage
AMC1100 tc_nonlinearity-vin_bas542.png
Figure 21. Nonlinearity vs Input Voltage
AMC1100 tc_noise-frq_bas542.png
Figure 23. Output Noise Density vs Frequency
AMC1100 tc_rise_fall-tmp_bas542.png
Figure 25. Output Rise and Fall Time vs Temperature
AMC1100 tc_delay-tmp_bas542.png
Figure 27. Output Signal Delay Time vs Temperature
AMC1100 tc_vcm-tmp_bas542.png
Figure 29. Output Common-Mode Voltage vs Temperature
AMC1100 tc_ivdd2-vdd2_bas542.png
Figure 31. Low-Side Supply Current vs
Low-Side Supply Voltage
AMC1100 tc_offset-vdd2_27v_bas542.png
Figure 4. Input Offset vs Low-Side Supply Voltage
AMC1100 tc_offset-tmp_bas542.png
Figure 6. Input Offset vs Temperature
AMC1100 tc_iin-vin_bas542.png
Figure 8. Input Current vs Input Voltage
AMC1100 tc_gain-vdd1_bas542.png
Figure 10. Gain Error vs High-Side Supply Voltage
AMC1100 tc_gain-vdd2_45v_bas542.png
Figure 12. Gain Error vs Low-Side Supply Voltage
AMC1100 tc_gain-frq_bas542.png
Figure 14. Normalized Gain vs Input Frequency
AMC1100 tc_vout-vin_bas542.png
Figure 16. Output Voltage vs Input Voltage
AMC1100 tc_nonlinearity-vdd1_bas542.png
Figure 18. Nonlinearity vs High-Side Supply Voltage
AMC1100 tc_nonlinearity-vdd2_45v_bas542.png
Figure 20. Nonlinearity vs Low-Side Supply Voltage
AMC1100 tc_nonlinearity-tmp_bas542.png
Figure 22. Nonlinearity vs Temperature
AMC1100 tc_psrr-frq_bas542.png
Figure 24. Power-Supply Rejection Ratio vs
Ripple Frequency
AMC1100 tc_step_response_bas542.gif
Figure 26. Full-Scale Step Response
AMC1100 tc_vcm-vdd2_bas542.png
Figure 28. Output Common-Mode Voltage vs
Low-Side Supply Voltage
AMC1100 tc_idd-vdd_bas542.png
Figure 30. Supply Current vs Supply Voltage
AMC1100 tc_idd-tmp_bas542.png
Figure 32. Supply Current vs Temperature

7 Detailed Description

7.1 Overview

The AMC1100 consists of a delta-sigma modulator input stage including an internal reference and clock generator. The output of the modulator and clock signal are differentially transmitted over the integrated capacitive isolation barrier that separates the high- and low-voltage domains. The received bitstream and clock signals are synchronized and processed by a third-order analog filter with a nominal gain of 8 on the low-side and presented as a differential output of the device, as shown in the Functional Block Diagram section.

The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity, as described in application report SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity (available for download at www.ti.com).

7.2 Functional Block Diagram

AMC1100 ai_fbd_bas562.gif

7.3 Feature Description

The differential analog input of the AMC1100 is a switched-capacitor circuit based on a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The device compares the differential input signal (VIN = VINP – VINN) against the internal reference of 2.5 V using internal capacitors that are continuously charged and discharged with a typical frequency of 10 MHz. With the S1 switches closed, CIND charges to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then both S2 switches close. CIND discharges to approximately GND1 + 0.8 V during this phase. Figure 33 shows the simplified equivalent input circuitry.

AMC1100 ai_equiv_bas562.gifFigure 33. Equivalent Input Circuit

The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. However, there are two restrictions on the analog input signals, VINP and VINN. If the input voltage exceeds the range GND1 – 0.5 V to VDD1 + 0.5 V, the input current must be limited to 10 mA to protect the implemented input protection diodes from damage. In addition, the device linearity and noise performance are ensured only when the differential analog input voltage remains within ±250 mV.

7.4 Device Functional Modes

The AMC1100 is powered on when the supplies are connected. The device is operated off a 5-V nominal supply on the high-side. The potential of the ground reference GND1 can be floating, which is usually the case in shunt-based current-measurement applications. TI recommends tying one side of the shunt to the GND1 pin of the AMC1100 to maintain the operating common-mode range requirements of the device.

The low-side of the AMC1100 can be powered from a supply source with a nominal voltage of 3.0 V, 3.3 V, or 5.0 V. When operated at 5 V, the common-mode voltage of the output stage is set to 2.55 V nominal; in both other cases, the common-mode voltage is automatically set to 1.29 V.

Although usually applied in shunt-based current-sensing circuits, the AMC1100 can also be used for isolated voltage measurement applications, as shown in a simplified way in Figure 34. In such applications, usually a resistor divider (R1 and R2 in Figure 34) is used to match the relatively small input voltage range of the AMC1100. R2 and the AMC1100 input resistance (RIN) also create a resistance divider that results in additional gain error. With the assumption that R1 and RIN have a considerably higher value than R2, the resulting total gain error can be estimated using Equation 1:

Equation 1. AMC1100 q_gerrtot_bas542.gif

where

  • GERR = device gain error.
AMC1100 ai_voltage_meas_bas542.gifFigure 34. Voltage Measurement Application

 
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