bq76925 用于 3 至 6 节串联锂离子/锂聚合物电池保护和电量监测的主机控制模拟前端 应用

8.3.2.1 Reference Voltage

The bq76925 device outputs a stable reference voltage for use by the Host ADC. A nominal voltage of 1.5 V or 3 V is selected through the REF_SEL bit in the CONFIG_2 register. The reference voltage is very stable across temperature, but the initial voltage may vary by ±4%. The variation from nominal is manifested as a gain error in the ADC conversion result. To correct for this error, offset and gain correction factors are determined at final test and stored in the non-volatile registers VREF_CAL and VREF_CAL_EXT. The Host reads the correction factors and applies them to the nominal reference voltage to arrive at the actual reference voltage as described under Cell Voltage Monitoring. After gain correction, the tolerance of the reference will be within ±0.1%.

8.3.2.1.1 Host ADC Calibration

All analog-to-digital converters have inherent gain and offset errors, which adversely affect measurement accuracy. Some microcontrollers may be characterized by the manufacturer and shipped with ADC gain and offset information stored on-chip. It is also possible for such characterization to be done by the end-user on loose devices prior to PCB assembly or as a part of the assembled PCB test.

For applications where such ADC characterization is not provided or is not practical, the bq76925 device provides a means for in-situ calibration of the Host ADC through setting of the VCOUT_SEL bits in the CELL_CTL register two scaled versions of the reference voltage, 0.5 × V_REF and 0.85 × V_REF, can be selected for output on the VCOUT pin for measurement by the Host ADC. Measuring both scaled voltages enables the Host to do a two-point calibration of the ADC and compensate for the ADC offset and gain in all subsequent ADC measurement results as shown in Figure 10.

Note that the calibration accuracy will be limited by the tolerance of the scaled reference-voltage output so that use of this method may not be effective. For these cases, TI recommends to use a higher-accuracy source for the two-point calibration shown in Figure 10.

Figure 10. Host ADC Calibration Using V_REF

8.3.2.2 Cell Voltage Monitoring

The cell-voltage monitoring circuits include an input level-shifter, multiplexer (MUX), and scaling amplifier. The Host selects one VCn cell input for measurement by setting the VCOUT_SEL and CELL_SEL bits in the CELL_CTL register. The scaling factor is set by the REF_SEL bit in the CONFIG_2 register. The selected cell input is level shifted to VSS reference, scaled by a nominal gain G_VCOUT = 0.3 (REF_SEL = 0) or 0.6 (REF_SEL = 1) and output on the VCOUT pin for measurement by the Host ADC.

Similar to the reference voltage, gain and offset correction factors are determined at final test for each individual cell input and stored in non-volatile registers VCn_CAL (n = 1-6) and VC_CAL_EXT_m (m = 1-2). These factors are read by the Host and applied to the ADC voltage-measurement results in order to obtain the specified accuracy.

The cell voltage offset and gain correction factors are stored as 5-bit signed integers in 2’s complement format. The most significant bits (VCn_OC_4, VCn_GC_4) are stored separately and must be concatenated with the least significant bits (VCn_OFFSET_CORR, VCn_GAIN_CORR).

The reference voltage offset and gain correction factors are stored respectively as a 6-bit and 5-bit signed integer in 2’s complement format. As with the cell voltage correction factors, the most significant bits (VREF_OC_5, VREF_OC_4, VREF_GC_4) are stored separately and must be concatenated with the least significant bits (VREF_OFFSET_CORR, VREF_GAIN_CORR).

The actual cell voltage (VCn) is calculated from the measured voltage (VCOUT) as shown in the following equations:

Equation 1.

Equation 2.

8.3.2.2.1 Cell Amplifier Headroom Under Extreme Cell Imbalance

For cell voltages across (VC1 – VC0) that are less than approximately 2.64 V, extreme cell-voltage imbalances between (VC1 – VC0) and (VC2 – VC1) can lead to a loss of gain in the (VC2 – VC1) amplifier. The cell imbalance at which the loss of gain occurs is determined by Equation 3:

Equation 3.

Assuming VC0 = VSS, it can be seen that when (VC1 – VC0) > 2.64 volts, the voltage across (VC2 – VC1) can range up to the limit of 4.4 V without any loss of gain. At the minimum value of (VC1 – VC0) = 1.4 V, an imbalance of more than 900 mV is tolerated before any loss of gain in the (VC2 – VC1) amplifier. For higher values of (VC1 – VC0), increasingly large imbalances are tolerated. For example, when (VC1 – VC0) = 2.0 V, an imbalance up to 1.33 V (that is, (VC2 – VC1) = 3.33 V) results in no degradation of amplifier performance.

Normally, cell imbalances greater than 900 mV will signal a faulty condition of the battery pack and its use should be discontinued. The loss of gain on the second cell input does not affect the ability of the system to detect this condition. The gain fall-off is gradual so that the measured imbalance will never be less than the critical imbalance set by Equation 3.

Therefore, if the measured (VC2 – VC1) is greater than (VC1 – VSS) / 0.6, a severe imbalance is detected and the pack should enter a fault state which prevents further use. In this severe cell imbalance condition comparisons of the measured (VC2 – VC1) to any overvoltage limits will be optimistic due to the reduced gain in the amplifier, further emphasizing the need to enter a fault state.

8.3.2.2.2 Cell Amplifier Headroom Under BAT Voltage Drop

Voltage differences between BAT and the top cell potential come from two sources as shown in Figure 11: V3P3 regulator current that flows through the R_BAT filter resistor, and the voltage drop in the series diode D_BAT of the hold-up circuit. These effects cause BAT to be less than the top-cell voltage measured by the cell amplifier.

Figure 11. Sources of Voltage Drop Affecting the BAT Pin

The top-cell amplifier (VC6 – VC5) is designed to measure an input voltage down to 1.4 V with a difference between the BAT and VC6 pin up to 1.2 V (that is, BAT can be 1.2 V lower than VC6). However, in applications with fewer than 6 cells, the upper-cell inputs are typically shorted to the top-cell input. For example, in a 5-cell application VC6 and VC5 would be shorted together and the (VC5 – VC4) amplifier would measure the top-cell voltage. The case is similar for 4-cell and 3-cell applications.

For these cases when using the (VC5 – VC4), (VC4 –VC3), or (VC3 – VC2) amplifier to measure the top cell, the difference between BAT and the top-cell amplifier must be less than 240 mV in order to measure cell voltages down to 1.4 V. Note that at higher-cell input voltages the top amplifier tolerates a greater difference. For example, in a 5-cell configuration (VC6 and VC5 tied together) the (VC5 – VC4) amplifier is able to measure down to a 1.7 V input with a 600-mV difference between VC5 and BAT.

Accordingly, in systems with fewer than 6 cells, it is important in system design to minimize R_BAT and to use a Schottky type diode for D_BAT with a low forward voltage. If it is not possible to reduce the drop at BAT to an acceptable level, then for 4-cell and 5-cell configurations, the (VC6 – VC5) amplifier may be used as the top cell amplifier as shown in Table 1, which allows up to a 1.2 V difference between BAT and the top cell.

Table 1. Alternate Connections for 4 and 5 Cells

Configuration	Cell 5	Cell 4	Cell 3	Cell 2	Cell 1	Unused Cell Inputs
5-cell	VC6 – VC5	VC4 – VC3	VC3 – VC2	VC2 – VC1	VC1 – VC0	Short VC5 to VC4
4-cell		VC6 – VC5	VC3 – VC2	VC2 – VC1	VC1 – VC0	Short VC5 to VC4 to VC3

8.3.2.3 Current Monitoring

Current is measured by converting current to voltage through a sense resistor connected between SENSEN and SENSEP. A positive voltage at SENSEP with respect to SENSEN indicates a discharge current is flowing, and a negative voltage indicates a charge current. The small voltage developed across the sense resistor is amplified by gain G_VIOUT and output on the VIOUT pin for conversion by the Host ADC. The voltage on VIOUT is always positive and for zero current is set to 3/4 of the output range. The current sense amplifier is inverting; discharge current causes VIOUT to decrease and charge current causes VIOUT to increase. Therefore, the measurement range for discharge currents is 3 times the measurement range for charge currents.

The current-sense amplifier is preceded by a multiplexer that allows measurement of either the SENSEN or SENSEP input with respect to VSS. The Host selects the pin for measurement by writing the I_AMP_CAL bit in the CONFIG_1 register. The Host then calculates the voltage across the sense resistor by subtracting the measured voltage at SENSEN from the measured voltage at SENSEP. If the SENSEN and VSS connections are such that charge and discharge currents do not flow through the connection between them; that is, there is no voltage drop between SENSEN and VSS due to the current being measured, then the measurement of the SENSEN voltage can be regarded as a calibration step and stored by the Host for use as a pseudo-constant in the V_SENSE calculation. The SENSEN voltage measurement would then only need updating when changing environmental conditions warrant.

The Host sets G_VIOUT by writing the I_GAIN bit in the CONFIG_1 register. The available gains of 4 and 8 enable operation with a variety of sense-resistor values over a broad range of pack currents. The gain may be changed at any time allowing for dynamic range and resolution adjustment. The input and output ranges of the amplifier are determined by the value of the REF_SEL bit in the CONFIG_2 register. These values are shown in Table 2. Because the current amplifier is inverting, the Min column under Output Range corresponds to the Max column under Input Range. Likewise, the Max column under Output Range corresponds to the Min column under Input Range.

The actual current is calculated from the measured voltage (VIOUT) as follows. Note that V_SENSE is positive when discharge current is flowing. In keeping with battery pack conventions, the sign of I_SENSE is inverted so that discharge current is negative.

Equation 4.

8.3.2.4 Overcurrent Monitoring

The bq76925 device also includes a comparator for monitoring the current-sense resistor and alerting the Host when the voltage across the sense resistor exceeds a selected threshold. The available thresholds range from 25 mV to 400 mV and are set by writing the I_THRESH bits in the CONFIG_1 register. Positive (discharge) or negative (charge) current may be monitored by setting the I_COMP_POL bit in the CONFIG_1 register. By the choice of sense resistor and threshold, a variety of trip points are possible to support a wide range of applications.

The comparator result is driven through the open-drain ALERT output to signal the host when the threshold is exceeded. This feature can be used to wake up the Host on connection of a load or to alert the Host to a potential fault condition. The ALERT pin state is also available by reading the ALERT bit in the STATUS register.

8.3.2.5 Temperature Monitoring

To enable temperature measurements by the Host, the bq76925 device provides the LDO regulator voltage on a separate output pin (VTB) for biasing an external thermistor network. In order to minimize power consumption, the Host may switch the VTB output on and off by writing to the VTB_EN bit in the POWER_CTL register. Note that if the LDO is back-fed by an external source, the VTB bias will be switched to the external source.

In a typical application, the thermistor network will consist of a resistor in series with an NTC thermistor, forming a resistor divider where the output is proportional to temperature. This output may be measured by the Host ADC to determine temperature.

Table 3. Open Cell Detection Method

8.4.1.1 POWER ON RESET (POR)

When initially powering up the bq76925 device, the voltage on the BAT pin must exceed V_POR (4.7-V maximum) before the device will turn on. Following this, the device will remain operational as long as the voltage on BAT remains above V_SHUT (3.6-V maximum). If the BAT voltage falls below V_SHUT, the device will shut down. Recovery from shutdown occurs when BAT rises back above the V_POR threshold and is equivalent to a POR. The V_POR threshold following a shutdown depends on the minimum level reached by BAT after crossing below V_SHUT. If BAT does not fall below approximately 1.4 V, a higher V_POR (7.5-V maximum) applies. This is illustrated in Figure 12.

Figure 12. Power On State vs V_BAT

Following a power on reset, all volatile registers assume their default state. Therefore, care must be taken that transients on the BAT pin during normal operation do not fall below V_SHUT. To avoid this condition in systems subject to extreme transients or brown-outs, a hold-up circuit such as the one shown in the functional diagram is recommended. When using a hold-up circuit, care must be taken to observe the BAT to VC6 maximum ratings.

8.4.1.2 STANDBY

Individual device functions such as cell translator, current amplifier, reference, and current comparator can be enabled and disabled under Host control by writing to the POWER_CTL register. The STANDBY feature can be used to save power by disabling functions that are unused. In the minimum power standby mode, all device functions can be turned off leaving only the 3.3-V regulator active.

8.4.1.3 SLEEP

In addition to STANDBY, there is also a SLEEP mode. In SLEEP mode the Host orders the bq76925 device to shutdown all internal circuitry and all functions including the LDO regulator. The device consumes a minimal amount of current (< 1.5 μA) in SLEEP mode due only to leakage and powering of the wake-up detection circuitry.

SLEEP mode is entered by writing a ‘1’ to the SLEEP bit in the POWER_CTL register. Wake-up is achieved by pulling up the ALERT pin; however, the wake-up circuitry is not armed until the voltage at V3P3 drops to approximately 0 V. To facilitate the discharge of V3P3, an internal 3-kΩ pulldown resistor is connected from V3P3 to VSS during the time that sleep mode is active. Once V3P3 is discharged, the bq76925 may be awakened by pulling the ALERT pin above V_WAKE (2-V maximum).

The SLEEP_DIS bit in the POWER_CTL register acts as an override to the SLEEP function. When SLEEP_DIS is set to ‘1’, writing the SLEEP bit has no effect (that is, SLEEP mode cannot be entered). If SLEEP_DIS is set after SLEEP mode has been entered, the device will immediately exit SLEEP mode. This scenario can arise if SLEEP_DIS is set after SLEEP is set, but before V3P3 has discharged below a valid operating voltage. This scenario can also occur if the V3P3 pin is held up by external circuitry and not allowed to fully discharge.

If the overcurrent alert function is not used, the ALERT pin can function as a dedicated wake-up pin. Otherwise, the ALERT pin will normally be pulled up to the LDO voltage, so care must be taken in the system design so that the wake-up signal does not interfere with proper operation of the regulator.

8.5.1.1 I²C Addressing

In order to reduce communications overhead, the addressing scheme for the I²C interface combines the slave device address and device register addresses into a single 7-bit address as shown below.

ADDRESS[6:0] = (I2C_GROUP_ADDR[3:0] << 3) + REG_ADDR[4:0]

The I2C_GROUP_ADDR is a 4-bit value stored in the EEPROM. REG_ADDR is the 5-bit register address being accessed, and can range from 0x00 – 0x1F. The factory programmed value of the group address is ‘0100’. Contact TI if an alternative group address is required.

For the default I2C_GROUP_ADDR, the combined address can be formed as shown in Table 4.

8.5.1.2 Bus Write Command to bq76925

The Host writes to the registers of the bq76925 device as shown in Figure 13. The bq76925 acknowledges each received byte by pulling the SDA line low during the acknowledge period.

The Host may optionally send a CRC after the Data byte as shown. The CRC for write commands is enabled by writing the CRC_EN bit in the CONFIG_2 register. If the CRC is not used, then the Host generates the Stop condition immediately after the bq76925 acknowledges receipt of the Data byte.

When the CRC is disabled, the bq76925 device will act on the command on the first rising edge of SCL following the ACK of the Data byte. This occurs as part of the normal bus setup prior to a Stop. If a CRC byte is sent while the CRC is disabled, the first rising edge of the SCL following the ACK will be the clocking of the first bit of the CRC. The bq76925 device does not distinguish these two cases. In both cases, the command will complete normally, and in the latter case the CRC will be ignored.

Figure 13. I²C Write Command

8.5.1.3 Bus Read Command from bq76925 Device

The Host reads from the registers of the bq76925 device as shown in Figure 14. This protocol is similar to the write protocol, except that the slave now drives data back to the Host. The bq76925 device acknowledges each received byte by pulling the SDA line low during the acknowledge period. When the bq76925 device sends data back to the Host, the Host drives the acknowledge.

The Host may optionally request a CRC byte following the Data byte as shown. The CRC for read commands is always enabled, but not required. If the CRC is not used, then the Host simply NACK’s the Data byte and then generates the Stop condition.

Figure 14. I²C Read Command

Table 5. STATUS Register

Table 6. CELL_CTL

Table 7. VCOUT Pin Functions

Table 8. Cell Selection

Table 9. BAL_CTL

Table 10. CONFIG_1

Table 11. Current Comparator Threshold

Table 12. Nominal Gain of the Current Amplifier

Table 13. CONFIG_2

Table 14. Reference Voltage Selection

Table 15. POWER_CTL

Table 16. CHIP_ID

Table 17. VREF_CAL

Table 18. VC1_CAL

Table 19. VC2_CAL

Table 20. VC3_CAL

Table 21. VC4_CAL

Table 22. VC5_CAL

Table 23. VC6_CAL

Table 24. VC_CAL_EXT_1

Table 25. VC_CAL_EXT_2

Table 26. VREF_CAL_EXT

9.1.1.1 Voltage, Current, and Temperature Outputs

The bq76925 device provides voltage, current, and temperature outputs in analog form. A microcontroller (MCU) with an analog-to-digital converter (ADC) is required to complete the measurement system. A minimum of three input-ADC channels of the MCU are required to measure cell voltages, current, and temperature output. The bq76925 device can supply an external reference for the MCU ADC reference, Compare the internal reference voltage specification of the MCU to determine if using the AFE reference would improve the measurement accuracy.

9.1.1.2 Power Management

The bq76925 device can disable varies functions for power management. Refer to the POWER_CTL registers in this document for detailed descriptions. Additionally, the MCU can put the bq76925 device into SHUTDOWN mode by writing to the [SLEEP] bit in the POWER_CTL register. The wake up circuit does not activate until the V3P3 is completing discharge to 0 V. Once the wake up circuit is activated, pulling the ALERT pin high can wake up the device. This means, once the SLEEP command is sent, the bq76925 device remains in SHUTDOWN mode and cannot wake up if V3P3 is > 0 V.

9.1.1.3 Low Dropout (LDO) Regulator

When the LDO load current is higher than 4 mA, the LDO must be used with an external pass transistor. In this configuration, a high-gain bypass device is recommended. ZXTP2504DFH and IRLML9303 are example transistors. A Z1 diode is recommended to protect the gate-source or base emitter of the bypass transistor.

Adding the R_V3P3 and C_V3P3-2 filter helps to isolate the load from the V3P3 transient caused by the load and the transients on BAT.

Figure 15. LDO Regulator

9.1.1.4 Input Filters

TI recommends to use input filters for BAT, VCx, and SENSEN/P pins to protect the bq76925 device from large transients caused by switching of the battery load.

Additionally, the filter on BAT also avoids unintentional reset of the AFE when the battery voltage suddenly drops. To further avoid an unwanted reset, a hold-up circuit using a blocking diode can be added in series with the input filter. A zener diode clamp may be added in parallel with the filter capacitor to prevent the repeated peak transients that pump up the filter capacitor beyond the device absolute maximum rating.

9.1.1.5 Output Filters

Output capacitors are used on V3P3, VREF, VCOUT, and VIOUT for stability. These capacitors also function as bypass capacitors in response to the MCU internal switching and ADC operation. Additional filtering may be added to these output pins to smooth out noisy signals prior to ADC conversion. For the V3P3 case, an additional filter helps reduce the transient on the power input connected to the bq76925 device's V3P3 pin.

Table 27. Design Parameters