TPS53355 是一款具有集成 MOSFET 的 D-CAP™ 模式、30A 同步转换器。它的设计目标是简单易用、减少外部元件,以及适用于空间受限的电源系统。
该器件具有 5mΩ/2mΩ 集成 MOSFET、1% 精度、0.6V 基准电压和集成的升压开关。具有竞争力的特性示例包括:1.5V 至 15V 宽转换输入电压范围、超低的外部元件数、针对超快瞬变的 D-CAP™ 模式控制、自动跳跃模式运行、内部软启动控制、可选频率并且无需补偿。
转换输入电压范围为 1.5V 至 15V,电源电压范围为 4.5V 至 25V,输出电压范围为 0.6V 至 5.5V。
该器件采用 22 引脚 6mm × 5mm QFN 封装。
LMZ31530 将 TPS53355 电感器和其他无源器件集成在一个易于使用的小型模块中。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPS53355 | LSON-CLIP (22) | 6.00mm × 5.00mm |
Changes from Revision F (June 2019) to Revision G (April 2021)
Changes from Revision E (March 2019) to Revision F (June 2019)
Changes from Revision D (November 2016) to Revision E (March 2019)
Changes from Revision C (February 2016) to Revision D (November 2016)
Changes from Revision B (January 2014) to Revision C (February 2016)
Changes from Revision A (September 2012) to Revision B (January 2014)
Changes from Revision * (August 2011) to Revision A (September 2012)
PIN | I/O/P(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO | |||
EN | 2 | I | Enable pin. Typical turn-on threshold voltage is 1.2 V. Typical turn-off threshold is 0.95 V. | |
GND | — | — | Ground and thermal pad of the device. Use proper number of vias to connect to ground plane. | |
LL | 6 | B | Output of converted power. Connect this pin to the output Inductor. | |
7 | ||||
8 | ||||
9 | ||||
10 | ||||
11 | ||||
MODE | 20 | I | Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 7-3. The soft-start time is detected and stored into internal register during start-up. | |
N/C | 5 | No connect. | ||
PGOOD | 3 | O | Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB goes out of the specified limits PGOOD goes low after a 2-µs delay. | |
RF | 22 | I | Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 7-1. The switching frequency is detected and stored during the startup. | |
TRIP | 21 | I | OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows: | |
VOCL = VTRIP/32 | (VTRIP ≤ 2.4 V, VOCL ≤ 75 mV) | |||
VBST | 4 | P | Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node. Internally connected to VREG via bootstrap MOSFET switch. | |
VDD | 19 | P | Controller power supply input. VDD input voltage range is from 4.5 V to 25 V. | |
VFB | 1 | I | Output feedback input. Connect this pin to Vout through a resistor divider. | |
VIN | 12 | P | Conversion power input. VIN input voltage range is from 1.5 V to 15 V. | |
13 | ||||
14 | ||||
15 | ||||
16 | ||||
17 | ||||
VREG | 18 | P | 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage | VIN (main supply) | –0.3 | 25 | V | |
VDD | –0.3 | 28 | |||
VBST | –0.3 | 32 | |||
VBST (with respect to LL) | –0.3 | 7 | |||
EN, TRIP, VFB, RF, MODE | –0.3 | 7 | |||
Output voltage | LL | DC | –2 | 25 | V |
Pulse < 20 ns, E = 5 μJ | –7 | 27 | |||
PGOOD, VREG | –0.3 | 7 | |||
GND | –0.3 | 0.3 | |||
Source/sink current | VBST | 50 | mA | ||
Junction temperature, TJ | –40 | 150 | °C | ||
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds | 300 | °C | |||
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |