ADS1291、ADS1292 和 ADS1292R 是多通道同步采样 24 位 Δ-Σ 模数转换器 (ADC),它们具有内置的可编程增益放大器 (PGA)、内部基准和板载振荡器。
ADS1291、ADS1292 和 ADS1292R 包含 便携式 低功耗医疗心电图 (ECG)、体育和健身 应用通常所需的所有功能。
凭借高集成度和出色的性能,ADS1291、ADS1292 和 ADS1292R 可在显著减少尺寸、功耗和总体成本的前提下创建可扩展的医疗仪器系统。
ADS1291、ADS1292 和 ADS1292R 每通道具有灵活的输入多路复用器,此多路复用器可独立连接至内部生成的信号,实现测试、温度和持续断线检测。此外,可选择输入通道的任一配置生成右腿驱动 (RLD) 输出信号。ADS1291、ADS1292 和 ADS1292R 工作时的数据速率高达 8kSPS。通过器件内部激励灌电流或拉电流,可在器件内部执行持续断线检测。ADS1292R 版本包括一个完全集成的呼吸阻抗测量功能。
这些器件采用 5mm × 5mm、32 引脚薄型四方扁平封装 (TQFP) 和 4mm x 4mm、32 引脚无引线四方扁平封装 (VQFN)。额定工作温度范围 –40°C 至 +85°C。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
ADS129x | TQFP (32) | 5.00mm × 5.00mm |
VQFN (32) | 4.00mm × 4.00mm |
Changes from B Revision (September 2012) to C Revision
Changes from A Revision (March 2012) to B Revision
Changes from * Revision (December 2011) to A Revision
PIN | FUNCTION | DESCRIPTION | ||
---|---|---|---|---|
NO. | PBS (TQFP) | RSM (VQFN) | ||
1 | PGA1N | PGA1N | Analog output | PGA1 inverting output |
2 | PGA1P | PGA1P | Analog output | PGA1 noninverting output |
3 | IN1N(1) | IN1N(1) | Analog input | Differential analog negative input 1 |
4 | IN1P(1) | IN1P(1) | Analog input | Differential analog positive input 1 |
5 | IN2N(1) | IN2N(1) | Analog input | Differential analog negative input 2 |
6 | IN2P(1) | IN2P(1) | Analog input | Differential analog positive input 2 |
7 | PGA2N | PGA2N | Analog output | PGA2 inverting output |
8 | PGA2P | PGA2P | Analog output | PGA2 noninverting output |
9 | VREFP | VREFP | Analog input/output | Positive reference voltage |
10 | VREFN | VREFN | Analog input | Negative reference voltage; must be connected to AVSS |
11 | VCAP1 | VCAP1 | — | Analog bypass capacitor |
12 | AVDD | AVDD | Supply | Analog supply |
13 | AVSS | AVSS | Supply | Analog ground |
14 | CLKSEL | CLKSEL | Digital input | Master clock select |
15 | PWDN/RESET | PWDN/RESET | Digital input | Power-down or system reset; active low |
16 | START | START | Digital input | Start conversion |
17 | CLK | CLK | Digital input | Master clock input |
18 | CS | CS | Digital input | Chip select |
19 | DIN | DIN | Digital input | SPI data in |
20 | SCLK | SCLK | Digital input | SPI clock |
21 | DOUT | DOUT | Digital output | SPI data out |
22 | DRDY | DRDY | Digital output | Data ready; active low |
23 | DVDD | DVDD | Supply | Digital power supply |
24 | DGND | DGND | Supply | Digital ground |
25 | GPIO2/RCLK2 | GPIO2/RCLK2 | Digital input/output | General-purpose I/O 2 or resp clock 2 (ADS1292R) |
26 | GPIO1/RCLK1 | GPIO1/RCLK1 | Digital input/output | General-purpose I/O 1 or resp clock 1 (ADS1292R) |
27 | VCAP2 | VCAP2 | — | Analog bypass capacitor |
28 | RLDINV | RLDINV | Analog input | Right leg drive inverting input; connect to AVDD if not used |
29 | RLDIN/ RLDREF | RLDIN/ RLDREF | Analog input | Right leg drive input to MUX or RLD amplifier noninverting input; connect to AVDD if not used |
30 | RLDOUT | RLDOUT | Analog output | Right leg drive output |
31 | RESP_MODP/ IN3P(1) | RESP_MODP/ IN3P(1) | Analog output/input | P-side respiration excitation signal for respiration (analog output) or auxiliary input 3P (analog input) |
32 | RESP_MODN/ IN3N(1) | RESP_MODN/ IN3N(1) | Analog output/input | N-side respiration excitation signal for respiration (analog output) or auxiliary input 3N (analog input) |
Power Pad | — | Pad | — | Thermal pad; must be connected to AVSS |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog power supply, AVDD to AVSS | 2.7 | 5 | 5.25 | V |
DVDD | Digital power supply, DVDD to DGND | 1.7 | 3 | 3.6 | V |
Analog input voltage | AVSS | AVDD | V | ||
Digital input voltage | DVSS | DVDD | V | ||
TA | Operating ambient temperature | –40 | 85 | °C |
THERMAL METRIC(1) | ADS1291, ADS1292, ADS1292R | UNIT | ||
---|---|---|---|---|
PBS (TQFP) | RSM (VQFN) | |||
32 PINS | 32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 68.4 | 33.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.9 | 36.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 30.5 | 25.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 24.3 | 7.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 2.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG INPUTS | |||||||
Full-scale differential input voltage
(AINP – AINN) |
±VREF / gain | V | |||||
Input common-mode range | See the Input Common-Mode Range subsection of the PGA Settings and Input Range section | ||||||
Input capacitance | 20 | pF | |||||
Input bias current (PGA chop = 8 kHz) | TA = +25°C, input = 1.5 V | ±200 | pA | ||||
TA = –40°C to +85°C, input = 1.5 V | ±1 | nA | |||||
Chop rates other than 8 kHz | See Pace Detect section | ||||||
DC input impedance | No pull-up or pull-down current source | 1000 | MΩ | ||||
Current source lead-off detection (nA),
AVSS + 0.3 V < AIN < AVDD – 0.3 V |
500 | MΩ | |||||
Current source lead-off detection (µA),
AVSS + 0.6 V < AIN < AVDD – 0.6 V |
100 | MΩ | |||||
PGA PERFORMANCE | |||||||
Gain settings | 1, 2, 3, 4, 6, 8, 12 | ||||||
Bandwidth | With a 4.7-nF capacitor on PGA output
(see PGA Settings and Input Range section for details) |
8.5 | kHz | ||||
ADC PERFORMANCE | |||||||
Resolution | 24 | Bits | |||||
Data rate | fCLK = 512 kHz | 125 | 8000 | SPS | |||
CHANNEL PERFORMANCE (DC Performance) | |||||||
Input-referred noise | Gain = 6(1), 10 seconds of data | 8 | μVPP | ||||
Gain = 6, 256 points, 0.5 seconds of data | 8 | 11 | μVPP | ||||
Gain settings other than 6,
data rates other than 500 SPS |
See Noise Measurements section | ||||||
Integral nonlinearity | Full-scale with gain = 6, best fit | 2 | ppm | ||||
Offset error | ±100 | μV | |||||
Offset error drift | 2 | μV/°C | |||||
Offset error with calibration | 15 | μV | |||||
Gain error | Excluding voltage reference error | ±0.1 | ±0.2 | % of FS | |||
Gain drift | Excluding voltage reference drift | 2 | ppm/°C | ||||
Gain match between channels | 0.2 | % of FS | |||||
CHANNEL PERFORMANCE (AC performance) | |||||||
CMRR | Common-mode rejection ratio | fCM = 50 Hz and 60 Hz(2) | 105 | 120 | dB | ||
PSRR | Power-supply rejection ratio | fPS = 50 Hz and 60 Hz | 90 | dB | |||
Crosstalk | fIN = 50 Hz and 60 Hz | –120 | dB | ||||
SNR | Signal-to-noise ratio | fIN = 10 Hz input, gain = 6 | 107 | dB | |||
THD | Total harmonic distortion | 10 Hz, –0.5 dBFs, CFILTER = 4.7nF | –104 | dB | |||
100 Hz, –0.5 dBFs, CFILTER = 4.7nF | –95 | dB | |||||
ADS1292R channel 1, 10 Hz, –0.5 dBFS, CFILTER = 47 nF | –82 | dB | |||||
DIGITAL FILTER | |||||||
–3-dB bandwidth | 0.262 fDR | Hz | |||||
Digital filter settling | Full setting | 4 | Conversions | ||||
RIGHT LEG DRIVE (RLD) AMPLIFIER | |||||||
RLD integrated noise | BW = 150 Hz | 1.4 | μVRMS | ||||
GBP | Gain bandwidth product | 50 kΩ || 10 pF load, gain = 1 | 100 | kHz | |||
SR | Slew rate | 50 kΩ || 10 pF load, gain = 1 | 0.07 | V/μs | |||
THD | Total harmonic distortion | fIN = 100 Hz, gain = 1 | –85 | dB | |||
CMIR | Common-mode input range | AVSS + 0.3 | AVDD – 0.3 | V | |||
Common-mode resistor matching | Internal 200-kΩ resistor matching | 0.1 | % | ||||
ISC | Short-circuit current | 1.1 | mA | ||||
Quiescent power consumption | 5 | μA | |||||
LEAD-OFF DETECT | |||||||
Frequency | See Register Map section for settings | 0, fDR / 4 | kHz | ||||
Current | ILEAD_OFF [1:0] = 00 | 6 | nA | ||||
ILEAD_OFF [1:0] = 01 | 22 | nA | |||||
ILEAD_OFF [1:0] = 10 | 6 | μA | |||||
ILEAD_OFF [1:0] = 11 | 22 | μA | |||||
Current accuracy | ±10 | % | |||||
Comparator threshold accuracy | ±10 | mV | |||||
RESPIRATION (ADS1292R) | |||||||
Frequency | Internal source | 32, 64 | kHz | ||||
External source | 32 | 64 | kHz | ||||
Phase shift | See Register Map section for settings | 0 | 112.5 | 168.75 | Degrees | ||
Impedance range | IRESP = 30 µA | 2000 | 10,000 | Ω | |||
Impedance measurement noise | 0.05-Hz to 2-Hz brick wall filter, 32-kHz modulation clock, phase = 112.5,
using IRESP = 30 µA with 2-kΩ baseline load, gain = 4 |
40 | mΩPP | ||||
Maximum modulator current | Using Internal reference | 100 | μA | ||||
EXTERNAL REFERENCE | |||||||
Reference input voltage | 3-V supply VREF = (VREFP – VREFN) | 2 | 2.5 | VDD – 0.3 | V | ||
5-V supply VREF = (VREFP – VREFN) | 2 | 4 | VDD – 0.3 | V | |||
VREFN | Negative input | AVSS | V | ||||
VREFP | Positive input | AVSS + 2.5 | V | ||||
Input impedance | 120 | kΩ | |||||
INTERNAL REFERENCE | |||||||
Output voltage | Register bit CONFIG2.VREF_4V = 0 | 2.42 | V | ||||
Register bit CONFIG2.VREF_4V = 1 | 4.033 | V | |||||
Output current drive | Available for external use | 100 | µA | ||||
VREF accuracy | ±0.5 | % | |||||
Internal reference drift | –40°C ≤ TA ≤ +85°C | 45 | ppm/°C | ||||
Start-up time | Settled to 0.2% with 10-µF capacitor on VREFP pin | 100 | ms | ||||
Quiescent current consumption | 20 | µA | |||||
SYSTEM MONITORS | |||||||
Analog supply reading error | 1 | % | |||||
Digital supply reading error | 1 | % | |||||
Device wake up | From power-supply ramp after power-on reset (POR) to DRDY low | 32 | ms | ||||
From power-down mode to DRDY low | 10 | ms | |||||
From STANDBY mode to DRDY low | 10 | ms | |||||
VCAP1 settling time | 1% accuracy | 0.5 | s | ||||
Temperature sensor reading | Voltage | TA = +25°C | 145 | mV | |||
Coefficient | 490 | μV/°C | |||||
TEST SIGNAL | |||||||
Signal frequency | See Register Map section for settings | At dc and 1 Hz | Hz | ||||
Signal voltage | See Register Map section for settings | ±1 | mV | ||||
Accuracy | ±2 | % | |||||
CLOCK | |||||||
Internal oscillator clock frequency | Nominal frequency | 512 | kHz | ||||
Internal clock accuracy | TA = +25°C | ±0.5 | % | ||||
–40°C ≤ TA ≤ +85°C | ±1.5 | % | |||||
Internal oscillator start-up time | 32 | μs | |||||
Internal oscillator power consumption | 30 | μW | |||||
External clock input frequency | CLKSEL pin = 0, CLK_DIV = 0 | 485 | 512 | 562.5 | kHz | ||
CLKSEL pin = 0, CLK_DIV = 1 | 1.94 | 2.048 | 2.25 | MHz | |||
DIGITAL INPUT/OUTPUT | |||||||
VIH | Logic level | DVDD = 1.8 V to 3.6 V | 0.8 DVDD | DVDD + 0.1 | V | ||
VIL | DVDD = 1.8 V to 3.6 V | –0.1 | 0.2 DVDD | V | |||
VIH | DVDD = 1.7 V to 1.8 V | DVDD – 0.2 | V | ||||
VIL | DVDD = 1.7 V to 1.8 V | 0.2 | V | ||||
VOH | DVDD = 1.7 V to 3.6 V | IOH = –500 μA | 0.9 DVDD | V | |||
VOL | DVDD = 1.7 V to 3.6 V | IOL = +500 μA | 0.1 DVDD | V | |||
IIN | Input current | 0 V < VDigitalInput < DVDD | –10 | +10 | μA | ||
POWER-SUPPLY REQUIREMENTS | |||||||
AVDD | Analog supply | AVDD – AVSS | 2.7 | 3 | 5.25 | V | |
DVDD | Digital supply | DVDD – DGND | 1.7 | 1.8 | 3.6 | V | |
AVDD – DVDD | –2.1 | 3.6 | V | ||||
SUPPLY CURRENT (RLD Amplifier Turned Off) | |||||||
IAVDD | ADS1292 and ADS1292R | AVDD – AVSS = 3 V | 205 | μA | |||
AVDD – AVSS = 5 V | 250 | μA | |||||
IDVDD | ADS1292 and ADS1292R | DVDD = 3.3 V | 75 | μA | |||
DVDD = 1.8 V | 32 | μA | |||||
POWER DISSIPATION (Analog Supply = 3 V, RLD Amplifier Turned Off) | |||||||
Quiescent power dissipation | ADS1292 and ADS1292R | Normal mode | 670 | 740 | µW | ||
Standby mode | 160 | µW | |||||
ADS1291 | Normal mode | 450 | 495 | µW | |||
Standby mode | 160 | µW | |||||
Quiescent power dissipation, per channel | ADS1292R | Normal mode | 335 | µW | |||
ADS1292 | Normal mode | 335 | µW | ||||
ADS1291 | Normal mode | 450 | µW | ||||
POWER DISSIPATION (Analog Supply = 5 V, RLD Amplifier Turned Off) | |||||||
Quiescent power dissipation | ADS1292 and ADS1292R | Normal mode | 1300 | µW | |||
Standby mode | 340 | µW | |||||
ADS1291 | Normal mode | 950 | µW | ||||
Standby mode | 340 | µW | |||||
Quiescent power dissipation, per channel | ADS1292R | Normal mode | 670 | µW | |||
ADS1292 | Normal mode | 670 | µW | ||||
ADS1291 | Normal mode | 860 | µW | ||||
POWER DISSIPATION IN POWER-DOWN MODE | |||||||
Analog supply = 3 V | DVDD = 1.8 V | 1 | µW | ||||
DVDD = 3.3 V | 4 | µW | |||||
Analog supply = 5 V | DVDD = 1.8 V | 5 | µW | ||||
DVDD = 3.3 V | 10 | µW | |||||
TEMPERATURE | |||||||
Specified temperature range | –40 | +85 | °C | ||||
Operating temperature range | –40 | +85 | °C | ||||
Storage temperature range | –60 | +150 | °C |
2.7 V ≤ DVDD ≤ 3.6 V | 1.7 V ≤ DVDD ≤ 2 V | UNIT | ||||||
---|---|---|---|---|---|---|---|---|
MIN | NOM | MAX | MIN | NOM | MAX | |||
tCLK | Master clock period (CLK_DIV bit of LOFF_STAT register = 0) | 1775 | 2170 | 1775 | 2170 | ns | ||
Master clock period (CLK_DIV bit of LOFF_STAT register = 1) | 444 | 542 | 444 | 542 | ns | |||
tCSSC | CS low to first SCLK, setup time | 6 | 17 | ns | ||||
tSCLK | SCLK period | 50 | 66.6 | ns | ||||
tSPWH, L | SCLK pulse width, high and low | 15 | 25 | ns | ||||
tDIST | DIN valid to SCLK falling edge: setup time | 10 | 10 | ns | ||||
tDIHD | Valid DIN after SCLK falling edge: hold time | 10 | 11 | ns | ||||
tDOPD | SCLK rising edge to DOUT valid | 12 | 22 | ns | ||||
tCSH | CS high pulse | 2 | 2 | tCLKs | ||||
tCSDOD | CS low to DOUT driven | 10 | 20 | ns | ||||
tSCCS | Eighth SCLK falling edge to CS high | 3 | 3 | tCLKs | ||||
tSDECODE | Command decode time | 4 | 4 | tCLKs | ||||
tCSDOZ | CS high to DOUT Hi-Z | 10 | 20 | ns |
NOTE:
SPI settings are CPOL = 0 and CPHA = 1.The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 through Table 8 summarize the ADS1291, ADS1292, and ADS1292R noise performance. The data are representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. For the shown data rates, the ratio is approximately 6.6.
Table 1 through Table 8 show measurements taken with an internal reference. The data are also representative of the ADS1291, ADS1292, and ADS1292R noise performance when using a low-noise external reference such as the REF5025.
In Table 1 through Table 8, µVRMS and µVPP are measured values. Effective resolution (EFF RESOL) and dynamic range (DYN RANGE) are calculated with Equation 1 and Equation 2.
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 1 | PGA GAIN = 2 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 1.5 | 10.3 | 121.0 | 18.83 | 20.10 | 0.8 | 5.6 | 120.0 | 18.71 | 19.94 |
001 | 250 | 65.5 | 2.2 | 14.4 | 117.8 | 18.34 | 19.58 | 1.2 | 7.5 | 117.1 | 18.29 | 19.46 |
010 | 500 | 131 | 3.0 | 18.9 | 115.1 | 17.95 | 19.11 | 1.7 | 10.9 | 113.9 | 17.75 | 18.91 |
011 | 1000 | 262 | 4.6 | 30.8 | 111.3 | 17.25 | 18.49 | 2.5 | 15.6 | 110.6 | 17.23 | 18.37 |
100 | 2000 | 524 | 10.1 | 99 | 104.5 | 15.57 | 17.36 | 5.3 | 48 | 104.0 | 15.60 | 17.28 |
101 | 4000 | 1048 | 55.2 | 563 | 89.7 | 13.06 | 14.91 | 26.0 | 265 | 90.3 | 13.14 | 15.00 |
110 | 8000 | 2096 | 287.3 | 2930 | 75.4 | 10.68 | 12.53 | 144.1 | 1470 | 75.4 | 10.67 | 12.52 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 3 | PGA GAIN = 4 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.6 | 4.1 | 119.2 | 18.58 | 19.80 | 0.5 | 3.4 | 117.9 | 18.42 | 19.58 |
001 | 250 | 65.5 | 0.9 | 5.5 | 115.9 | 18.15 | 19.26 | 0.8 | 5.0 | 114.8 | 17.88 | 19.07 |
010 | 500 | 131 | 1.3 | 7.7 | 113.0 | 17.67 | 18.77 | 1.1 | 6.6 | 111.9 | 17.47 | 18.59 |
011 | 1000 | 262 | 1.9 | 12.0 | 109.5 | 17.02 | 18.19 | 1.6 | 10.3 | 108.7 | 16.83 | 18.06 |
100 | 2000 | 524 | 3.7 | 31 | 103.7 | 15.65 | 17.23 | 2.9 | 23 | 103.2 | 15.69 | 17.14 |
101 | 4000 | 1048 | 17.0 | 173 | 90.5 | 13.18 | 15.03 | 12.2 | 124 | 90.8 | 13.24 | 15.09 |
110 | 8000 | 2096 | 91.9 | 937 | 75.8 | 10.74 | 12.59 | 66.8 | 681 | 76.1 | 10.78 | 12.63 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 6 | PGA GAIN = 8 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.5 | 3.0 | 115.9 | 18.04 | 19.26 | 0.4 | 2.6 | 114.0 | 17.82 | 18.94 |
001 | 250 | 65.5 | 0.7 | 4.1 | 112.8 | 17.58 | 18.73 | 0.6 | 3.9 | 111.0 | 17.22 | 18.44 |
010 | 500 | 131 | 0.9 | 5.6 | 109.9 | 17.14 | 18.25 | 0.8 | 5.5 | 108.0 | 16.75 | 17.93 |
011 | 1000 | 262 | 1.3 | 8.7 | 106.8 | 16.49 | 17.73 | 1.2 | 7.6 | 104.9 | 16.26 | 17.42 |
100 | 2000 | 524 | 2.2 | 16 | 102.1 | 15.64 | 16.96 | 2.0 | 14 | 100.7 | 15.36 | 16.72 |
101 | 4000 | 1048 | 7.5 | 77 | 91.5 | 13.34 | 15.19 | 5.5 | 56 | 91.7 | 13.39 | 15.24 |
110 | 8000 | 2096 | 42.7 | 436 | 76.4 | 10.84 | 12.69 | 31.3 | 319 | 76.6 | 10.88 | 12.73 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 12 | ||||
---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.4 | 2.5 | 111.3 | 17.31 | 18.48 |
001 | 250 | 65.5 | 0.5 | 3.5 | 108.4 | 16.81 | 18.01 |
010 | 500 | 131 | 0.8 | 5.0 | 105.0 | 16.29 | 17.44 |
011 | 1000 | 262 | 1.1 | 6.9 | 102.1 | 15.82 | 16.97 |
100 | 2000 | 524 | 1.7 | 11 | 98.6 | 15.21 | 16.38 |
101 | 4000 | 1048 | 3.5 | 36 | 92.0 | 13.44 | 15.29 |
110 | 8000 | 2096 | 20.1 | 205 | 76.9 | 10.93 | 12.78 |
111 | NA | NA | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 1 | PGA GAIN = 2 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 1.6 | 10.2 | 124.9 | 19.58 | 20.75 | 0.9 | 5.4 | 124.3 | 19.50 | 20.65 |
001 | 250 | 65.5 | 2.2 | 13.3 | 122.3 | 19.20 | 20.31 | 1.2 | 8.1 | 121.3 | 18.91 | 20.15 |
010 | 500 | 131 | 3.1 | 18.9 | 119.3 | 18.69 | 19.82 | 1.7 | 10.6 | 118.2 | 18.52 | 19.63 |
011 | 1000 | 262 | 4.9 | 31.9 | 115.2 | 17.94 | 19.14 | 2.7 | 17.9 | 114.4 | 17.77 | 19.00 |
100 | 2000 | 524 | 15.5 | 167 | 105.2 | 15.55 | 17.48 | 7.5 | 80 | 105.5 | 15.62 | 17.53 |
101 | 4000 | 1048 | 89.6 | 959 | 90.0 | 13.03 | 14.95 | 45.0 | 481 | 89.9 | 13.02 | 14.94 |
110 | 8000 | 2096 | 460.1 | 4923 | 75.8 | 10.67 | 12.59 | 229.0 | 2450 | 75.8 | 10.67 | 12.59 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 3 | PGA GAIN = 4 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.6 | 4.2 | 123.4 | 19.28 | 20.50 | 0.5 | 3.6 | 122.3 | 19.08 | 20.32 |
001 | 250 | 65.5 | 0.9 | 5.7 | 120.7 | 18.82 | 20.04 | 0.7 | 4.8 | 119.5 | 18.66 | 19.86 |
010 | 500 | 131 | 1.3 | 8.4 | 117.3 | 18.27 | 19.49 | 1.1 | 7.4 | 116.2 | 18.04 | 19.31 |
011 | 1000 | 262 | 2.0 | 13.3 | 113.5 | 17.62 | 18.85 | 1.6 | 11.0 | 112.7 | 17.48 | 18.72 |
100 | 2000 | 524 | 5.1 | 53 | 105.3 | 15.61 | 17.49 | 3.9 | 38 | 105.2 | 15.67 | 17.47 |
101 | 4000 | 1048 | 28.7 | 307 | 90.3 | 13.08 | 15.00 | 20.7 | 222 | 90.6 | 13.14 | 15.06 |
110 | 8000 | 2096 | 149.3 | 1598 | 76.0 | 10.70 | 12.62 | 111.8 | 1196 | 76.0 | 10.71 | 12.63 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 6 | PGA GAIN = 8 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.5 | 3.0 | 120.4 | 18.78 | 19.99 | 0.4 | 2.7 | 118.5 | 18.48 | 19.68 |
001 | 250 | 65.5 | 0.6 | 4.0 | 117.5 | 18.36 | 19.52 | 0.6 | 3.8 | 115.7 | 18.01 | 19.21 |
010 | 500 | 131 | 0.9 | 6.0 | 114.3 | 17.75 | 18.99 | 0.8 | 5.3 | 112.8 | 17.53 | 18.74 |
011 | 1000 | 262 | 1.4 | 8.8 | 110.8 | 17.20 | 18.41 | 1.2 | 8.1 | 109.5 | 16.92 | 18.19 |
100 | 2000 | 524 | 2.8 | 24 | 104.6 | 15.74 | 17.38 | 2.3 | 18 | 103.6 | 15.73 | 17.22 |
101 | 4000 | 1048 | 13.3 | 142 | 91.0 | 13.20 | 15.12 | 9.3 | 100 | 91.5 | 13.29 | 15.21 |
110 | 8000 | 2096 | 71.5 | 765 | 76.4 | 10.77 | 12.69 | 52.3 | 560 | 76.6 | 10.80 | 12.72 |
111 | NA | NA | — | — | — | — | — | — | — | — | — | — |
DR BITS OF CONFIG1 REGISTER | OUTPUT DATA RATE (SPS) | –3-dB BANDWIDTH (Hz) | PGA GAIN = 12 | ||||
---|---|---|---|---|---|---|---|
μVRMS | μVPP | DYN RANGE | EFF RESOL | ENOB | |||
000 | 125 | 32.75 | 0.4 | 2.6 | 115.7 | 17.96 | 19.21 |
001 | 250 | 65.5 | 0.5 | 3.4 | 112.9 | 17.59 | 18.75 |
010 | 500 | 131 | 0.8 | 5.2 | 109.8 | 16.96 | 18.24 |
011 | 1000 | 262 | 1.1 | 6.9 | 106.6 | 16.56 | 17.70 |
100 | 2000 | 524 | 1.9 | 14 | 101.9 | 15.57 | 16.83 |
101 | 4000 | 1048 | 5.9 | 63 | 92.0 | 13.37 | 15.29 |
110 | 8000 | 2096 | 33.8 | 362 | 76.9 | 10.85 | 12.77 |
111 | NA | NA | — | — | — | — | — |
The ADS1291, ADS1292, and ADS1292R are low-power, multichannel, simultaneously-sampling, 24-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various electrocardiogram (ECG)-specific functions that make them well-suited for scalable ECG, sports, and fitness applications. The devices can also be used in high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry.
The ADS1291, ADS1292, and ADS1292R have a highly programmable multiplexer that allows for temperature, supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The ADCs in the device offer data rates from 125 SPS to 8 kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides two general-purpose I/O (GPIO) pins for general use. Multiple devices can be synchronized using the START pin.
The internal reference can be programmed to either 2.42 V or 4.033 V. The internal oscillator generates a 512-kHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using an external pull-up or pull-down resistor or the device internal current source or sink. An internal ac lead-off detection feature is also available. Apart from the above features, the ADS1292R provides options for internal respiration circuitry. Functional Block Diagram shows a block diagram for the ADS1291, ADS1292, and ADS1292R.