• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TPD4S014 USB 充电器端口保护，包括为所有线路提供 ESD 保护以及在 VBUS 中实现过压保护

    • ZHCS116G May   2011  – December 2015 TPD4S014

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TPD4S014 USB 充电器端口保护，包括为所有线路提供 ESD 保护以及在 VBUS 中实现过压保护
  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, EN, ACK, D+, D-, ID Pins
    6. 6.6 Electrical Characteristics OVP Circuits
    7. 6.7 Supply Current Consumption
    8. 6.8 Thermal Shutdown Feature
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Protection at VBUS up to 28 V DC
      2. 7.3.2 Low RON nFET Switch
      3. 7.3.3 ESD Performance D+/D-/ID/VBUS Pins
      4. 7.3.4 Overvoltage and Undervoltage Lockout Features
      5. 7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate
      6. 7.3.6 Start-up Delay
      7. 7.3.7 OVP Glitch Immunity
      8. 7.3.8 Integrated Input Enable and Status Output Signal
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 For Non-OTG USB Systems
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 For OTG USB Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPD4S014 USB 充电器端口保护，包括为所有线路提供 ESD 保护以及在 VBUS 中实现过压保护

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • VBUS 上达 28 V 的输入电压保护
  • 导通电阻 (Ron) 较低的 N 沟道场效应晶体管 (FET) 开关
  • 支持大于 2A 的充电电流
  • 静电放电 (ESD) 性能 D+/D–/ID/VBUS 引脚：
    • ±15kV 接触放电 (IEC 61000-4-2)
    • ±15kV 空气间隙放电 (IEC 61000-4-2)
  • 过压和欠压锁定 功能
  • 针对 USB2.0 高速数据率的低电容瞬态电压抑制器 (TVS) ESD 钳位
  • 内部 17ms 启动延迟
  • 集成输入使能和状态输出信号
  • 热关断特性
  • 采用节省空间的小外形尺寸无引线 (SON) 封装 (2 mm × 2 mm)

2 应用范围

  • 手机
  • 电子书
  • 便携式媒体播放器
  • 数码摄像机

3 说明

TPD4S014 是一款用于 USB 充电器端口保护的单芯片解决方案。该器件为 D+、D- 提供低电容瞬态电压抑制器 (TVS) 静电放电 (ESD) 钳位并为 ID 引脚提供标准电容。该器件在 VBUS 引脚提供直流电压高达 28V 的过压保护 (OVP)。过压锁定功能可确保当 VBUS 线路出现故障情况时，TPD4S014 能够隔离 VBUS 线路，从而避免内部电路受损。VBUS 升至欠压锁定 (UVLO) 阈值后存在 17ms 开机延迟，从而在 nFET 导通前使电压趋于稳定。该功能可去除毛刺脉冲并避免因线路连接过程中出现的任何振铃问题导致意外开关。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPD4S014 WSON (10) 2.00mm x 2.00mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化框图

TPD4S014 app_dia_lvsau0.gif

4 修订历史记录

Changes from F Revision (September 2015) to G Revision

  • Added a frequency test condition to capacitance in the Electrical Characteristics table. Go

Changes from E Revision (June 2014) to F Revision

  • Corrected VDROP on nFET under loadGo

Changes from D Revision (April 2014) to E Revision

  • Updated Recommended Operating Conditions table. Go
  • Changed terminal name to ILEAK from ILGo
  • Updated Electrical Characteristics OVP Circuits table.Go
  • Changed tON MAX value from 18 ms to 22ms Go
  • Changed tOFF 8 µs value from MAX to TYP.Go
  • Changed td(OVP) 11 µs value from MAX to TYP.Go
  • Changed tREC MAX value from 9 ms to 10.5 ms. Go
  • Updated Application and Implementation section. Go

Changes from C Revision (December 2011) to D Revision

  • Added ESD Ratings table.Go
  • Added Recommended Operating Conditions table.Go
  • Added Thermal Information table. Go
  • Updated Electrical Characteristics OVP Circuits table.Go

Changes from B Revision (October 2011) to C Revision

  • 已通过更改数据表严格限定了参数，VOP+ 由 5.55V 变更为 5.9V。Go
  • 已更新 说明）。Go

Changes from A Revision (June 2011) to B Revision

  • Changed name of VCC to VBUSOUT throughout the entire document.Go
  • Deleted row from Device Operation table.Go
  • Added Eye Diagrams to Typical Characteristics section.Go

5 Pin Configuration and Functions

DSQ Package
10-Pin WSON
Top Side/See-Through View
TPD4S014 po_lvsau0.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
VBUSOUT 1, 2 Power Output Connect to PCB internal PCB plane
EN 3 IO Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the switch.
ACK 4 I Open-Drain Adapter-Voltage Indicator Output. ACK is driven low after the VIN voltage is stable between UVLO and OVLO for 17 ms (typ). Connect a pullup resistor from ACK to the logic I/O voltage of the host system.
ID 5 IO ESD-protected line
D– 6 IO ESD-protected line
D+ 7 IO ESD-protected line
GND 8 Ground Ground
VBUS 9, 10 USB Input Power Connector Side of VBUS
Central PAD Central PAD Heat Sink Electrically disconnected. Use as heat sink. Connect to GND plane via large PCB PAD

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Maximum junction temperature –40 150 °C
Max Voltage on VBUS –0.5 30 V
Continuous current through nFET 2.6 A
Continuous current through ACK –50 50 mA
Max Current through D+, D–, ID, VBUS ESD clamps 50 mA
Max voltage on EN, ACK, D+, D-, ID, VBUSOUT 6 V
Storage temperature, Tstg –65 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
IEC 61000-4-2 Contact Discharge D+, D–, ID, VBUS pins ±1500
IEC 61000-4-2 Air-gap Discharge D+, D–, ID, VBUS pins ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TA Operating free-air temperature –40 85 °C
VI Input voltage VBUSOUT –0.1 5.5 V
VBUS –0.1 5.5
EN –0.1 5.5
ACK –0.1 5.5
D+, D-, ID, –0.1 5.5
IVBUS VBUS continuous current(1) VBUSOUT 2.0 A
CVBUS Capacitance on VBUS VBUS Pin 10 µF
CVBUSOUT Capacitance on VBUSOUT VBUSOUT Pin 10 µF
RACK Pullup resistor on ACK ACK Pin 10 kΩ
(1) IVBUS Max value is dependent on ambient temperature. See Thermal Shutdown section.

6.4 Thermal Information

THERMAL METRIC(1) TPD4S014 UNIT
DSQ (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 70.3 °C/W
RθJCtop Junction-to-case (top) thermal resistance 46.3 °C/W
RθJB Junction-to-board thermal resistance 33.8 °C/W
ψJT Junction-to-top characterization parameter 2.9 °C/W
ψJB Junction-to-board characterization parameter 33.5 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 16.3 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics, EN, ACK, D+, D–, ID Pins

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage EN Load current = 50 µA 1 V
VIL Low-level input voltage EN Load current = 50 µA 0.5 V
ILEAK Input Leakage Current EN, D+, D–, ID VIO = 3.3 V 1 µA
VOL Low-level output voltage ACK IOL = 2 mA 0.1 V
VD Diode forward Voltage D+, D–, ID pins; lower clamp diode IO = 8 mA 0.95 V
ΔCIO Differential Capacitance between the D+, D– lines 0.03 pF
CIO Capacitance to GND for the D+, D– lines ƒ = 1 MHz 1.6 pF
CIO-ID Capacitance to GND for the ID line 19 pF
VR Reverse stand-off voltage of D+, D- and ID pins 5 V
VBR Breakdown voltage D+, D–, ID pins IBR = 1 mA 6 V
VBR VBUS Breakdown voltage on VBUS IBR = 1 mA 28 V
RDYN Dynamic on resistance D+, D–, ID clamps II = 1 A 1 Ω

6.6 Electrical Characteristics OVP Circuits

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT UNDERVOLTAGE LOCKOUT
VUVLO+ Under-voltage lock-out, input power detected threshold rising VBUS increasing from 0 V to 5 V, No load on OUT pin 2.65 2.8 3 V
VUVLO– Under-voltage lock-out, input power detected threshold falling VBUS decreasing from 5 V to 0 V, No load on OUT pin 2.25 2.44 2.7 V
VHYS-UVLO Hysteresis on UVLO Δ of VUVLO+ and VUVLO– 150 360 550 mV
INPUT TO OUTPUT CHARACTERISTICS
RDS_VBUSSWITCH VBUS switch resistance VBUS = 5 V, IOUT = 500 mA 151 200 mΩ
tON Turn-ON time VBUS increasing from 2.8 V to 4.75 V, EN = 0 V, RL = 36 Ω, CL = 10 uF 16 17.4 22 ms
tOFF Turn-OFF time VBUS decreasing from 2.44 V to 0.5 V, EN = 0V, RL = 36 Ω, CL = 10 uF 8 µs
INPUT OVERVOLTAGE PROTECTION (OVP)
VOVP+ Input over –voltage protection threshold rising VBUS VBUS increasing from 5 V to 7 V, No Load 5.9 6.15 6.45 V
VOVP- Input over –voltage protection threshold falling VBUS VBUS decreasing from 7 V to 5 V, No Load 5.75 5.98 6.24 V
VHYS-OVP Hysteresis on OVP VBUS Δ of VOVP+ and VOVP– 25 100 275 mV
td(OVP) Over voltage delay VBUS RL = 36 Ω, CL = 10 µF; VBUS increasing from 5 V to 7 V 11 µs
tREC Recovery time from input over voltage condition VBUS RL = 36 Ω, CL = 10 µF; VBUS decreasing from 7 V to 5 V 8 10.5 ms

6.7 Supply Current Consumption

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVBUS VBUS Operating Current Consumption No load on VBUS_OUT pin, VBUS = 5 V,
EN = 0 V		 147.6 160 µA
IVBUS_OFF VBUS Operating Current Consumption No load on VBUS_OUT pin, VBUS = 5 V,
EN = 5 V		 111.8 120 µA

6.8 Thermal Shutdown Feature

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSHDN Thermal Shutdown 144 °C
TSHDN-HYS Thermal-Shutdown Hysteresis 23 °C

6.9 Typical Characteristics

TPD4S014 typ_char1_lvsau0.png Figure 1. IEC61000-4-2 -8-kV Contact Waveform
TPD4S014 typ_char3_lvsau0.png
Figure 3. Capacitance Variation With Voltage
TPD4S014 typ_char5_lvsau0.png
Figure 5. Max Pulse Current Through Switch vs Pulse Duration
TPD4S014 typ_char7_lvsau0.png
Figure 7. OVP Threshold Variation With Temperature
TPD4S014 typ_char9_lvsau0.png
.
Figure 9. Device Turn on Characteristics
TPD4S014 typ_char11_lvsau0.png
Figure 11. Device Turn OFF Characteristics (Overvoltage)
TPD4S014 typ_char2_lvsau0.png
Figure 2. IEC61000-4-2 +8-kV Contact Waveform
TPD4S014 typ_char4_lvsau0.png
Figure 4. Variation of On Resistance with Ambient Temperature
TPD4S014 typ_char6_lvsau0.png
Figure 6. UVLO Threshold Variation With Temperature
TPD4S014 typ_char8_lvsau0.png
Figure 8. Start Up Inrush Current Characteristics
TPD4S014 typ_char10_lvsau0.png
Figure 10. Device Turn OFF Characteristics (Undervoltage)

7 Detailed Description

7.1 Overview

The TPD4S014 provides a single-chip protection solution for USB charger interfaces. The VBUS line is tolerant up to 28 V DC. A Low RON nFET switch is used to disconnect the downstream circuits in case of a fault condition. At power-up, when the voltage on VBUS is rising, the switch will close 17 ms after the input crosses the under voltage threshold, thereby making power available to the downstream circuits. The TPD4S014 also has an ACK output, which de-asserts to alert the system a fault has occurred. The TPD4S014 offers 4 channel ESD clamps for D+, D-, ID, and VBUS pins that provide IEC61000-4-2 level 4 ESD protection. This eliminates the need for external TVS clamp circuits in the application.

7.2 Functional Block Diagram

TPD4S014 cir_sch_lvsau0.gif

7.3 Feature Description

7.3.1 Input Voltage Protection at VBUS up to 28 V DC

When the input voltage rises above VOVP, or drops below the VUVLO, the internal VBUS switch is turned off, removing power to the application. The ACK signal is de-asserted when a fault condition is detected. If the fault was an over voltage event, the VBUS nFET switch turns on 8 ms (tREC) after the input voltage returns below VOVP – VHYS_OVP and remains above VUVLO. If the fault was an under voltage event, the switch turns on 17 ms after the voltage returns above VUVLO+ (similar to start up). When the switch turns on, the ACK is asserted once again.

7.3.2 Low RON nFET Switch

The nFET switch has a total on resistance (RON) of 151 mΩ. This equates to a voltage drop of 302 mV when charging at the maximum 2.0 A current level. Such low RON helps provide maximum potential to the system as provided by an external charger.

7.3.3 ESD Performance D+/D–/ID/VBUS Pins

The D+, D–, ID, and VBUS pins can withstand ESD events up to ±15-kV contact and air-gap. An ESD clamp diverts the current to ground.

7.3.4 Overvoltage and Undervoltage Lockout Features

The over voltage and under voltage lockout feature ensures that if there is a fault condition at the VBUS line, the TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. Due to the body diode of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.

7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate

The D+/D– ESD protection pins have low capacitance so there is no significant impact to the signal integrity of the USB 2.0 Hi-Speed data rate.

7.3.6 Start-up Delay

Upon startup, TPD4S014 has a built in startup delay. An internal oscillator controls a charge pump to control the turn-on delay (tON) of the internal nFET switch. The internal oscillator controls the timers that enable the turn-on of the charge pump and sets the state of the open-drain ACK output. If VBUS < VUVLO or if VBUS > VOVLO, the internal oscillator remains off, thus disabling the charge pump. At any time, if VBUS drops below VUVLO or rises above VOVLO, ACK is released and the nFET switch is disabled.

7.3.7 OVP Glitch Immunity

A 17 ms deglitch time has been introduced into the turn on sequence to ensure that the input supply has stabilized before turning the nFET switch ON. Noise on the VBUS line could turn ON the nFET switch when the fault condition is still active. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. Such a glitch protection circuitry is also introduced in the turn off sequence in order to prevent the switch from turning off for voltage transients. The glitch protection circuitry integrates the glitch over time, allowing the OVP circuitry to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions.

7.3.8 Integrated Input Enable and Status Output Signal

External control of the nFET switch is provided by an active low EN pin. An ACK pin provides output logic to acknowledge VBUS is between UVLO and OVP by asserting low.

7.3.9 Thermal Shutdown

When the device is ON, current flowing through the device will cause the device to heat up. Overheating can lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into the device. Whenever the junction temperature exceeds 145ºC, the switch will turn off, thereby limiting the temperature. The ACK signal will be asserted for an over temperature event. Once the device cools down to below 120ºC the ACK signal will be de-asserted, and the switch will turn on if the EN is active and the VBUS voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kick-in unless the die temperature reaches 145ºC, it is generally recommended that care is taken to keep the junction temperature below 125 ºC. Operation of the device above 125 ºC for extended periods of time can affect the long-term reliability of the part.

The junction temperature of the device can be calculated using below formula:

Equation 1. TPD4S014 Eqn1_lvsau0.gif

where

  • TJ = Junction temperature
  • Ta = Ambient temperature
  • θJA = Thermal resistance
  • PD = Power dissipated in device
Equation 2. TPD4S014 Eqn2_lvsau0.gif

where

  • I = Current through device
RON = Max on resistance of device

Example

At 2-A continuous current power dissipation is given by:

TPD4S014 Eqn3_lvsau0.gif

If the ambient temperature is about 60°C the junction temperature will be:

TPD4S014 Eqn4_lvsau0.gif

This implies that, at an ambient temperature of 60ºC, TPD4S014 can pass a continuous 2 A without sustaining damage. Conversely, the above calculation can also be used to calculate the total continuous current the TPD4S014 can handle at any given temperature.

7.4 Device Functional Modes

Table 1 is the function table for TPD4S014.

Table 1. Function Table

OTP UVLO OVLO EN SW ACK
X H X X OFF H
X X H X OFF H
L L L H OFF L
L L L L ON L
H X X X OFF H
OTP = Over temperature protection circuit active
UVLO = Under voltage lock-out circuit active
OVLO = Over voltage lock-out circuit active
SW = Load switch
CP = Charge pump
X = Don’t Care
H = True
L = False

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD4S014 is a single-chip solution for USB charger port protection. This device offers low capacitance TVS type ESD clamps for the D+, D–, and standard capacitance for the ID pin. On the VBUS pin, this device can handle over voltage protection up to 28 V. The over voltage lockout feature ensures that if there is a fault condition at the VBUS line TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. In order to let the voltage stabilize before closing the switch there is a 17 ms turn on delay after VBUS crosses the UVLO threshold. This function acts as a de-glitch which prevents unnecessary switching if there is any ringing on the line during connection. Due to the body diode of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.

8.2 Typical Applications

8.2.1 For Non-OTG USB Systems

TPD4S014 app_dia_lvsau0.gif Figure 12. Non-OTG Schematic

8.2.1.1 Design Requirements

Table 2 shows the design parameters.

Table 2. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Signal range on VBUS 3.3 V – 5.9 V
Signal range on VBUSOUT 3.9 V – 5.9 V
Signal range on D+/D– and ID 0 V – 5 V
Drive EN low (enabled) 0 V – 0.5 V
Drive EN high (disabled) 1 V – 6 V

8.2.1.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

  • VBUS voltage range
  • Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins

8.2.1.3 Application Curves

TPD4S014 typ_eye1_lvsau0.png Figure 13. Eye Diagram With No EVM and No IC, Full USB2.0 Speed at 480 Mbps
TPD4S014 typ_eye3_lvsau0.png Figure 15. Eye Diagram With EVM and IC, Full USB2.0 Speed at 480 Mbps
TPD4S014 typ_eye2_lvsau0.png Figure 14. Eye Diagram With EVM, No IC, Full USB2.0 Speed at 480 Mbps

8.2.2 For OTG USB Systems

TPD4S014 app2_dia_lvsau0.gif Figure 16. OTG Schematic

8.2.2.1 Design Requirements

Table 3 shows the design parameters.

Table 3. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Signal range on VBUS 3.3 V – 5.9 V
Signal range on VBUSOUT 3.9 V – 5.9 V
Signal range on D+/D– and ID 0 V – 5 V
Drive EN low (enabled) 0 V – 0.5 V
Drive EN high (disabled) 1 V – 6 V

8.2.2.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

  • VBUS voltage range
  • Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins
  • OTG power supply output voltage range

8.2.2.3 Application Curves

Refer to Application Curves in the previous section.

9 Power Supply Recommendations

TPD4S014 Is designed to receive power from a USB 3.0 (or lower) VBUS source. It can operate normally (nFET ON) between 3.0 V and 5.9 V. Thus, the power supply (with a ripple of VRIPPLE) requirement for TPD4S014 to be able to switch the nFET ON is between 3.0 V + VRIPPLE and 5.9 V – VRIPPLE.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale