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  • ADS42xx 双通道、14 位/12 位、160MSPS/125MSPS/65MSPS、超低功耗 ADC

    • ZHCS114E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

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  • ADS42xx 双通道、14 位/12 位、160MSPS/125MSPS/65MSPS、超低功耗 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 支持资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information
  12. 重要声明
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DATA SHEET

ADS42xx 双通道、14 位/12 位、160MSPS/125MSPS/65MSPS、超低功耗 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 超低功耗，采用 1.8V 单电源供电，CMOS 输出：
    • 65MSPS 时的总功耗为 183mW
    • 125MSPS 时的总功耗为 277mW
    • 160MSPS 时的总功耗为 332mW
  • 高动态性能：
    • 170MHz 时的无杂散动态范围 (SFDR) 为 88dBc
    • 170MHz 时的信噪比 (SNR) 为 71.4dBFS
  • 串扰：185MHz 时大于 90dB
  • 高达 6dB 的可编程增益支持 SNR/SFDR 权衡
  • 直流偏移校正
  • 输出接口选项：
    • 1.8V 并行 CMOS 接口
    • 支持可编程摆幅的双倍数据速率 (DDR) 低压差分信令 (LVDS)：
      • 标准摆幅：350mV
      • 低摆幅：200mV
  • 支持低至
    200mVPP 的输入时钟幅值
  • 封装：VQFN-64 (9.00mm × 9.00mm)

2 应用

  • 无线通信基础设施
  • 软件定义的无线电
  • 功率放大器线性化

3 说明

ADS424x 和 ADS422x 系列器件是 ADS42xx 超低功耗系列双通道 14 位/12 位模数转换器 (ADC) 的低速变型产品。该器件凭借创新设计技术实现了高动态性能，并且采用 1.8V 电源供电运行，功耗极低。该拓扑使 ADS424x/422x 非常适合多载波、大带宽通信应用。

封装信息
器件型号封装(1)封装尺寸（标称值）
ADS4222VQFN (64)9.00mm x 9.00mm
ADS4225
ADS4226
ADS4242
ADS4245
ADS4246
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
GUID-52C243F8-1B80-40A9-AF61-56B6565B4128-low.gifADS4222/25/26/42/45/46 方框图

4 Revision History

Changes from Revision D (December 2015) to Revision E (February 2023)

  • 将“器件信息”表更改为封装信息 表Go
  • 将封装信息 表中的 VQFN (48) 更改为 VQFN (64)Go
  • Changed the Pin Configuration and Functions. Updated the Pin Functions tables and pinout imagesGo

Changes from Revision C (March 2011) to Revision D (December 2015)

  • 添加了 ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from Revision B (May 2011) to Revision C (March 2011)

  • 将器件状态从“混合状态”更改为“量产数据”Go
  • 更改了第一个“特性”要点的 125MSPS 子要点Go
  • 更改了第二个“特性”要点的子要点Go
  • Changed description of pin 64 in Pin Descriptions: LVDS Mode tableGo
  • Changed description of pin 64 in Pin Descriptions: CMOS Mode tableGo
  • Changed ADS4246 fIN = 170 MHz Worst spur typical spcification in the ADS4246/ADS4245/ADS4242 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 fIN = 70 MHz SNR, SINAD, SFDR, THD, HD2, HD3, and Worst spur minimum and typical spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 DNL minimum and maximum spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Added ADS4225/ADS4222 INL maximum spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics tableGo
  • Changed ADS4242/ADS4222 Power Supply, Digital power LVDS interface typical specification in Electrical Characteristics: General tableGo
  • Changed ADS4245/ADS4225 Power Supply, Digital power CMOS interface typical specification in Electrical Characteristics: General tableGo
  • Moved High-Performance Modes into separate tableGo
  • Changed description of READOUT disabled in Serial Register Readout sectionGo
  • Updated Figure 8-18 Go
  • Changed READOUT desciption in Register Address 00h sectionGo
  • Changed CLKOUT FALL POSN and CLKOUT RISE POSN description in Register Address 42h sectionGo

Changes from Revision A (May 2011) to Revision B (May 2011)

  • 更改了第一个“特性”要点的子要点Go
  • Updated description of NC pin in LVDS Pin Descriptions tableGo
  • Updated description of NC pin in CMOS Pin Descriptions tableGo
  • Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 table Go
  • Deleted INL minimum specifications from Electrical Characteristics: ADS4246/ADS4245/ADS4242 tableGo
  • Changed INL maximum specifications in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 tableGo
  • Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 table Go
  • Changed ADS4226 INL maximum specification in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 tableGo
  • Changed Power Supply, IDRVDD and Digital power CMOS interface rows in the Electrical Characteristics: General tableGo
  • Updated Figure 7-16 Go
  • Updated Figure 7-18 Go
  • Updated Figure 7-37 and Figure 7-38 Go
  • Updated Figure 7-39 and Figure 7-40 Go
  • Updated Figure 7-58 and Figure 7-59 Go
  • Updated Figure 7-60 and Figure 7-61 Go
  • Updated Figure 7-79 and Figure 7-80 Go
  • Updated Figure 7-81 and Figure 7-82 Go
  • Updated Figure 7-96 Go
  • Updated Figure 7-97 and SBAS533graph8650Go
  • Updated Figure 7-115 Go
  • Updated Figure 7-127 Go
  • Changed title of Figure 7-128 Go
  • Updated ADS424x/422x Family Pins section in Table 8-1 Go
  • Changed 111110 and 001111 LVDS SWING description in Register Address 01hGo

5 说明（续）

ADS424x/422x 具有精细增益选项，可用于提升在较低满量程输出范围内的 SFDR 性能。这些器件包括一个 DC 失调校正环路，可用来消除 ADC 偏移。双倍数据速率 (DDR) LVDS 与并行 CMOS 数字输出接口都采用紧凑型 VQFN-64 封装。

这些器件包含内部基准，并消除了传统基准引脚与相关去耦电容。所有器件都在工业温度范围（–40°C 至 85°C）内额定运行。

表 5-1 ADS424x、422x 系列比较
器件系列(1) 250MSPS 160MSPS 125 MSPS 65 MSPS
ADS424x
14 位系列		 ADS4249 ADS4246 ADS4245 ADS4242
ADS422x
12 位系列		 ADS4229 ADS4226 ADS4225 ADS4222
(1) 了解 表 8-1从 ADS62P49 系列升级的更多详情。

6 Pin Configuration and Functions

Pin Functions – LVDS Mode

GUID-20230214-CA0I-L1JD-XTLN-SFXZWJXHKFVK-low.svg Figure 6-1 ADS4246, ADS4245, and ADS4242
RGC Package
64-Pin VQFN With Exposed Thermal Pad
LVDS Mode (Top View)
GUID-20230214-CA0I-1CDS-WNQ4-DGN7DM2J0W9L-low.svg Figure 6-2 ADS4226, ADS4225, and ADS4222
RGC Package
64-Pin VQFN With Exposed Thermal Pad
LVDS Mode (Top View)
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME ADS4246, 45,42 ADS4226, 25, 22
AGND 17, 18, 21, 24, 27, 28, 31, 32 17, 18, 21, 24, 27, 28, 31, 32 Input Analog ground
AVDD 16, 22, 33, 34 16, 22, 33, 34 Input Analog power supply
CLKM 26 26 Input Differential clock negative input
CLKOUTM 56 56 Output Differential output clock, complement
CLKOUTP 57 57 Output Differential output clock, true
CLKP 25 25 Input Differential clock positive input
CTRL1 35 35 Input Digital control input pins. Together, they control the various power-down modes.
CTRL2 36 36 Input Digital control input pins. Together, they control the various power-down modes.
CTRL3 37 37 Input Digital control input pins. Together, they control the various power-down modes.
DA0P 41 43 Output Channel A differential output data pair, D0 and D1 multiplexed
DA0M 40 42 Output Channel A differential output data pair, D0 and D1 multiplexed
DA2P 43 45 Output Channel A differential output data D2 and D3 multiplexed
DA2M 42 44 Output Channel A differential output data D2 and D3 multiplexed
DA4P 45 47 Output Channel A differential output data D4 and D5 multiplexed
DA4M 44 46 Output Channel A differential output data D4 and D5 multiplexed
DA6P 47 51 Output Channel A differential output data D6 and D7 multiplexed
DA6M 46 50 Output Channel A differential output data D6 and D7 multiplexed
DA8P 51 53 Output Channel A differential output data D8 and D9 multiplexed
DA8M 50 52 Output Channel A differential output data D8 and D9 multiplexed
DA10P 53 55 Output Channel A differential output data D10 and D11 multiplexed
DA10M 52 54 Output Channel A differential output data D10 and D11 multiplexed
DA12M 54 -- Output Channel A differential output data D12 and D13 multiplexed (ADS424x only)
DA12P 55 -- Output Channel A differential output data D12 and D13 multiplexed (ADS424x only)
DB0P 61 63 Output Channel B differential output data pair, D0 and D1 multiplexed
DB0M 60 62 Output Channel B differential output data pair, D0 and D1 multiplexed
DB2P 63 3 Output Channel B differential output data D2 and D3 multiplexed
DB2M 62 2 Output Channel B differential output data D2 and D3 multiplexed
DB4P 3 5 Output Channel B differential output data D4 and D5 multiplexed
DB4M 2 4 Output Channel B differential output data D4 and D5 multiplexed
DB6P 5 7 Output Channel B differential output data D6 and D7 multiplexed
DB6M 4 6 Output Channel B differential output data D6 and D7 multiplexed
DB8P 7 9 Output Channel B differential output data D8 and D9 multiplexed
DB8M 6 8 Output Channel B differential output data D8 and D9 multiplexed
DB10P 9 11 Output Channel B differential output data D10 and D11 multiplexed
DB10M 8 10 Output Channel B differential output data D10 and D11 multiplexed
DB12P 11 -- Output Channel B differential output data D12 and D13 multiplexed (ADS424x only)
DB12M 10 -- Output Channel B differential output data D12 and D13 multiplexed (ADS424x only)
DRGND 49, PAD 49, PAD Input Output buffer ground. The Thermal PAD is connected to DRGND
DRVDD 1, 48 1, 48 Input Output buffer supply
INM_A 30 30 Input Differential analog negative input, channel A
INM_B 20 20 Input Differential analog negative input, channel B
INP_A 29 29 Input Differential analog positive input, channel A
INP_B 19 19 Input Differential analog positive input, channel B
NC 38, 39, 58, 59
Refer to Figure 7-28, Figure 7-29, and Figure 7-45		 38, 39, 40, 41, 58, 59, 60, 61 — Do not connect, must be floated
RESET 12 12 Input Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pulldown resistor.
SCLK 13 13 Input This pin functions as a serial interface clock input when RESET is low. It controls the low-speed mode selection when RESET is tied high; see Table 8-6 for detailed information. This pin has an internal 150-kΩ pulldown resistor.
SDATA 14 14 Input Serial interface data input; this pin has an internal 150-kΩ pulldown resistor.
SDOUT 64 64 Output This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is in high-impedance state.
SEN 15 15 Input This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 8-7 for detailed information. This pin has an internal 150-kΩ pullup resistor to AVDD.
VCM 23 23 Output This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins

 
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