ADS41xx 14、12 位、65MSPS 或 125MSPS 超低功耗 ADC

Table 2. Full-Scale Range Across Gains

Table 3. Time Constant of Offset Correction Loop

8.3.4.1 Power-Down Global

In this mode, the entire device (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of approximately 10 mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100 µs. To enter the global power-down mode, set the PDN GLOBAL register bit.

8.3.4.2 Standby

In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5 µs. The total power dissipation in standby mode is approximately 130 mW at 125 MSPS. To enter the standby mode, set the STBY register bit.

8.3.4.3 Output Buffer Disable

The output buffers can be disabled and put in a high-impedance state; wake-up time from this mode is fast, approximately 100 ns. Disabling the output buffers can be controlled using the PDN OBUF register bit or using the OE pin.

8.3.4.4 Input Clock Stop

In addition, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is approximately 80 mW.

8.4.1.1 Output Interface

Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. These options can be selected using the LVDS CMOS serial interface register bit or using the DFS pin.

8.4.1.2 DDR LVDS Outputs

In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 97 and Figure 98.

Figure 97. ADS412x LVDS Data Outputs

Figure 98. ADS414x LVDS Data Outputs

Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 99.

Figure 99. DDR LVDS Interface

8.4.1.3 LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 100. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination.

The V_DIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, the output impedance of buffer helps improve signal integrity.

Use the default buffer strength to match 100-Ω external termination (R_OUT = 100 Ω). To match with a 50-Ω external termination, set the LVDS STRENGTH bit (R_OUT = 50 Ω).

Figure 100. LVDS Buffer Equivalent Circuit

8.4.1.4 Parallel CMOS Interface

In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 101 depicts the CMOS output interface.

Figure 101. CMOS Output Interface

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window. TI recommends using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load capacitance, as shown in Figure 102.

Figure 102. Using the CMOS Data Outputs

8.4.1.5 CMOS Interface Power Dissipation

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current is determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal.

Figure 86 details the current across sampling frequencies at 2-MHz analog input frequency.

Table 5. DFS: Analog Control Pin

Table 6. OE: Digital Control Pin

Table 7. SDATA: Digital Control Pin

8.5.2.1 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways:

1. Either through hardware reset by applying a high pulse on RESET pin (of durations greater than 10 ns), as shown in Figure 5; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

Table 8. Serial Interface Register Map⁽¹⁾

Table 1. Register Address 00h (Default = 00h)

Table 2. Register Address 01h (Default = 00h)

Table 3. Register Address 03h (Default = 00h)

Table 4. Register Address 25h (Default = 00h)

Table 5. Register Address 26h (Default = 00h)

Table 6. Register Address 3Dh (Default = 00h)

Table 7. Register Address 3Fh (Default = 00h)

Table 8. Register Address 40h (Default = 00h)

Table 9. Register Address 41h (Default = 00h)

Table 10. Register Address 42h (Default = 00h)

Table 11. Register Address 43h (Default = 00h)

Table 12. Register Address 4Ah (Default = 00h)

Table 13. Register Address BFh (Default = 00h)

Table 14. Register Address CFh (Default = 00h)

Table 15. Register Address DFh (Default = 00h)

9.1.1.1 Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. Low impedance (less than 50 Ω) must be present for the common-mode switching currents. This impedance can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM).

Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support the sampling glitches.

In the ADS412x and ADS414x, the R-C component values are optimized when supporting high input bandwidth (550 MHz). However, in applications where very high input frequency support is not required, filtering of the glitches can be improved further with an external R-C-R filter; see Figure 108 and Figure 109).

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. When designing the drive circuit, the ADC impedance must be considered. Figure 106 and Figure 107 show the impedance (Z_IN = R_IN || C_IN) looking into the ADC input pins.

Figure 106. ADC Analog Input Resistance (R_IN) Across Frequency

Figure 107. ADC Analog Input Capacitance (C_IN) Across Frequency

9.1.1.2 Driving Circuit

Two example driving circuit configurations are shown in Figure 108 and Figure 109—one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 108, an external R-C-R filter with 3.3 pF is used to help absorb sampling glitches. The R-C-R filter limits the bandwidth of the drive circuit, making the drive circuit suitable for low input frequencies (up to 250 MHz). Transformers such as ADT1-1WT or WBC1-1 can be used up to 250 MHz.

For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5 Ω to 10 Ω), this drive circuit provides higher bandwidth to support frequencies up to 500 MHz (as shown in Figure 109). A transmission line transformer such as ADTL2-18 can be used.

Note that both the drive circuits have been terminated by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 0.95-V common-mode (VCM) from the device. This termination allows the analog inputs to be biased around the required common-mode voltage.

Figure 108. Drive Circuit With Low Bandwidth (for Low Input Frequencies)

Figure 109. Drive Circuit With High Bandwidth (for High Input Frequencies)

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 108 and Figure 109. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance).

Figure 108 and Figure 109 use 1:1 transformers with a 50-Ω source. As explained in the Drive Circuit Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches. With a 1:4 transformer, the source impedance is 200 Ω. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).

In almost all cases, either a band-pass or low-pass filter is needed to obtain the desired dynamic performance, as shown in Figure 110. Such a filter presents low source impedance at the high frequencies corresponding to the sampling glitch and helps avoid the performance loss with the high source impedance.

Figure 110. Drive Circuit With 1:4 Transformer

9.1.1.3 Input Common-Mode

To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a common-mode current of approximately 0.6 µA per MSPS of clock frequency.

9.1.4.1 ADS412x (12-Bit Device)

fS = 3 MSPS, fIN = 4 MHz, SNR = 71 dBFS, SFDR = 94 dBc, SINAD = 70.9 dBFS, THD = 91 dBc

Figure 114. FFT for 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 12 MHz, SNR = 70.5 dBFS, SFDR = 89 dBc, SINAD = 70.4 dBFS, THD = 87 dBc

Figure 116. FFT for 5-MSPS Sampling Speed

fS = 5 MSPS, fIN = 3 MHz, SNR = 70.9 dBFS, SFDR = 89 dBc, SINAD = 70.8 dBFS, THD = 87 dBc

Figure 115. FFT for 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 86 dBc

Figure 117. FFT for 10-MSPS Sampling Speed

fS = 10 MSPS, fIN = 12 MHz, SNR = 70.9 dBFS, SFDR = 88 dBc, SINAD = 70.8 dBFS, THD = 86 dBc

Figure 118. FFT for 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 12 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 87 dBc

Figure 120. FFT for 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 12 MHz, SNR = 71 dBFS, SFDR = 89 dBc, SINAD = 71.9 dBFS, THD = 87 dBc

Figure 122. FFT for 50-MSPS Sampling Speed

fS = 3 MSPS, fIN = 4 MHz

Figure 124. Differential Nonlinearity at 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 3 MHz

Figure 126. Differential Non-linearity at 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz

Figure 128. Differential Nonlinearity at 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 3 MHz

Figure 130. Differential Nonlinearity at 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz

Figure 132. Differential Nonlinearity at 50-MSPS Sampling Speed

fIN = 3 MHz

Figure 134. Performance Across Sampling Speed

fS = 20 MSPS, fIN = 3 MHz, SNR = 71.1 dBFS, SFDR = 89 dBc, SINAD = 71 dBFS, THD = 87 dBc

Figure 119. FFT for 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz, SNR = 71 dBFS, SFDR = 90 dBc, SINAD = 70.9 dBFS, THD = 87 dBc

Figure 121. FFT for 50-MSPS Sampling Speed

fS = 3 MSPS, fIN = 4 MHz

Figure 123. Integral Nonlinearity at 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 3 MHz

Figure 125. Integral Nonlinearity at 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz

Figure 127. Integral Nonlinearity at 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 3 MHz

Figure 129. Integral Nonlinearity at 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz

Figure 131. Integral Nonlinearity at 50-MSPS Sampling Speed

Figure 133. INL Histogram Across Sampling Speed

fIN = 12 MHz

Figure 135. Performance Across Sampling speed

9.1.4.2 ADS414x (14-Bit Device)

fS = 3 MSPS, fIN = 4 MHz, SNR = 73.8 dBFS, SFDR = 97 dBc, SINAD = 73.7 dBFS, THD = 90 dBc

Figure 136. FFT for 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 12 MHz, SNR = 73 dBFS, SFDR = 89 dBc, SINAD = 72.9 dBFS, THD = 87 dBc

Figure 138. FFT for 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 12 MHz, SNR = 73.6 dBFS, SFDR = 88 dBc, SINAD = 73.4 dBFS, THD = 86 dBc

Figure 140. FFT for 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 12 MHz, SNR = 73.9 dBFS, SFDR = 89 dBc, SINAD = 73.7 dBFS, THD = 87 dBc

Figure 142. FFT for 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 12 MHz, SNR = 73.8 dBFS, SFDR = 88 dBc, SINAD = 73.6 dBFS, THD = 86 dBc

Figure 144. FFT for 50-MSPS Sampling Speed

fS = 3 MSPS, fIN = 4 MHz

Figure 146. Differential Nonlinearity at 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 3 MHz

Figure 148. Differential Nonlinearity at 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz

Figure 150. Differential Nonlinearity at 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 3 MHz

Figure 152. Differential Nonlinearity at 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz

Figure 154. Differential Nonlinearity at 50-MSPS Sampling Speed

RMS = 1.1523 LSB

Figure 156. Output Noise Histogram (With Inputs shorted to VCM) at 5-MSPS Sampling Speed

RMS = 1.104 LSB

Figure 158. Output Noise Histogram (With Inputs shorted to VCM) at 20-MSPS Sampling Speed

fIN = 3 MHz

Figure 160. Performance Across Sampling Speed

fS = 5 MSPS, fIN = 3 MHz, SNR = 73.8 dBFS, SFDR = 90 dBc, SINAD = 73.7 dBFS, THD = 87 dBc

Figure 137. FFT for 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz, SNR = 73.9 dBFS, SFDR = 88 dBc, SINAD = 73.7 dBFS, THD = 86 dBc

Figure 139. FFT for 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 3 MHz, SNR = 74 dBFS, SFDR = 89 dBc, SINAD = 73.8 dBFS, THD = 87 dBc

Figure 141. FFT for 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz, SNR = 73.8 dBFS, SFDR = 89 dBc, SINAD = 73.6 dBFS, THD = 86 dBc

Figure 143. FFT for 50-MSPS Sampling Speed

fS = 3 MSPS, fIN = 4 MHz

Figure 145. Integral Nonlinearity at 3-MSPS Sampling Speed

fS = 5 MSPS, fIN = 3 MHz

Figure 147. Integral Nonlinearity at 5-MSPS Sampling Speed

fS = 10 MSPS, fIN = 3 MHz

Figure 149. Integral Nonlinearity at 10-MSPS Sampling Speed

fS = 20 MSPS, fIN = 3 MHz

Figure 151. Integral Nonlinearity at 20-MSPS Sampling Speed

fS = 50 MSPS, fIN = 3 MHz

Figure 153. Integral Nonlinearity at 50-MSPS Sampling Speed

Figure 155. INL Histogram Across Sampling Speed

RMS = 1.080 LSB

Figure 157. Output Noise Histogram (With Inputs shorted to VCM) at 10-MSPS Sampling Speed

RMS = 1.072 LSB

Figure 159. Output Noise Histogram (With Inputs shorted to VCM) at 50-MSPS Sampling Speed

fIN = 12 MHz

Figure 161. Performance Across Sampling Speed

9.1.4.3 Power Consumption at Low Sampling Rates

Figure 162 shows typical power consumption at lower sampling rates on each supply.

Figure 162. Power vs Sample Rate

9.1.4.4 Output Timing at Low Sampling Rates

Table 9 describes the set-up and hold times for the digital outputs of the ADS41xx with respect to the output clock at low sampling rates.

Table 10. Example Design Requirements for the ADS412x and ADS414x

9.2.2.1 Analog Input

The analog input of the ADS412x and ADS414x is typically driven by a fully differential amplifier. The amplifier must have sufficient bandwidth for the frequencies of interest. The noise and distortion performance of the amplifier affect the combined performance of the ADC and amplifier. The amplifier is often ac-coupled to the ADC to allow both the amplifier and ADC to operate at the optimal common-mode voltages. The amplifier can be dc-coupled to the ADC if required. An alternate approach is to drive the ADC using transformers. DC coupling cannot be used with the transformer approach.

9.2.2.2 Clock Driver

The ADS412x and ADS414x must be driven by a high-performance clock driver such as a clock jitter cleaner. The clock must have low noise to maintain optimal performance. LVPECL is the most common clocking interface, but LVDS and LVCMOS can be used as well. TI does not advise driving the clock input from an FPGA unless the noise degradation can be tolerated, such as for input signals near dc where the clock noise impact is minimal.

9.2.2.3 Digital Interface

The ADS412x and ADS414x supports both LVDS and CMOS interfaces. The LVDS interface must be used for best performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the FPGA without any additional components. When using CMOS outputs resistors must be placed in series with the outputs to reduce the output current spikes to limit the performance degradation. The resistors must be large enough to limit current spikes but not so large as to significantly distort the digital output waveform. An external CMOS buffer must be used when driving distances greater than a few inches to reduce ground bounce within the ADC.