SPRZ454A February 2018 – February 2021 TDA2P-ABZ , TDA2P-ACD
HDMI Transmitter is Marginal to Source Eye Mask Requirements Above 177MHz
Low
When running the HDMI interface at greater than 177MHz pixel clock rate (e.g., 1920x1440@60fps, 8-bit color), the source eye diagram CK - DATA is marginal to the HDMI specification source eye mask requirements. The source eye diagram CK - DATA is marginal at the datasheet target of 185.6MHz (e.g., 1920x1080 @ 60fps, 10-bit color).
When running the HDMI interface at greater than 177MHz pixel clock rate, the receiver input signal requirements should be evaluated to determine whether the HDMI signal meets the input signal requirements of the receiving device or the TMDS input characteristics defined in the HDMI bus specification. If the input signal requirements of the receiver are met across all conditions, then no further action is needed. If the receiver input signal requirements are not met, then a max HDMI pixel clock rate of 177MHz should be applied.
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0