| NA | i862: Reset Should Use PORz | Yes | Yes |
| i864: VDDS18V to VDDSHVn Current Path | Yes | Yes |
| i931: VDD to VDDA_"PHY" Current Path | Yes | Yes |
| CAMSS | i709: CSI-2 Receiver Executes Software Reset Unconditionally | | Yes |
| i904: CSI Interface Setup/Hold Timing Does Not Meet MIPI DPHY Spec above 600MHz | | Yes |
| Control Module | i813: Spurious Thermal Alert Generation When Temperature Remains in Expected Range | Yes | Yes |
| i814: Bandgap Temperature Read Dtemp Can Be Corrupted | Yes | Yes |
| i827: Thermal Alert Will Not Be Generated When Bandgap Is Configured in "Smart Idle" Mode | Yes | Yes |
| i863: MMC2 Has PU/PD Contention Immediately after Release from Reset | Yes | Yes |
| i869: IO Glitches Can Occur When Changing IO Settings | Yes | Yes |
| i870: PCIe Unaligned Read Access Issue | Yes | Yes |
| i885: Software Requirements for Data Manual IO Timing | Yes | Yes |
| i900: SoC Will Hang If Region 5 Accessed While CTRL_CORE_MMR_LOCK_5 Is Locked | Yes | Yes |
| DCAN | i893: DCAN Initialization Sequence | Yes | Yes |
| i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can Hang | Yes | Yes |
| DEBUG | i879: DSP MStandby Requires CD_EMU in SW_WKUP | Yes | Yes |
| DMA | i378: sDMA Channel Is Not Disabled after a Transaction Error | Yes | Yes |
| i698: DMA4 Generates Unexpected Transaction on WR Port | Yes | Yes |
| i699: DMA4 Channel Fails to Continue With Descriptor Load When Pause Bit Is Cleared | Yes | Yes |
| DSP | i872: DSP MFlag Output Not Initialized | Yes | Yes |
| i879: DSP MStandby Requires CD_EMU in SW_WKUP | Yes | Yes |
| i883: DSP Doesn't Wake from Subsystem Internal Interrupts | Yes | Yes |
| i898: DSP Pre-fetch Should Be Disabled before Entering Power Down Mode | Yes | Yes |
| DSS | i596: BITMAP1-2-4 Formats Not Supported by the Graphics Pipeline | Yes | Yes |
| i631: Wrong Access in 1D Burst for YUV4:2:0-NV12 Format | Yes | Yes |
| i641: Overlay Optimization Limitations | Yes | Yes |
| i734: LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled | Yes | Yes |
| i815: Power Management Enhancement Implemented Inside DSS Leads to DSS Underflows | Yes | Yes |
| i829: Reusing Pipe Connected to Writeback Pipeline On-the-Fly to an Active Panel | Yes | Yes |
| i838: DSS BT.656/BT.1120 Max Horizontal Blanking Is Non Compliant | Yes | Yes |
| i839: Some RGB and YUV Formats Have Non-Standard Ordering | Yes | Yes |
| i932: DPLL_VIDEOn May Require Multiple Lock Attempts | Yes | Yes |
| i936: DSS LCD/DPI Out Field Reversal in Interlaced RGB Mode | Yes | Yes |
| EMIF | i727: Refresh Rate Issue after Warm Reset | Yes(1) | Yes(2) |
| i729: DDR Access Hang after Warm Reset | Yes(1) | Yes(2) |
| i878: MPU Lockup With Concurrent DMM and EMIF Accesses | Yes | Yes |
| eMMC/SD/SDIO | i802: MMCHS DCRC Errors During Tuning Procedure | Yes | Yes |
| i803: MMCHS Read Transfer With CMD23 Never Complete When BCE=0 and ADMA Used | Yes | Yes |
| i832: DLL SW Reset Bit Does Not Reset to 0 after Execution | Yes | Yes |
| i834: MMCHS HS200 and SDR104 Command Timeout Window Too Small | Yes | Yes |
| i836: Bus Testing Commands CMD19 Incorrectly Waits for CRC Status Return | Yes | Yes |
| i856: 32k Oscillator Fails to Start-Up at POR | Yes | Yes |
| i863: MMC2 Has PU/PD Contention Immediately after Release from Reset | Yes | Yes |
| i890: MMC1 IOs and PBIAS Must Be Powered-Up before Isolation | Yes | Yes |
| i929: MMC1/2 SDR104/HS200 Mode DLL Delay Value May Result In Unexpected Tuning Pattern Errors | Yes | Yes |
| GMAC_SW | i877: RGMII Clocks Should Be Enabled at Boot Time | Yes | Yes |
| i899: Ethernet DLR Is Not Supported | Yes | Yes |
| i903: Ethernet RMII Interface RMII_MHZ_50_CLK Not Supported as Output Reference Clock | Yes | Yes |
| GPIO | i856: 32k Oscillator Fails to Start-Up at POR | Yes | Yes |
| HDMI | i937: HDMI Transmitter is Marginal to Source Eye Mask Requirements Above 177MHz | Yes | Yes |
| I2C | i694: System I2C Hang Due to Miss of Bus Clear Support | Yes | Yes |
| i833: I2C Module in Multislave Mode Potentially Acknowledges Wrong Address | Yes | Yes |
| i930: I2C1 and I2C2 May Drive Low During Reset | Yes | Yes |
| INTC | i883: DSP Doesn't Wake from Subsystem Internal Interrupts | Yes | Yes |
| Interconnect | i871: L4_PER3 Firewall Initiator ConnID Value Left-Shift 1-Bit | Yes | Yes |
| McASP | i848: McASP IO Pad Loopback Not Functional | Yes | Yes |
| i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can Hang | Yes | Yes |
| MPU | i878: MPU Lockup With Concurrent DMM and EMIF Accesses | Yes | Yes |
|
i940: MPU COUNTER_REALTIME saturates after several
hundred days |
Yes |
Yes |
| PCIe | i870: PCIe Unaligned Read Access Issue | Yes | Yes |
| i909: PCIe Unintentional Translation of Outbound Message TLPs | Yes | Yes |
| i925: PCI-Express Gen2 (5.0 GT/s) Operation Not Supported When Operating Junction Temperature Less than 0 Deg C | Yes | Yes |
| i926: PCIe Preferred PCIe_PHY_RX SCP Register Settings Updated | Yes | Yes |
| i935: MSI Bit in PCIECTRL_TI_CONF_IRQSTATUS_MSI Register Does Not Clear Automatically | Yes | Yes |
| PRCM | i810: DPLL Controller Can Get Stuck While Transitioning to a Power Saving State | Yes | Yes |
| i826: HSDIVIDER1 CLKOUT4 Could Glitch During On-the-Fly Divider Change to/from Divide-by-2.5 | Yes | Yes |
| i876: DVFS Only Supported on MPU | Yes | Yes |
| i886: FPDLink PLL Unlocks With Certain SoC PLL M/N Values | Yes | Yes |
| i892: L3 Clocks Should Be Enabled at All Times | Yes | Yes |
| PWMSS | i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can Hang | Yes | Yes |
| QSPI | i912: QSPI_SPI_CMD_REG [25:24] Masked from Read in RTL | Yes | Yes |
| i916: QSPI Reads Can Fail For Flash Devices with HOLD Function | Yes | Yes |
| SATA | i782: SATA AHCI Command Issue Order | Yes | Yes |
| i783: SATA Lockup after SATA DPLL Unlock/Relock | Yes | Yes |
| i807: SATA Host Controller Locks Up if PIO Setup FIS Is Received and Bus Busy and Data Request Bits Are Cleared | Yes | Yes |
| i808: SATA Link Locks Up Under Certain Conditions | Yes | Yes |
| i809: SATA Command Does Not Complete and Software Must Issue a Port Reset Under Certain Conditions | Yes | Yes |
| i818: SATA PHY Reset Required Following SATA PLL Unlock | Yes | Yes |
| TIMERS | i767: Delay Needed to Read Some Timer Registers after Wakeup | Yes | Yes |
| i856: 32k Oscillator Fails to Start-Up at POR | Yes | Yes |
| i874: TIMER5/6/7/8 Interrupts Not Propagated | Yes | Yes |
| UART/IrDA/CIR | i202: MDR1 Access Can Freeze UART Module | Yes | Yes |
| i849: UART2_RXD Is Not Working for MUXMODE=0 | Yes | Yes |
| i889: UART Does Not Acknowledge Idle Request after DMA Has Been Enabled | Yes | Yes |
| i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can Hang | Yes | Yes |
| USB | i819: A Device Control Bit Meta-Stability for USB3.0 Controller in USB2.0 Mode | Yes | Yes |
| i820: Unexpected USB Link State Value upon U3 Exit by USB3.0 Link | Yes | Yes |
| i824: USB3.0 Link Cannot Be Established When Suspend Mode Is Enabled | Yes | Yes |
| i845: USB2.0 False Detection of Disconnect Condition | Yes | Yes |
| i896: USB xHCI Port Disable Feature Does Not Work | Yes | Yes |
| i897: USB xHCI Stop Endpoint Command Does Not Work in Certain Circumstances | Yes | Yes |
| VIP | i839: Some RGB and YUV Formats Have Non-Standard Ordering | Yes | Yes |
| VPE | i839: Some RGB and YUV Formats Have Non-Standard Ordering | Yes | Yes |