CRITICALITY

High

DESCRIPTION

An unintended leakage current path between VDDA_PCIE (1.8 V) and VDDA33_USB1 (3.3 V) due to ESD protection diode connection across the signal to I/O supply pads exists. This path can allow current to flow from VDDA_PCIE to VDDA33V_USB1. The current flows whenever the voltage level on VDDA_PCIE exceeds VDDA33V_USB by more than a diode drop during certain power-up and power-down sequences.

This leakage current causes the un-energized VDDA33V_USB1 to rise to a ~1 V plateau (see Figure 4-3) due to the power resource’s “off impedance” seen between the VDDA33V_USB1 power rail to ground. When the minimum “off impedance” is >= 100 Ω, the SoC leakage current is small and sustainable with no SoC reliability impacts.

Figure 4-3 Original Power-Up Sequence

Note: Figure 4-3 shows in VDA_PHY_1V8 rail a plateau approximately 250 mV documented in i931, VDD to VDDA_"PHY" Current Path.

GUIDELINES

TI recommended Power Delivery Networks (PDNs) could have multiple different PMIC LDO power resources connected to the VDDA33V_USB1 rail. The LP87332D/LP873220 PMICs have a minimum OFF resistance equal to 150 Ω so a PDN using these PMICs would not exceed safe leakage current level and could continue to use the original SoC power sequences. However, the TPS65916 PMICs have a minimum OFF resistance equal to 30 Ω and would exceed the safe leakage current limit. As a result, any PDN using TPS65916 PMICs must implement the power sequencing as shown in DM version C or later. The specific sequence changes are:

• For power-up, energize VDDA_PCIE either concurrently or after VDDA33V_USB1
• For power-down, de-energize VDDA_PCIE either concurrently or before VDDA33V_USB1

REVISIONS IMPACTED

AM570x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (17mm): 2.1, 2.0

AM570x: 2.1, 2.0

DRA71x: 2.1, 2.0